arc: Workaround the ARC 600 problem with DEBUG.RA bit

It has been found that in ARC 600 (at least in AXS101) writing RA | IS | SS
will not step instruction, as expected - RA bit mustn't be set. This problem
doesn't happen on other cores or because of other bits in DEBUG. RA is set
by the processor itself and since OpenOCD does read-modify-write of register
when stepping, it is required to explicitly disable RA while stepping.

Signed-off-by: Anton Kolesov <[email protected]>

Author: anthony-kolesov

src/target/arc32.c

@@ -394,6 +394,11 @@ int arc32_config_step(struct target *target, int enable_step)
 			LOG_DEBUG("ARC600 extra single step bit to set.");
 		}
 
+		if (arc32->on_step_reset_debug_ra) {
+			LOG_DEBUG("Resetting DEBUG.RA bit.");
+			value &= ~SET_CORE_RESET_APPLIED; /* Reset the RA bit. */
+		}
+
 		CHECK_RETVAL(arc_jtag_write_aux_reg_one(&arc32->jtag_info, AUX_DEBUG_REG,
 			value));
 		LOG_DEBUG("core debug step mode enabled [debug-reg:0x%08" PRIx32 "]", value);

src/target/arc32.h

@@ -146,6 +146,13 @@ struct arc32_common {
 	/* Whether DEBUG.SS bit is present. This is a unique feature of ARC 600. */
 	bool has_debug_ss;
 
+	/* Workaround for a problem with ARC 600 - writing RA | IS | SS will not
+	 * step an instruction - it must be only a (IS | SS). However RA is set by
+	 * the processor itself and since OpenOCD does read-modify-write of DEBUG
+	 * register when stepping, it is required to explicitly disable RA before
+	 * stepping. */
+	bool on_step_reset_debug_ra;
+
 	/* CCM memory regions (optional). */
 	arc32_address_t iccm0_start;
 	arc32_address_t iccm0_end;

src/target/arc_ocd.c

@@ -160,6 +160,7 @@ int arc_ocd_arc600_target_create(struct target *target, Jim_Interp *interp)
 	struct arc_common *arc = calloc(1, sizeof(struct arc_common));
 
 	arc->arc32.has_debug_ss = true;
+	arc->arc32.on_step_reset_debug_ra = true;
 
 	CHECK_RETVAL(arc_ocd_init_arch_info(target, arc, target->tap));