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Description
Hi dear professor,
It's a great honor to write a message here.
u@u-virtual-machine:~/tools/gitlab-wp/phd1/pin/test$ pin -t /home/u/tools/gitlab-wp/phd1/pin/source/tools/ntua_Computer_Architecture2/obj-intel64/MyPinTool.so -- ./hello
u@u-virtual-machine:~/tools/gitlab-wp/phd1/pin/test$ cat cslab_cache.out
Total Statistics
Total Instructions: 0
Total Cycles: 0
IPC: nan
Single level Tlb hierarchy
Data Tlb:
Entries: 64
Page Size(B): 4096
Associativity: 4
Latencies: 0 50
Tlb-Sets: 16 - LRU - assoc: 4
Tlb Stats:
Tlb-Load-Hits: 0 nan%
Tlb-Load-Misses: 0 nan%
Tlb-Load-Accesses: 0 nan%
Tlb-Store-Hits: 0 nan%
Tlb-Store-Misses: 0 nan%
Tlb-Store-Accesses: 0 nan%
Tlb-Total-Hits: 0 nan%
Tlb-Total-Misses: 0 nan%
Tlb-Total-Accesses: 0 nan%
Two level Cache hierarchy
L1-Data Cache:
Size(KB): 32
Block Size(B): 64
Associativity: 8
L2-Data Cache:
Size(KB): 256
Block Size(B): 64
Associativity: 8
Latencies: 1 10 150
L1-Sets: 64 - LRU - assoc: 8
L2-Sets: 512 - LRU - assoc: 8
Store_allocation: Yes
L2_inclusive: Yes
L2_prefetching: No
L1 Cache Stats:
L1-Load-Hits: 0 nan%
L1-Load-Misses: 0 nan%
L1-Load-Accesses: 0 nan%
L1-Store-Hits: 0 nan%
L1-Store-Misses: 0 nan%
L1-Store-Accesses: 0 nan%
L1-Total-Hits: 0 nan%
L1-Total-Misses: 0 nan%
L1-Total-Accesses: 0 nan%
L2 Cache Stats:
L2-Load-Hits: 0 nan%
L2-Load-Misses: 0 nan%
L2-Load-Accesses: 0 nan%
L2-Store-Hits: 0 nan%
L2-Store-Misses: 0 nan%
L2-Store-Accesses: 0 nan%
L2-Total-Hits: 0 nan%
L2-Total-Misses: 0 nan%
L2-Total-Accesses: 0 nan%
I can't get any information when using ntua_Computer_Architecture2/obj-intel64/MyPinTool.so , pin tool is OK, cause I have tested other programs like instruction count in another file under pin/source/tools/.