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| 1 | +/****************************************************************************** |
| 2 | + * * |
| 3 | + * License Agreement * |
| 4 | + * * |
| 5 | + * Copyright (c) 2006 Altera Corporation, San Jose, California, USA. * |
| 6 | + * All rights reserved. * |
| 7 | + * * |
| 8 | + * Permission is hereby granted, free of charge, to any person obtaining a * |
| 9 | + * copy of this software and associated documentation files (the "Software"), * |
| 10 | + * to deal in the Software without restriction, including without limitation * |
| 11 | + * the rights to use, copy, modify, merge, publish, distribute, sublicense, * |
| 12 | + * and/or sell copies of the Software, and to permit persons to whom the * |
| 13 | + * Software is furnished to do so, subject to the following conditions: * |
| 14 | + * * |
| 15 | + * The above copyright notice and this permission notice shall be included in * |
| 16 | + * all copies or substantial portions of the Software. * |
| 17 | + * * |
| 18 | + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR * |
| 19 | + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, * |
| 20 | + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE * |
| 21 | + * AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER * |
| 22 | + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING * |
| 23 | + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER * |
| 24 | + * DEALINGS IN THE SOFTWARE. * |
| 25 | + * * |
| 26 | + * This agreement shall be governed in all respects by the laws of the State * |
| 27 | + * of California and by the laws of the United States of America. * |
| 28 | + * * |
| 29 | + ******************************************************************************/ |
| 30 | + |
| 31 | +#ifndef __ALTERA_AVALON_FIFO_REGS_H__ |
| 32 | +#define __ALTERA_AVALON_FIFO_REGS_H__ |
| 33 | + |
| 34 | +#include <io.h> |
| 35 | + |
| 36 | +#define ALTERA_AVALON_FIFO_OTHER_INFO_REG 1 |
| 37 | +#define ALTERA_AVALON_FIFO_DATA_REG 0 |
| 38 | + |
| 39 | +#define ALTERA_AVALON_FIFO_LEVEL_REG 0 |
| 40 | +#define ALTERA_AVALON_FIFO_STATUS_REG 1 |
| 41 | +#define ALTERA_AVALON_FIFO_EVENT_REG 2 |
| 42 | +#define ALTERA_AVALON_FIFO_IENABLE_REG 3 |
| 43 | +#define ALTERA_AVALON_FIFO_ALMOSTFULL_REG 4 |
| 44 | +#define ALTERA_AVALON_FIFO_ALMOSTEMPTY_REG 5 |
| 45 | + |
| 46 | +// Read slave |
| 47 | +#define IORD_ALTERA_AVALON_FIFO_DATA(base) \ |
| 48 | + IORD(base, ALTERA_AVALON_FIFO_DATA_REG) |
| 49 | + |
| 50 | +#define IORD_ALTERA_AVALON_FIFO_OTHER_INFO(base) \ |
| 51 | + IORD(base, ALTERA_AVALON_FIFO_OTHER_INFO_REG) |
| 52 | + |
| 53 | +// Write slave |
| 54 | +#define IOWR_ALTERA_AVALON_FIFO_DATA(base, data) \ |
| 55 | + IOWR(base, ALTERA_AVALON_FIFO_DATA_REG, data) |
| 56 | + |
| 57 | +#define IOWR_ALTERA_AVALON_FIFO_OTHER_INFO(base, data) \ |
| 58 | + IOWR(base, ALTERA_AVALON_FIFO_OTHER_INFO_REG, data) |
| 59 | + |
| 60 | +// Control slave |
| 61 | +#define IORD_ALTERA_AVALON_FIFO_LEVEL(base) \ |
| 62 | + IORD(base, ALTERA_AVALON_FIFO_LEVEL_REG) |
| 63 | + |
| 64 | +#define IORD_ALTERA_AVALON_FIFO_STATUS(base) \ |
| 65 | + IORD(base, ALTERA_AVALON_FIFO_STATUS_REG) |
| 66 | + |
| 67 | +#define IORD_ALTERA_AVALON_FIFO_EVENT(base) \ |
| 68 | + IORD(base, ALTERA_AVALON_FIFO_EVENT_REG) |
| 69 | + |
| 70 | +#define IORD_ALTERA_AVALON_FIFO_IENABLE(base) \ |
| 71 | + IORD(base, ALTERA_AVALON_FIFO_IENABLE_REG) |
| 72 | + |
| 73 | +#define IORD_ALTERA_AVALON_FIFO_ALMOSTFULL(base) \ |
| 74 | + IORD(base, ALTERA_AVALON_FIFO_ALMOSTFULL_REG) |
| 75 | + |
| 76 | +#define IORD_ALTERA_AVALON_FIFO_ALMOSTEMPTY(base) \ |
| 77 | + IORD(base, ALTERA_AVALON_FIFO_ALMOSTEMPTY_REG) |
| 78 | + |
| 79 | +#define IOWR_ALTERA_AVALON_FIFO_EVENT(base, data) \ |
| 80 | + IOWR(base, ALTERA_AVALON_FIFO_EVENT_REG, data) |
| 81 | + |
| 82 | +#define IOWR_ALTERA_AVALON_FIFO_IENABLE(base, data) \ |
| 83 | + IOWR(base, ALTERA_AVALON_FIFO_IENABLE_REG, data) |
| 84 | + |
| 85 | +#define IOWR_ALTERA_AVALON_FIFO_ALMOSTFULL(base, data) \ |
| 86 | + IOWR(base, ALTERA_AVALON_FIFO_ALMOSTFULL_REG, data) |
| 87 | + |
| 88 | +#define IOWR_ALTERA_AVALON_FIFO_ALMOSTEMPTY(base, data) \ |
| 89 | + IOWR(base, ALTERA_AVALON_FIFO_ALMOSTEMPTY_REG, data) |
| 90 | + |
| 91 | +#define ALTERA_AVALON_FIFO_EVENT_F_MSK (0x01) |
| 92 | +#define ALTERA_AVALON_FIFO_EVENT_E_MSK (0x02) |
| 93 | +#define ALTERA_AVALON_FIFO_EVENT_AF_MSK (0x04) |
| 94 | +#define ALTERA_AVALON_FIFO_EVENT_AE_MSK (0x08) |
| 95 | +#define ALTERA_AVALON_FIFO_EVENT_OVF_MSK (0x10) |
| 96 | +#define ALTERA_AVALON_FIFO_EVENT_UDF_MSK (0x20) |
| 97 | +#define ALTERA_AVALON_FIFO_EVENT_ALL (0x3F) |
| 98 | + |
| 99 | +#define ALTERA_AVALON_FIFO_STATUS_F_MSK (0x01) |
| 100 | +#define ALTERA_AVALON_FIFO_STATUS_E_MSK (0x02) |
| 101 | +#define ALTERA_AVALON_FIFO_STATUS_AF_MSK (0x04) |
| 102 | +#define ALTERA_AVALON_FIFO_STATUS_AE_MSK (0x08) |
| 103 | +#define ALTERA_AVALON_FIFO_STATUS_OVF_MSK (0x10) |
| 104 | +#define ALTERA_AVALON_FIFO_STATUS_UDF_MSK (0x20) |
| 105 | +#define ALTERA_AVALON_FIFO_STATUS_ALL (0x3F) |
| 106 | + |
| 107 | +#define ALTERA_AVALON_FIFO_IENABLE_F_MSK (0x01) |
| 108 | +#define ALTERA_AVALON_FIFO_IENABLE_E_MSK (0x02) |
| 109 | +#define ALTERA_AVALON_FIFO_IENABLE_AF_MSK (0x04) |
| 110 | +#define ALTERA_AVALON_FIFO_IENABLE_AE_MSK (0x08) |
| 111 | +#define ALTERA_AVALON_FIFO_IENABLE_OVF_MSK (0x10) |
| 112 | +#define ALTERA_AVALON_FIFO_IENABLE_UDF_MSK (0x20) |
| 113 | +#define ALTERA_AVALON_FIFO_IENABLE_ALL (0x3F) |
| 114 | + |
| 115 | +#endif /* __ALTERA_AVALON_FIFO_REGS_H__ */ |
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