diff --git a/content/items/rggen.md b/content/items/rggen.md
index 9f22abcd..c238c2bd 100644
--- a/content/items/rggen.md
+++ b/content/items/rggen.md
@@ -28,6 +28,7 @@ RgGen has following features:
 
 * Generate following source files for CSR automatically from register map specifications
     * SystemVerilog/Verilog RTL
+    * [Veryl](https://veryl-lang.org) RTL
     * VHDL RTL
     * UVM register model (RAL)
     * Markdown documents