From 74366a82cbeef66d53ca65b9508a2adf2f9459fe Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Tue, 24 Jun 2025 13:50:34 -0700 Subject: [PATCH 1/3] add metrics and events for GNR when the fixed tma register isn't available Signed-off-by: Harper, Jason M --- cmd/metrics/event_defs.go | 2 +- cmd/metrics/metric_defs.go | 2 +- .../x86_64/GenuineIntel/gnr_nofixedtma.txt | 214 ++++++++ .../x86_64/GenuineIntel/gnr_nofixedtma.json | 478 ++++++++++++++++++ 4 files changed, 694 insertions(+), 2 deletions(-) create mode 100644 cmd/metrics/resources/events/x86_64/GenuineIntel/gnr_nofixedtma.txt create mode 100644 cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json diff --git a/cmd/metrics/event_defs.go b/cmd/metrics/event_defs.go index b790f921..93e67531 100644 --- a/cmd/metrics/event_defs.go +++ b/cmd/metrics/event_defs.go @@ -43,7 +43,7 @@ func LoadEventGroups(eventDefinitionOverridePath string, metadata Metadata) (gro uarch = strings.Split(uarch, " ")[0] // use alternate events/metrics when TMA fixed counters are not supported alternate := "" - if (uarch == "icx" || uarch == "spr" || uarch == "emr") && !metadata.SupportsFixedTMA { // AWS VM instances + if (uarch == "icx" || uarch == "spr" || uarch == "emr" || uarch == "gnr") && !metadata.SupportsFixedTMA { // AWS/GCP VM instances alternate = "_nofixedtma" } eventFileName := fmt.Sprintf("%s%s.txt", uarch, alternate) diff --git a/cmd/metrics/metric_defs.go b/cmd/metrics/metric_defs.go index a07fd1bd..5fb1b2bb 100644 --- a/cmd/metrics/metric_defs.go +++ b/cmd/metrics/metric_defs.go @@ -43,7 +43,7 @@ func LoadMetricDefinitions(metricDefinitionOverridePath string, selectedMetrics uarch = strings.Split(uarch, " ")[0] // use alternate events/metrics when TMA fixed counters are not supported alternate := "" - if (uarch == "icx" || uarch == "spr" || uarch == "emr") && !metadata.SupportsFixedTMA { + if (uarch == "icx" || uarch == "spr" || uarch == "emr" || uarch == "gnr") && !metadata.SupportsFixedTMA { alternate = "_nofixedtma" } metricFileName := fmt.Sprintf("%s%s.json", uarch, alternate) diff --git a/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr_nofixedtma.txt b/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr_nofixedtma.txt new file mode 100644 index 00000000..9789f048 --- /dev/null +++ b/cmd/metrics/resources/events/x86_64/GenuineIntel/gnr_nofixedtma.txt @@ -0,0 +1,214 @@ +# GraniteRapids event list + +# cpu groups +cpu/event=0x51,umask=0x01,period=100003,name='L1D.REPLACEMENT'/, # 0,1,2,3 +cpu/event=0x24,umask=0xe4,period=200003,name='L2_RQSTS.ALL_CODE_RD'/, # 0,1,2,3 +cpu/event=0xd1,umask=0x01,period=1000003,name='MEM_LOAD_RETIRED.L1_HIT'/, # 0,1,2,3 +cpu/event=0x25,umask=0x1f,period=100003,name='L2_LINES_IN.ALL'/, # 0,1,2,3 +cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, +cpu/event=0xb7,umask=0x02,period=2000003,name='EXE.AMX_BUSY'/, +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xd1,umask=0x10,period=100021,name='MEM_LOAD_RETIRED.L2_MISS'/, # 0,1,2,3 +cpu/event=0x24,umask=0x24,period=200003,name='L2_RQSTS.CODE_RD_MISS'/, # 0,1,2,3 +cpu/event=0x11,umask=0x0e,period=100003,name='ITLB_MISSES.WALK_COMPLETED'/, # 0,1,2,3 +cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, # 0,1,2,3 +cpu/event=0xa6,umask=0x40,cmask=0x02,period=1000003,name='EXE_ACTIVITY.BOUND_ON_STORES'/, +cpu/event=0xa6,umask=0x21,cmask=0x05,period=2000003,name='EXE_ACTIVITY.BOUND_ON_LOADS'/, +cpu/event=0xad,umask=0x10,period=1000003,name='INT_MISC.UOP_DROPPING'/, +cpu/event=0xad,umask=0x40,period=1000003,name='INT_MISC.UNKNOWN_BRANCH_CYCLES'/, # [*] +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xe5,umask=0x03,period=1000003,name='MEM_UOP_RETIRED.ANY'/, +cpu/event=0xc0,umask=0x10,period=2000003,name='INST_RETIRED.MACRO_FUSED'/, +cpu/event=0xc4,umask=0x00,period=400009,name='BR_INST_RETIRED.ALL_BRANCHES'/, +cpu/event=0xc5,umask=0x00,period=400009,name='BR_MISP_RETIRED.ALL_BRANCHES'/, +cpu/event=0x12,umask=0x0e,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED'/, # 0,1,2,3 +cpu/event=0x12,umask=0x04,period=100003,name='DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M'/, # 0,1,2,3 +cpu/event=0x13,umask=0x0e,period=100003,name='DTLB_STORE_MISSES.WALK_COMPLETED'/, # 0,1,2,3 +cpu/event=0xd1,umask=0x02,period=200003,name='MEM_LOAD_RETIRED.L2_HIT'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x47,umask=0x09,cmask=0x09,period=1000003,name='MEMORY_ACTIVITY.STALLS_L3_MISS'/, # 0,1,2,3 +cpu/event=0x80,umask=0x04,period=500009,name='ICACHE_DATA.STALLS'/, # 0,1,2,3 +cpu/event=0x83,umask=0x04,period=200003,name='ICACHE_TAG.STALLS'/, # 0,1,2,3 +cpu/event=0xc2,umask=0x02,period=2000003,name='UOPS_RETIRED.SLOTS'/, +cpu/event=0xae,umask=0x01,period=2000003,name='UOPS_ISSUED.ANY'/; +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x47,umask=0x03,cmask=0x03,period=1000003,name='MEMORY_ACTIVITY.STALLS_L1D_MISS'/, # 0,1,2,3 +cpu/event=0x47,umask=0x05,cmask=0x05,period=1000003,name='MEMORY_ACTIVITY.STALLS_L2_MISS'/, # 0,1,2,3 +cpu/event=0x12,umask=0x10,cmask=0x01,period=100003,name='DTLB_LOAD_MISSES.WALK_ACTIVE'/, # 0,1,2,3 +cpu/event=0xa3,umask=0x10,cmask=0x10,period=1000003,name='CYCLE_ACTIVITY.CYCLES_MEM_ANY'/, +cpu/event=0xad,umask=0x80,period=500009,name='INT_MISC.CLEAR_RESTEER_CYCLES'/, +cpu/event=0xec,umask=0x02,period=2000003,name='CPU_CLK_UNHALTED.DISTRIBUTED'/, +cpu/event=0xd1,umask=0x08,period=200003,name='MEM_LOAD_RETIRED.L1_MISS'/, # 0,1,2,3 +cpu/event=0xc2,umask=0x04,period=2000003,name='UOPS_RETIRED.MS'/, # [*] +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1'/, # [*] +cpu/event=0xd0,umask=0x21,period=100007,name='MEM_INST_RETIRED.LOCK_LOADS'/, # 0,1,2,3 +cpu/event=0xd0,umask=0x82,period=1000003,name='MEM_INST_RETIRED.ALL_STORES'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xc2,umask=0x04,cmask=0x01,period=2000003,name='UOPS_RETIRED.MS:c1:e1'/, # [*] +cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x8003C0001,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD'/, # 0,1,2,3 +cpu/event=0x2b,umask=0x01,period=100003,offcore_rsp=0x10003C0002,name='OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM'/, # 0,1,2,3 +cpu/event=0x20,umask=0x04,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO'/, # 0,1,2,3 +cpu/event=0xd1,umask=0x40,period=100007,name='MEM_LOAD_RETIRED.FB_HIT'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xd2,umask=0x02,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD'/, # 0,1,2,3 +cpu/event=0xd2,umask=0x04,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD'/, # 0,1,2,3 +cpu/event=0x47,umask=0x02,cmask=0x02,period=1000003,name='MEMORY_ACTIVITY.CYCLES_L1D_MISS'/, # 0,1,2,3 +cpu/event=0xc5,umask=0x50,period=400009,name='BR_MISP_RETIRED.COND_NTAKEN_COST'/, +cpu/event=0xc5,umask=0x41,period=400009,name='BR_MISP_RETIRED.COND_TAKEN_COST'/, +cpu/event=0xc5,umask=0x42,period=400009,name='BR_MISP_RETIRED.INDIRECT_CALL_COST'/, +cpu/event=0xc5,umask=0xc0,period=100003,name='BR_MISP_RETIRED.INDIRECT_COST'/, +cpu/event=0xc5,umask=0x48,period=100007,name='BR_MISP_RETIRED.RET_COST'/, +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x79,umask=0x08,period=2000003,name='IDQ.DSB_UOPS'/, # 0,1,2,3 +cpu/event=0x79,umask=0x04,period=2000003,name='IDQ.MITE_UOPS'/, # 0,1,2,3 +cpu/event=0x79,umask=0x20,period=1000003,name='IDQ.MS_UOPS'/, # 0,1,2,3 +cpu/event=0xa8,umask=0x01,period=2000003,name='LSD.UOPS'/, +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x1030004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM'/, # 0,1,2,3 +cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x830004477,name='OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD'/, # 0,1,2,3 +cpu/event=0xb0,umask=0x09,cmask=0x01,period=1000003,name='ARITH.DIV_ACTIVE'/, +cpu/event=0xa2,umask=0x02,period=100003,name='RESOURCE_STALLS.SCOREBOARD'/, +cpu/event=0xec,umask=0x20,period=2000003,name='CPU_CLK_UNHALTED.C02'/, +cpu-cycles:k, +ref-cycles:k, +instructions:k; + +cpu/event=0x87,umask=0x01,period=500009,name='DECODE.LCP'/, # 0,1,2,3 +cpu/event=0x61,umask=0x02,period=100003,name='DSB2MITE_SWITCHES.PENALTY_CYCLES'/, # 0,1,2,3 +cpu/event=0x79,umask=0x04,cmask=0x01,period=2000003,name='IDQ.MITE_CYCLES_ANY'/, # 0,1,2,3 +cpu/event=0x79,umask=0x04,cmask=0x06,period=2000003,name='IDQ.MITE_CYCLES_OK'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x79,umask=0x08,cmask=0x01,period=2000003,name='IDQ.DSB_CYCLES_ANY'/, # 0,1,2,3 +cpu/event=0x79,umask=0x08,cmask=0x06,period=2000003,name='IDQ.DSB_CYCLES_OK'/, # 0,1,2,3 +cpu/event=0x79,umask=0x20,cmask=0x01,period=2000003,name='IDQ.MS_CYCLES_ANY'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xad,umask=0x01,cmask=0x01,period=500009,name='INT_MISC.CLEARS_COUNT'/, +cpu/event=0xc3,umask=0x01,cmask=0x01,period=100003,name='MACHINE_CLEARS.COUNT'/, +cpu/event=0xc3,umask=0x02,period=100003,name='MACHINE_CLEARS.MEMORY_ORDERING'/, +cpu/event=0xd0,umask=0x09,period=100003,name='MEM_INST_RETIRED.STLB_HIT_LOADS'/, # 0,1,2,3 +cpu/event=0x03,umask=0x82,period=100003,name='LD_BLOCKS.STORE_FORWARD'/, # 0,1,2,3 +cpu/event=0xd0,umask=0x81,period=1000003,name='MEM_INST_RETIRED.ALL_LOADS'/, # 0,1,2,3 +cpu/event=0xd0,umask=0x41,period=100003,name='MEM_INST_RETIRED.SPLIT_LOADS'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x48,umask=0x01,period=1000003,name='L1D_PEND_MISS.PENDING'/, # 0,1,2,3 +cpu/event=0x43,umask=0xfd,period=1000003,name='MEM_LOAD_COMPLETED.L1_MISS_ANY'/, # 0,1,2,3 +cpu/event=0x48,umask=0x02,period=1000003,name='L1D_PEND_MISS.FB_FULL'/, # 0,1,2,3 +cpu/event=0xd2,umask=0x01,period=20011,name='MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS'/, # 0,1,2,3 +cpu/event=0x9c,umask=0x01,period=1000003,name='IDQ_BUBBLES.CORE'/, +cpu/event=0x9c,umask=0x01,cmask=0x06,period=1000003,name='IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE'/; +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xa4,umask=0x01,period=10000003,name='TOPDOWN.SLOTS_P'/, +cpu/event=0xa4,umask=0x02,period=10000003,name='TOPDOWN.BACKEND_BOUND_SLOTS'/, +cpu/event=0xa4,umask=0x08,period=10000003,name='TOPDOWN.BR_MISPREDICT_SLOTS'/, # 0 +cpu/event=0xa4,umask=0x10,period=10000003,name='TOPDOWN.MEMORY_BOUND_SLOTS'/, +cpu/event=0xc2,umask=0x01,period=2000003,name='UOPS_RETIRED.HEAVY'/, +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0xd1,umask=0x04,period=100021,name='MEM_LOAD_RETIRED.L3_HIT'/, # 0,1,2,3 +cpu/event=0x2d,umask=0x01,cmask=0x01,period=1000003,name='XQ.FULL_CYCLES'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x48,umask=0x04,period=1000003,name='L1D_PEND_MISS.L2_STALLS'/, # 0,1,2,3 +cpu/event=0x44,umask=0x01,period=200003,name='MEM_STORE_RETIRED.L2_HIT'/, # 0,1,2,3 +cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x103b800002,name='OCR.DEMAND_RFO.L3_MISS'/, # 0,1,2,3 +cpu/event=0xd0,umask=0x42,period=100003,name='MEM_INST_RETIRED.SPLIT_STORES'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x10800,name='OCR.STREAMING_WR.ANY_RESPONSE'/, # 0,1,2,3 +cpu/event=0xd0,umask=0x0a,period=100003,name='MEM_INST_RETIRED.STLB_HIT_STORES'/, # 0,1,2,3 +cpu/event=0x13,umask=0x10,cmask=0x01,period=100003,name='DTLB_STORE_MISSES.WALK_ACTIVE'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +cpu/event=0x2a,umask=0x01,period=100003,offcore_rsp=0x1030004477,name='OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM'/, # 0,1,2,3 +cpu/event=0x20,umask=0x08,cmask=0x01,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD'/, # 0,1,2,3 +cpu/event=0x20,umask=0x08,cmask=0x04,period=1000003,name='OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4'/, # 0,1,2,3 +cpu-cycles, +ref-cycles, +instructions; + +# upi groups +upi/event=0x02,umask=0x0f,name='UNC_UPI_TxL_FLITS.ALL_DATA'/; # 0,1,2,3 + +# cha groups +cha/event=0x35,umask=0xc80ffe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_CRD'/, # 0,1,2,3 +cha/event=0x35,umask=0xc8177e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE'/, # 0,1,2,3 +cha/event=0x36,umask=0xc8177e01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE'/; # 0 + +cha/event=0x35,umask=0xc816fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL'/, # 0,1,2,3 +cha/event=0x36,umask=0xc816fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL'/, # 0 +cha/event=0x35,umask=0xc896fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL'/, # 0,1,2,3 +cha/event=0x35,umask=0xc8977e01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE'/; # 0,1,2,3 + +cha/event=0x35,umask=0xccd7fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA'/, # 0,1,2,3 +cha/event=0x35,umask=0xc817fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD'/, # 0,1,2,3 +cha/event=0x35,umask=0xc897fe01,name='UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF'/, # 0,1,2,3 +cha/event=0x36,umask=0xc817fe01,name='UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD'/; # 0 + +cha/event=0x35,umask=0xc8f3ff04,name='UNC_CHA_TOR_INSERTS.IO_PCIRDCUR'/, # 0,1,2,3 +cha/event=0x35,umask=0xcc43ff04,name='UNC_CHA_TOR_INSERTS.IO_ITOM'/, # 0,1,2,3 +cha/event=0x35,umask=0xcd43ff04,name='UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR'/, # 0,1,2,3 +cha/event=0x01,umask=0x00,name='UNC_CHA_CLOCKTICKS'/; # 0,1,2,3 + +# imc groups +imc/event=0x05,umask=0xcf,name='UNC_M_CAS_COUNT_SCH0.RD'/, # 0,1,2,3 +imc/event=0x06,umask=0xcf,name='UNC_M_CAS_COUNT_SCH1.RD'/, # 0,1,2,3 +imc/event=0x05,umask=0xf0,name='UNC_M_CAS_COUNT_SCH0.WR'/, # 0,1,2,3 +imc/event=0x06,umask=0xf0,name='UNC_M_CAS_COUNT_SCH1.WR'/; # 0,1,2,3 + +# cstate_core groups +cstate_core/c6-residency/; + +# cstate_pkg groups +cstate_pkg/c6-residency/; + +# power groups +power/energy-pkg/, +power/energy-ram/; diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json new file mode 100644 index 00000000..996cfa8c --- /dev/null +++ b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json @@ -0,0 +1,478 @@ +[ + { + "name": "CPU operating frequency (in GHz)", + "expression": "([cpu-cycles] / [ref-cycles] * [SYSTEM_TSC_FREQ]) / 1000000000" + }, + { + "name": "CPU utilization %", + "expression": "100 * [ref-cycles] / [TSC]" + }, + { + "name": "CPU utilization% in kernel mode", + "expression": "100 * [ref-cycles:k] / [TSC]" + }, + { + "name": "CPI", + "expression": "[cpu-cycles] / [instructions]" + }, + { + "name": "cycles per txn", + "expression": "[cpu-cycles] / [TXN]" + }, + { + "name": "kernel_CPI", + "expression": "[cpu-cycles:k] / [instructions:k]" + }, + { + "name": "kernel_cycles per txn", + "expression": "[cpu-cycles:k] / [TXN]" + }, + { + "name": "IPC", + "expression": "[instructions] / [cpu-cycles]" + }, + { + "name": "txn per cycle", + "expression": "[TXN] / [cpu-cycles]" + }, + { + "name": "giga_instructions_per_sec", + "expression": "[instructions] / 1000000000" + }, + { + "name": "branch misprediction ratio", + "expression": "[BR_MISP_RETIRED.ALL_BRANCHES] / [BR_INST_RETIRED.ALL_BRANCHES]" + }, + { + "name": "locks retired per instr", + "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [instructions]" + }, + { + "name": "locks retired per txn", + "expression": "[MEM_INST_RETIRED.LOCK_LOADS] / [TXN]" + }, + { + "name": "L1D MPI (includes data+rfo w/ prefetches)", + "expression": "[L1D.REPLACEMENT] / [instructions]" + }, + { + "name": "L1D misses per txn (includes data+rfo w/ prefetches)", + "expression": "[L1D.REPLACEMENT] / [TXN]" + }, + { + "name": "L1D demand data read hits per instr", + "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [instructions]" + }, + { + "name": "L1D demand data read hits per txn", + "expression": "[MEM_LOAD_RETIRED.L1_HIT] / [TXN]" + }, + { + "name": "L1-I code read misses (w/ prefetches) per instr", + "expression": "[L2_RQSTS.ALL_CODE_RD] / [instructions]" + }, + { + "name": "L1I code read misses (includes prefetches) per txn", + "expression": "[L2_RQSTS.ALL_CODE_RD] / [TXN]" + }, + { + "name": "L2 demand data read hits per instr", + "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [instructions]" + }, + { + "name": "L2 demand data read hits per txn", + "expression": "[MEM_LOAD_RETIRED.L2_HIT] / [TXN]" + }, + { + "name": "L2 MPI (includes code+data+rfo w/ prefetches)", + "expression": "[L2_LINES_IN.ALL] / [instructions]" + }, + { + "name": "L2 misses per txn (includes code+data+rfo w/ prefetches)", + "expression": "[L2_LINES_IN.ALL] / [TXN]" + }, + { + "name": "L2 demand data read MPI", + "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [instructions]" + }, + { + "name": "L2 demand data read misses per txn", + "expression": "[MEM_LOAD_RETIRED.L2_MISS] / [TXN]" + }, + { + "name": "L2 demand code MPI", + "expression": "[L2_RQSTS.CODE_RD_MISS] / [instructions]" + }, + { + "name": "L2 demand code misses per txn", + "expression": "[L2_RQSTS.CODE_RD_MISS] / [TXN]" + }, + { + "name": "LLC code read MPI (demand+prefetch)", + "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [instructions]" + }, + { + "name": "LLC code read (demand+prefetch) misses per txn", + "expression": "[UNC_CHA_TOR_INSERTS.IA_MISS_CRD] / [TXN]" + }, + { + "name": "LLC data read MPI (demand+prefetch)", + "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [instructions]" + }, + { + "name": "LLC data read (demand+prefetch) misses per txn", + "expression": "([UNC_CHA_TOR_INSERTS.IA_MISS_LLCPREFDATA] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF]) / [TXN]" + }, + { + "name": "LLC total HITM (per instr) (excludes LLC prefetches)", + "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [instructions]" + }, + { + "name": "LLC total HITM per txn (excludes LLC prefetches)", + "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HITM] / [TXN]" + }, + { + "name": "LLC total HIT clean line forwards (per instr) (excludes LLC prefetches)", + "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [instructions]" + }, + { + "name": "LLC total HIT clean line forwards per txn (excludes LLC prefetches)", + "expression": "[OCR.READS_TO_CORE.REMOTE_CACHE.SNOOP_HIT_WITH_FWD] / [TXN]" + }, + { + "name": "Average LLC demand data read miss latency (in ns)", + "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" + }, + { + "name": "Average LLC demand data read miss latency for LOCAL requests (in ns)", + "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_LOCAL] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL]) / ([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" + }, + { + "name": "Average LLC demand data read miss latency for REMOTE requests (in ns)", + "expression": "1000000000 * ([UNC_CHA_TOR_OCCUPANCY.IA_MISS_DRD_REMOTE] / [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE]) / ([UNC_CHA_CLOCKTICKS]/([CHAS_PER_SOCKET] * [SOCKET_COUNT]))" + }, + { + "name": "UPI Data transmit BW (MB/sec) (only data)", + "expression": "[UNC_UPI_TxL_FLITS.ALL_DATA] * (64/9.0) / 1000000" + }, + { + "name": "package power (watts)", + "expression": "[power/energy-pkg/]" + }, + { + "name": "DRAM power (watts)", + "expression": "[power/energy-ram/]" + }, + { + "name": "core c6 residency %", + "expression": "100 * [cstate_core/c6-residency/] / [TSC]" + }, + { + "name": "package c6 residency %", + "expression": "100 * [cstate_pkg/c6-residency/] * [CORES_PER_SOCKET] / [TSC]" + }, + { + "name": "% Uops delivered from decoded Icache (DSB)", + "expression": "100 * ([IDQ.DSB_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]))" + }, + { + "name": "% Uops delivered from legacy decode pipeline (MITE)", + "expression": "100 * ([IDQ.MITE_UOPS] / ([IDQ.DSB_UOPS] + [IDQ.MITE_UOPS] + [IDQ.MS_UOPS] + [LSD.UOPS]))" + }, + { + "name": "memory bandwidth read (MB/sec)", + "expression": "([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD]) * 64 / 1000000" + }, + { + "name": "memory bandwidth write (MB/sec)", + "expression": "([UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000" + }, + { + "name": "memory bandwidth total (MB/sec)", + "expression": "([UNC_M_CAS_COUNT_SCH0.RD] + [UNC_M_CAS_COUNT_SCH1.RD] + [UNC_M_CAS_COUNT_SCH0.WR] + [UNC_M_CAS_COUNT_SCH1.WR]) * 64 / 1000000" + }, + { + "name": "ITLB (2nd level) MPI", + "expression": "[ITLB_MISSES.WALK_COMPLETED] / [instructions]" + }, + { + "name": "ITLB (2nd level) misses per txn", + "expression": "[ITLB_MISSES.WALK_COMPLETED] / [TXN]" + }, + { + "name": "DTLB (2nd level) load MPI", + "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [instructions]" + }, + { + "name": "DTLB (2nd level) load misses per txn", + "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED] / [TXN]" + }, + { + "name": "DTLB (2nd level) 2MB large page load MPI", + "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [instructions]" + }, + { + "name": "DTLB (2nd level) 2MB large page load misses per txn", + "expression": "[DTLB_LOAD_MISSES.WALK_COMPLETED_2M_4M] / [TXN]" + }, + { + "name": "DTLB (2nd level) store MPI", + "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [instructions]" + }, + { + "name": "DTLB (2nd level) store misses per txn", + "expression": "[DTLB_STORE_MISSES.WALK_COMPLETED] / [TXN]" + }, + { + "name": "NUMA %_Reads addressed to local DRAM", + "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" + }, + { + "name": "NUMA %_Reads addressed to remote DRAM", + "expression": "100 * ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE]) / ([UNC_CHA_TOR_INSERTS.IA_MISS_DRD_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_LOCAL] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_REMOTE] + [UNC_CHA_TOR_INSERTS.IA_MISS_DRD_PREF_REMOTE])" + }, + { + "name": "uncore frequency GHz", + "expression": "([UNC_CHA_CLOCKTICKS] / ([CHAS_PER_SOCKET] * [SOCKET_COUNT]) / 1000000000) / 1" + }, + { + "name": "IO_bandwidth_disk_or_network_writes (MB/sec)", + "expression": "([UNC_CHA_TOR_INSERTS.IO_PCIRDCUR] * 64 / 1000000) / 1" + }, + { + "name": "IO_bandwidth_disk_or_network_reads (MB/sec)", + "expression": "(([UNC_CHA_TOR_INSERTS.IO_ITOM] + [UNC_CHA_TOR_INSERTS.IO_ITOMCACHENEAR]) * 64 / 1000000) / 1" + }, + { + "name": "TMA_Frontend_Bound(%)", + "expression": "100 * ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] )" + }, + { + "name": "TMA_..Fetch_Latency(%)", + "expression": "100 * ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] )" + }, + { + "name": "TMA_....ICache_Misses(%)", + "expression": "100 * ( [ICACHE_DATA.STALLS] / [cpu-cycles] )" + }, + { + "name": "TMA_....ITLB_Misses(%)", + "expression": "100 * ( [ICACHE_TAG.STALLS] / [cpu-cycles] )" + }, + { + "name": "TMA_....Branch_Resteers(%)", + "expression": "100 * ( [INT_MISC.CLEAR_RESTEER_CYCLES] / [cpu-cycles] + ( [INT_MISC.UNKNOWN_BRANCH_CYCLES] / [cpu-cycles] ) )" + }, + { + "name": "TMA_....MS_Switches(%)", + "expression": "100 * ( ( 3 ) * [UOPS_RETIRED.MS:c1:e1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) / [cpu-cycles] )" + }, + { + "name": "TMA_....LCP(%)", + "expression": "100 * ( [DECODE.LCP] / [cpu-cycles] )" + }, + { + "name": "TMA_....DSB_Switches(%)", + "expression": "100 * ( [DSB2MITE_SWITCHES.PENALTY_CYCLES] / [cpu-cycles] )" + }, + { + "name": "TMA_..Fetch_Bandwidth(%)", + "expression": "100 * ( max( 0 , ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) - ( ( [IDQ_BUBBLES.CYCLES_0_UOPS_DELIV.CORE] * ( 6 ) - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) ) )" + }, + { + "name": "TMA_....MITE(%)", + "expression": "100 * ( ( [IDQ.MITE_CYCLES_ANY] - [IDQ.MITE_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) / 2 )" + }, + { + "name": "TMA_....DSB(%)", + "expression": "100 * ( ( [IDQ.DSB_CYCLES_ANY] - [IDQ.DSB_CYCLES_OK] ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) / 2 )" + }, + { + "name": "TMA_....MS(%)", + "expression": "100 * ( max( [IDQ.MS_CYCLES_ANY] , [UOPS_RETIRED.MS:c1] / ( [UOPS_RETIRED.SLOTS] / [UOPS_ISSUED.ANY] ) ) / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) / 2 )" + }, + { + "name": "TMA_Bad_Speculation(%)", + "expression": "100 * ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) )" + }, + { + "name": "TMA_..Branch_Mispredicts(%)", + "expression": "100 * ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] )" + }, + { + "name": "TMA_....Cond_NT_Mispredicts(%)", + "expression": "100 * ( ( [BR_MISP_RETIRED.COND_NTAKEN_COST] * [BR_MISP_RETIRED.COND_NTAKEN_COST:retire_latency] ) / [cpu-cycles] )" + }, + { + "name": "TMA_....Cond_TK_Mispredicts(%)", + "expression": "100 * ( ( [BR_MISP_RETIRED.COND_TAKEN_COST] * [BR_MISP_RETIRED.COND_TAKEN_COST:retire_latency] ) / [cpu-cycles] )" + }, + { + "name": "TMA_....Ind_Call_Mispredicts(%)", + "expression": "100 * ( ( [BR_MISP_RETIRED.INDIRECT_CALL_COST] * [BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency] ) / [cpu-cycles] )" + }, + { + "name": "TMA_....Ind_Jump_Mispredicts(%)", + "expression": "100 * ( max( ( ( [BR_MISP_RETIRED.INDIRECT_COST] * [BR_MISP_RETIRED.INDIRECT_COST:retire_latency] ) - ( [BR_MISP_RETIRED.INDIRECT_CALL_COST] * [BR_MISP_RETIRED.INDIRECT_CALL_COST:retire_latency] ) ) / [cpu-cycles] , 0 ) )" + }, + { + "name": "TMA_....Ret_Mispredicts(%)", + "expression": "100 * ( ( [BR_MISP_RETIRED.RET_COST] * [BR_MISP_RETIRED.RET_COST:retire_latency] ) / [cpu-cycles] )" + }, + { + "name": "TMA_....Other_Mispredicts(%)", + "expression": "max( ( 100 * ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] ) ) * ( 1 - [BR_MISP_RETIRED.ALL_BRANCHES] / ( [INT_MISC.CLEARS_COUNT] - [MACHINE_CLEARS.COUNT] ) ) , 0.0001 )" + }, + { + "name": "TMA_..Machine_Clears(%)", + "expression": "100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) ) - ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] ) ) )" + }, + { + "name": "TMA_....Other_Nukes(%)", + "expression": "max ( ( 100 * ( max( 0 , ( max( 1 - ( ( ( [IDQ_BUBBLES.CORE] - [INT_MISC.UOP_DROPPING] ) / [TOPDOWN.SLOTS_P] ) + ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) + ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] ) ) , 0 ) ) - ( [TOPDOWN.BR_MISPREDICT_SLOTS] / [TOPDOWN.SLOTS_P] ) ) ) ) * ( 1 - [MACHINE_CLEARS.MEMORY_ORDERING] / [MACHINE_CLEARS.COUNT] ), 0.0001 )" + }, + { + "name": "TMA_Backend_Bound(%)", + "expression": "100 * ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )" + }, + { + "name": "TMA_..Memory_Bound(%)", + "expression": "100 * ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] )" + }, + { + "name": "TMA_....L1_Bound(%)", + "expression": "100 * ( max( ( [EXE_ACTIVITY.BOUND_ON_LOADS] - [MEMORY_ACTIVITY.STALLS_L1D_MISS] ) / [cpu-cycles] , 0 ) )" + }, + { + "name": "TMA_......DTLB_Load(%)", + "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.STLB_HIT_LOADS] * [MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency] ) , [MEM_INST_RETIRED.STLB_HIT_LOADS] * ( 7 ) ) if ( [MEM_INST_RETIRED.STLB_HIT_LOADS:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.STLB_HIT_LOADS] * ( 7 ) ) ) / [cpu-cycles] + ( [DTLB_LOAD_MISSES.WALK_ACTIVE] / [cpu-cycles] ) )" + }, + { + "name": "TMA_......Store_Fwd_Blk(%)", + "expression": "100 * ( 13 * [LD_BLOCKS.STORE_FORWARD] / [cpu-cycles] )" + }, + { + "name": "TMA_......L1_Latency_Dependency(%)", + "expression": "100 * ( min( 2 * ( [MEM_INST_RETIRED.ALL_LOADS] - [MEM_LOAD_RETIRED.FB_HIT] - [MEM_LOAD_RETIRED.L1_MISS] ) * 20 / 100 , max( [CYCLE_ACTIVITY.CYCLES_MEM_ANY] - [MEMORY_ACTIVITY.CYCLES_L1D_MISS] , 0 ) ) / [cpu-cycles] )" + }, + { + "name": "TMA_......Lock_Latency(%)", + "expression": "100 * ( ( [MEM_INST_RETIRED.LOCK_LOADS] * [MEM_INST_RETIRED.LOCK_LOADS:retire_latency] ) / [cpu-cycles] )" + }, + { + "name": "TMA_......Split_Loads(%)", + "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.SPLIT_LOADS] * [MEM_INST_RETIRED.SPLIT_LOADS:retire_latency] ) , [MEM_INST_RETIRED.SPLIT_LOADS] * ( [L1D_PEND_MISS.PENDING] / [MEM_LOAD_COMPLETED.L1_MISS_ANY] ) ) if ( [MEM_INST_RETIRED.SPLIT_LOADS:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.SPLIT_LOADS] * ( [L1D_PEND_MISS.PENDING] / [MEM_LOAD_COMPLETED.L1_MISS_ANY] ) ) ) / [cpu-cycles] )" + }, + { + "name": "TMA_......FB_Full(%)", + "expression": "100 * ( [L1D_PEND_MISS.FB_FULL] / [cpu-cycles] )" + }, + { + "name": "TMA_....L2_Bound(%)", + "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L1D_MISS] - [MEMORY_ACTIVITY.STALLS_L2_MISS] ) / [cpu-cycles] )" + }, + { + "name": "TMA_....L3_Bound(%)", + "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L2_MISS] - [MEMORY_ACTIVITY.STALLS_L3_MISS] ) / [cpu-cycles] )" + }, + { + "name": "TMA_......Contested_Accesses(%)", + "expression": "100 * ( ( ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_MISS] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) + ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 81 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 81 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / [cpu-cycles] )" + }, + { + "name": "TMA_......Data_Sharing(%)", + "expression": "100 * ( ( ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_NO_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) + ( min( ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] ) , [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD:retire_latency] >= 0 ) else ( [MEM_LOAD_L3_HIT_RETIRED.XSNP_FWD] * ( 79 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( 1 - ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] / ( [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HITM] + [OCR.DEMAND_DATA_RD.L3_HIT.SNOOP_HIT_WITH_FWD] ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / [cpu-cycles] )" + }, + { + "name": "TMA_......L3_Hit_Latency(%)", + "expression": "100 * ( ( min( ( [MEM_LOAD_RETIRED.L3_HIT] * [MEM_LOAD_RETIRED.L3_HIT:retire_latency] ) , [MEM_LOAD_RETIRED.L3_HIT] * ( 37 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) if ( [MEM_LOAD_RETIRED.L3_HIT:retire_latency] >= 0 ) else ( [MEM_LOAD_RETIRED.L3_HIT] * ( 37 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) - ( 4.4 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) ) ) * ( 1 + ( [MEM_LOAD_RETIRED.FB_HIT] / [MEM_LOAD_RETIRED.L1_MISS] ) / 2 ) / [cpu-cycles] )" + }, + { + "name": "TMA_......SQ_Full(%)", + "expression": "100 * ( ( [XQ.FULL_CYCLES] + [L1D_PEND_MISS.L2_STALLS] ) / [cpu-cycles] )" + }, + { + "name": "TMA_....DRAM_Bound(%)", + "expression": "100 * ( ( [MEMORY_ACTIVITY.STALLS_L3_MISS] / [cpu-cycles] ) )" + }, + { + "name": "TMA_......MEM_Bandwidth(%)", + "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / [cpu-cycles] )" + }, + { + "name": "TMA_......MEM_Latency(%)", + "expression": "100 * ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DATA_RD] ) ) / [cpu-cycles] - ( ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.DATA_RD:c4] ) ) / [cpu-cycles] ) )" + }, + { + "name": "TMA_....Store_Bound(%)", + "expression": "100 * ( [EXE_ACTIVITY.BOUND_ON_STORES] / [cpu-cycles] )" + }, + { + "name": "TMA_......Store_Latency(%)", + "expression": "100 * ( ( ( [MEM_STORE_RETIRED.L2_HIT] * ( 10 ) * ( 1 - ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) ) ) + ( 1 - ( [MEM_INST_RETIRED.LOCK_LOADS] / [MEM_INST_RETIRED.ALL_STORES] ) ) * ( min( [cpu-cycles] , [OFFCORE_REQUESTS_OUTSTANDING.CYCLES_WITH_DEMAND_RFO] ) ) ) / [cpu-cycles] )" + }, + { + "name": "TMA_......False_Sharing(%)", + "expression": "100 * ( ( ( 170 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) * [OCR.DEMAND_RFO.L3_MISS] + ( 81 * ( ( [cpu-cycles] / [ref-cycles] ) * [SYSTEM_TSC_FREQ] / ( 1000000000 ) / ( ( 1000 / 1000 ) ) ) ) * [OCR.DEMAND_RFO.L3_HIT.SNOOP_HITM] ) / [cpu-cycles] )" + }, + { + "name": "TMA_......Split_Stores(%)", + "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.SPLIT_STORES] * [MEM_INST_RETIRED.SPLIT_STORES:retire_latency] ) , [MEM_INST_RETIRED.SPLIT_STORES] * 1 ) if ( [MEM_INST_RETIRED.SPLIT_STORES:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.SPLIT_STORES] * 1 ) ) / [cpu-cycles] )" + }, + { + "name": "TMA_......Streaming_Stores(%)", + "expression": "100 * ( 9 * [OCR.STREAMING_WR.ANY_RESPONSE] / [cpu-cycles] )" + }, + { + "name": "TMA_......DTLB_Store(%)", + "expression": "100 * ( ( min( ( [MEM_INST_RETIRED.STLB_HIT_STORES] * [MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency] ) , [MEM_INST_RETIRED.STLB_HIT_STORES] * ( 7 ) ) if ( [MEM_INST_RETIRED.STLB_HIT_STORES:retire_latency] >= 0 ) else ( [MEM_INST_RETIRED.STLB_HIT_STORES] * ( 7 ) ) ) / [cpu-cycles] + ( [DTLB_STORE_MISSES.WALK_ACTIVE] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) ) )" + }, + { + "name": "TMA_..Core_Bound(%)", + "expression": "max( 0 , ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) - ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) )" + }, + { + "name": "TMA_....Divider(%)", + "expression": "100 * ( [ARITH.DIV_ACTIVE] / [cpu-cycles] )" + }, + { + "name": "TMA_....Serializing_Operation(%)", + "expression": "100 * ( [RESOURCE_STALLS.SCOREBOARD] / [cpu-cycles] + ( [CPU_CLK_UNHALTED.C02] / [cpu-cycles] ) )" + }, + { + "name": "TMA_....AMX_Busy(%)", + "expression": "100 * ( [EXE.AMX_BUSY] / ( [CPU_CLK_UNHALTED.DISTRIBUTED] if [HYPERTHREADING_ON] else [cpu-cycles] ) )" + }, + { + "name": "TMA_Retiring(%)", + "expression": "100 * ( [UOPS_RETIRED.SLOTS] / [TOPDOWN.SLOTS_P] )" + }, + { + "name": "TMA_..Light_Operations(%)", + "expression": "100 * ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) )" + }, + { + "name": "TMA_....Memory_Operations(%)", + "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [MEM_UOP_RETIRED.ANY] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" + }, + { + "name": "TMA_....Fused_Instructions(%)", + "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * [INST_RETIRED.MACRO_FUSED] / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" + }, + { + "name": "TMA_....Non_Fused_Branches(%)", + "expression": "100 * ( ( max( 0 , ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) - ( [UOPS_RETIRED.HEAVY] / ( [TOPDOWN.SLOTS_P] ) ) ) ) * ( [BR_INST_RETIRED.ALL_BRANCHES] - [INST_RETIRED.MACRO_FUSED] ) / ( ( [UOPS_RETIRED.SLOTS] / ( [TOPDOWN.SLOTS_P] ) ) * ( [TOPDOWN.SLOTS_P] ) ) )" + }, + { + "name": "TMA_..Heavy_Operations(%)", + "expression": "100 * ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] )" + }, + { + "name": "TMA_....Few_Uops_Instructions(%)", + "expression": "max( 0 , ( 100 * ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] ) ) - ( 100 * ( [UOPS_RETIRED.MS] / [TOPDOWN.SLOTS_P] ) ) )" + }, + { + "name": "TMA_....Microcode_Sequencer(%)", + "expression": "100 * ( [UOPS_RETIRED.MS] / [TOPDOWN.SLOTS_P] )" + } +] \ No newline at end of file From 73c4e7a6c6bc2acc17ebe8d86530f31f2805eb98 Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Wed, 25 Jun 2025 07:32:23 -0700 Subject: [PATCH 2/3] fix core bound Signed-off-by: Harper, Jason M --- .../resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json index 996cfa8c..ee2c1ce5 100644 --- a/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json +++ b/cmd/metrics/resources/metrics/x86_64/GenuineIntel/gnr_nofixedtma.json @@ -429,7 +429,7 @@ }, { "name": "TMA_..Core_Bound(%)", - "expression": "max( 0 , ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) - ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) )" + "expression": "100 * max( 0 , ( [TOPDOWN.BACKEND_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) - ( [TOPDOWN.MEMORY_BOUND_SLOTS] / [TOPDOWN.SLOTS_P] ) )" }, { "name": "TMA_....Divider(%)", @@ -469,7 +469,7 @@ }, { "name": "TMA_....Few_Uops_Instructions(%)", - "expression": "max( 0 , ( 100 * ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] ) ) - ( 100 * ( [UOPS_RETIRED.MS] / [TOPDOWN.SLOTS_P] ) ) )" + "expression": "100 * max( 0 , ( [UOPS_RETIRED.HEAVY] / [TOPDOWN.SLOTS_P] ) - ( [UOPS_RETIRED.MS] / [TOPDOWN.SLOTS_P] ) )" }, { "name": "TMA_....Microcode_Sequencer(%)", From 444343d867aba3ca5a949b51eb08dd2c81cbcdea Mon Sep 17 00:00:00 2001 From: "Harper, Jason M" Date: Wed, 25 Jun 2025 07:32:56 -0700 Subject: [PATCH 3/3] remove customized PEBs events for C4 Signed-off-by: Harper, Jason M --- cmd/metrics/event_defs.go | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-) diff --git a/cmd/metrics/event_defs.go b/cmd/metrics/event_defs.go index 93e67531..aade1a14 100644 --- a/cmd/metrics/event_defs.go +++ b/cmd/metrics/event_defs.go @@ -145,9 +145,13 @@ func isCollectableEvent(event EventDefinition, metadata Metadata) bool { } // PEBS events (not supported on GCP c4 VMs) pebsEventNames := []string{"INT_MISC.UNKNOWN_BRANCH_CYCLES", "UOPS_RETIRED.MS"} - if !metadata.SupportsPEBS && slices.Contains(pebsEventNames, event.Name) { - slog.Debug("PEBS events not supported on target", slog.String("event", event.Name)) - return false + if !metadata.SupportsPEBS { + for _, pebsEventName := range pebsEventNames { + if strings.Contains(event.Name, pebsEventName) { + slog.Debug("PEBS events not supported on target", slog.String("event", event.Name)) + return false + } + } } // short-circuit for cpu events that aren't off-core response events if event.Device == "cpu" && !(strings.HasPrefix(event.Name, "OCR") || strings.HasPrefix(event.Name, "OFFCORE_REQUESTS_OUTSTANDING")) {