Change default float controls

By default enable denormals retain and make float to integer conversion
use the same rounding mode as FP operations (RTNE)

Author: mshelego

IGC/VectorCompiler/lib/GenXCodeGen/GenXFloatControl.cpp

@@ -36,7 +36,7 @@ class GenXFloatControl : public FGPassImplInterface, IDMixin<GenXFloatControl> {
 
   bool getFloatControl(Function *F, uint32_t *Val);
 
-  Value *buildCr0Update(Value* V, Instruction *InsertBefore);
+  Value *buildCr0Update(Value *V, Instruction *InsertBefore);
 
 public:
   void releaseMemory() {}
@@ -72,14 +72,21 @@ ModulePass *llvm::createGenXFloatControlWrapperPass() {
 }
 
 bool GenXFloatControl::runOnFunctionGroup(FunctionGroup &FG) {
+  // By default retain all denormals, rounding mode - RTNE (both FPU and float
+  // to integer conversion)
+  DefaultFloatControl = Bits::DoublePrecisionDenorm |
+                        Bits::SinglePrecisionDenorm |
+                        Bits::HalfPrecisionDenorm | Bits::FPToIntRoundingMode;
+
   // By default allow to specify with the attribute only rounding and denorm
   // modes
   Mask = Bits::RoundingMode | Bits::DoublePrecisionDenorm |
-             Bits::SinglePrecisionDenorm | Bits::HalfPrecisionDenorm;
+         Bits::SinglePrecisionDenorm | Bits::HalfPrecisionDenorm;
   const auto *Subtarget = &getAnalysis<TargetPassConfig>()
                                .getTM<GenXTargetMachine>()
                                .getGenXSubtarget();
   if (Subtarget->hasSystolicDenormControl()) {
+    DefaultFloatControl |= Bits::SystolicDenorm;
     Mask |= Bits::SystolicDenorm;
   }
 
@@ -134,9 +141,9 @@ Value *GenXFloatControl::buildCr0Update(Value *V, Instruction *InsertBefore) {
   auto *Or = B.CreateOr(AndOld, AndNew);
   auto *WrR = R.createWrRegion(Cr0, Or, "cr0.0.updated", InsertBefore, DL);
 
-  B.CreateCall(
-      vc::getAnyDeclaration(M, GenXIntrinsic::genx_write_predef_reg, {VTy, VTy}),
-      {Id, WrR});
+  B.CreateCall(vc::getAnyDeclaration(M, GenXIntrinsic::genx_write_predef_reg,
+                                     {VTy, VTy}),
+               {Id, WrR});
 
   return RdR;
 }

IGC/VectorCompiler/test/GenXFloatControl/float_control.ll

@@ -13,7 +13,7 @@
 ; CHECK-NEXT: [[VAR1:[^ ]+]] = call <4 x i32> @llvm.genx.read.predef.reg.v4i32.v4i32(i32 14, <4 x i32> undef)
 ; CHECK-NEXT: [[VAR2:[^ ]+]] = call i32 @llvm.genx.rdregioni.i32.v4i32.i16(<4 x i32> [[VAR1]], i32 0, i32 1, i32 1, i16 0, i32 undef)
 ; CHECK-NEXT: [[VAR3:[^ ]+]] = and i32 [[VAR2]], -1265
-; CHECK-NEXT: [[VAR4:[^ ]+]] = or i32 [[VAR3]], 0
+; CHECK-NEXT: [[VAR4:[^ ]+]] = or i32 [[VAR3]], 1216
 ; CHECK-NEXT: [[VAR5:[^ ]+]] = call <4 x i32> @llvm.genx.wrregioni.v4i32.i32.i16.i1(<4 x i32> [[VAR1]], i32 [[VAR4]], i32 0, i32 1, i32 1, i16 0, i32 undef, i1 true)
 ; CHECK-NEXT: call <4 x i32> @llvm.genx.write.predef.reg.v4i32.v4i32(i32 14, <4 x i32> [[VAR5]])
 define dllexport spir_kernel void @kernel(i32 %arg, i64 %privBase) #0 {