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mmereckiigcbot
mmerecki
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igcbot
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Fix ConstantCoalescing chunk size
Fix a couple of places that produced incorrect chunk sizes in `ConstantCoalescing` pass
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3 files changed

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3 files changed

+96
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‎IGC/Compiler/CISACodeGen/ConstantCoalescing.cpp

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Original file line numberDiff line numberDiff line change
@@ -1792,7 +1792,7 @@ Instruction* ConstantCoalescing::FindOrAddChunkExtract(BufChunk* cov_chunk, uint
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void ConstantCoalescing::AdjustChunk(
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BufChunk* cov_chunk, uint start_adj, uint size_adj, const ExtensionKind &Extension)
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{
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cov_chunk->chunkSize += size_adj;
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cov_chunk->chunkSize = RoundChunkSize(cov_chunk->chunkSize + size_adj, cov_chunk->elementSize);
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cov_chunk->chunkStart -= start_adj;
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// mutateType to change array-size
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Type* originalType = cov_chunk->chunkIO->getType();
@@ -2038,7 +2038,7 @@ void ConstantCoalescing::MoveExtracts(BufChunk* cov_chunk, Instruction* load, ui
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void ConstantCoalescing::EnlargeChunk(BufChunk* cov_chunk, uint size_adj)
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{
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cov_chunk->chunkSize += size_adj;
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cov_chunk->chunkSize = RoundChunkSize(cov_chunk->chunkSize + size_adj, cov_chunk->elementSize);
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// mutateType to change array-size
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Type* originalType = cov_chunk->chunkIO->getType();
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Type* vty = IGCLLVM::FixedVectorType::get(cov_chunk->chunkIO->getType()->getScalarType(), cov_chunk->chunkSize);

‎IGC/Compiler/tests/ConstantCoalescing/ldraw-round-chunk-3vf16-size-adjust-chunk.ll

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Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; REQUIRES: llvm-14-plus
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; RUN: igc_opt --opaque-pointers %s -S -o - -igc-constant-coalescing -instcombine -dce | FileCheck %s --check-prefixes=CHECK
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f80:128:128-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a:64:64-f80:128:128-n8:16:32:64"
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define <3 x half> @f0(i32 %src) {
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entry:
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%buf = inttoptr i32 %src to ptr addrspace(2490373)
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%off = add i32 %src, 4
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%z = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373(ptr addrspace(2490373) %buf, i32 %off, i32 4, i1 false)
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%xy = call <2 x half> @llvm.genx.GenISA.ldraw.indexed.v2f16.p2490373(ptr addrspace(2490373) %buf, i32 %src, i32 4, i1 false)
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%x = extractelement <2 x half> %xy, i32 0
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%y = extractelement <2 x half> %xy, i32 1
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%res.x = insertelement <3 x half> undef, half %x, i32 0
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%res.xy = insertelement <3 x half> %res.x, half %y, i32 1
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%res.xyz = insertelement <3 x half> %res.xy, half %z, i32 2
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ret <3 x half> %res.xyz
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}
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; CHECK-LABEL: define <3 x half> @f0
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; CHECK: [[PTR:%.*]] = inttoptr i32 %src to ptr addrspace(2490373)
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; CHECK: [[CHUNK:%.*]] = call <4 x half> @llvm.genx.GenISA.ldrawvector.indexed.v4f16.p2490373(ptr addrspace(2490373) [[PTR]], i32 %src, i32 4, i1 false)
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; CHECK: [[RESULT:%.*]] = shufflevector <4 x half> [[CHUNK]], <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
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; CHECK: ret <3 x half> [[RESULT]]
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; Function Attrs: argmemonly nounwind readonly willreturn
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declare half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373(ptr addrspace(2490373), i32, i32, i1) argmemonly nounwind readonly willreturn
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declare <2 x half> @llvm.genx.GenISA.ldraw.indexed.v2f16.p2490373(ptr addrspace(2490373), i32, i32, i1) argmemonly nounwind readonly willreturn
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!igc.functions = !{!0}
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!0 = !{ptr @f0, !1}
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!1 = !{!2}
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!2 = !{!"function_type", i32 0}
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‎IGC/Compiler/tests/ConstantCoalescing/ldraw-round-chunk-3vf16-size-enlarge-chunk.ll

+47
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,47 @@
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;=========================== begin_copyright_notice ============================
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;
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; Copyright (C) 2025 Intel Corporation
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;
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; SPDX-License-Identifier: MIT
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;
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;============================ end_copyright_notice =============================
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; REQUIRES: llvm-14-plus
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; RUN: igc_opt --opaque-pointers %s -S -o - -igc-constant-coalescing -instcombine -dce | FileCheck %s --check-prefixes=CHECK
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target datalayout = "e-p:32:32:32-i1:8:8-i8:8:8-i16:16:16-i32:32:32-i64:64:64-f16:16:16-f32:32:32-f64:64:64-f80:128:128-v16:16:16-v24:32:32-v32:32:32-v48:64:64-v64:64:64-v96:128:128-v128:128:128-v192:256:256-v256:256:256-v512:512:512-v1024:1024:1024-a:64:64-f80:128:128-n8:16:32:64"
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define <3 x half> @f0(i32 %src) {
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entry:
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%buf = inttoptr i32 %src to ptr addrspace(2490373)
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%xy = call <2 x half> @llvm.genx.GenISA.ldraw.indexed.v2f16.p2490373(ptr addrspace(2490373) %buf, i32 %src, i32 4, i1 false)
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%off = add i32 %src, 4
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%z = call half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373(ptr addrspace(2490373) %buf, i32 %off, i32 4, i1 false)
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%x = extractelement <2 x half> %xy, i32 0
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%y = extractelement <2 x half> %xy, i32 1
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%res.x = insertelement <3 x half> undef, half %x, i32 0
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%res.xy = insertelement <3 x half> %res.x, half %y, i32 1
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%res.xyz = insertelement <3 x half> %res.xy, half %z, i32 2
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ret <3 x half> %res.xyz
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}
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; CHECK-LABEL: define <3 x half> @f0
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; CHECK: [[PTR:%.*]] = inttoptr i32 %src to ptr addrspace(2490373)
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; CHECK: [[CHUNK:%.*]] = call <4 x half> @llvm.genx.GenISA.ldrawvector.indexed.v4f16.p2490373(ptr addrspace(2490373) [[PTR]], i32 %src, i32 4, i1 false)
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; CHECK: [[RESULT:%.*]] = shufflevector <4 x half> [[CHUNK]], <4 x half> undef, <3 x i32> <i32 0, i32 1, i32 2>
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; CHECK: ret <3 x half> [[RESULT]]
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; Function Attrs: argmemonly nounwind readonly willreturn
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declare half @llvm.genx.GenISA.ldraw.indexed.f16.p2490373(ptr addrspace(2490373), i32, i32, i1) argmemonly nounwind readonly willreturn
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declare <2 x half> @llvm.genx.GenISA.ldraw.indexed.v2f16.p2490373(ptr addrspace(2490373), i32, i32, i1) argmemonly nounwind readonly willreturn
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!igc.functions = !{!0}
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!0 = !{ptr @f0, !1}
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!1 = !{!2}
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!2 = !{!"function_type", i32 0}
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