VCVTDQ2PD & VCVTUDQ2PD: allow evex.b=1 (ignored rounding/sae) and fix VL

   * part of  #233

(cherry picked from commit 0fb6f8655cf67c9b59e0b7cf7048e22d989f9a84)

Author: mjcharne

datafiles/avx512-skx/skx-isa.xed.txt

@@ -2471,7 +2471,7 @@ ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX MXCSR 
-PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
+PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1  NOEVSR  FIX_ROUND_LEN512() AVX512_ROUND()  
 OPERANDS:    REG0=ZMM_R3():w:zi64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zf64
 IFORM:       VCVTQQ2PD_ZMMi64_MASKmskw_ZMMf64_AVX512
 }
@@ -3455,7 +3455,7 @@ ISA_SET:     AVX512DQ_512
 EXCEPTIONS:     AVX512-E2
 REAL_OPCODE: Y
 ATTRIBUTES:  MASKOP_EVEX MXCSR 
-PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] FIX_ROUND_LEN512() AVX512_ROUND()  W1  NOEVSR 
+PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn] W1  NOEVSR  FIX_ROUND_LEN512() AVX512_ROUND()  
 OPERANDS:    REG0=ZMM_R3():w:zf64:TXT=ROUNDC REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=ZMM_B3():r:zu64
 IFORM:       VCVTUQQ2PD_ZMMf64_MASKmskw_ZMMu64_AVX512
 }

datafiles/avx512f/avx512-foundation-isa.xed.txt

@@ -796,6 +796,10 @@ ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
 IFORM:       VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512
+COMMENT:  ignores rc/sae. need to adjust VL to 512
+PATTERN:    EVV 0xE6 VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn]   W0  NOEVSR  FIX_ROUND_LEN512()
+OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:i32
+IFORM:       VCVTDQ2PD_ZMMf64_MASKmskw_YMMi32_AVX512
 }
 
 {
@@ -2440,6 +2444,10 @@ ATTRIBUTES:  MASKOP_EVEX
 PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=0 REG[rrr] RM[nnn]  VL512  W0  NOEVSR 
 OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
 IFORM:       VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512
+COMMENT:  ignores rc/sae. need to adjust VL to 512
+PATTERN:    EVV 0x7A VF3 V0F MOD[0b11] MOD=3 BCRC=1 REG[rrr] RM[nnn]  W0  NOEVSR  FIX_ROUND_LEN512()  
+OPERANDS:    REG0=ZMM_R3():w:zf64 REG1=MASK1():r:mskw:TXT=ZEROSTR REG2=YMM_B3():r:qq:u32
+IFORM:       VCVTUDQ2PD_ZMMf64_MASKmskw_YMMu32_AVX512
 }
 
 {