Skip to content

Commit d1d9ad3

Browse files
mjcharnemarkcharney
mjcharne
authored and
markcharney
committed
AMD XOP: VGPRy_R, VGPRy_B. Use VGPR32_[RB] for correct modal behavior.
 * needed to ignore upper 8 regs when in 32b mode. * use VGPR32_B and VGPR32_R for correct 32b mode behavior of AMD XOP instr. * Add&use VGPRy_R and VGPRy_B for correct 32/64b mode behavior of AMD XOP. * #233 (cherry picked from commit 1dd63ff3cf987057016ca354f10facb206fec102)
1 parent b263f4a commit d1d9ad3

File tree

2 files changed

+38
-27
lines changed

2 files changed

+38
-27
lines changed

‎datafiles/amd/amdxop/amd-xop-isa.txt

+26-26
Original file line numberDiff line numberDiff line change
@@ -992,14 +992,14 @@ ATTRIBUTES: AMDONLY
992992
FLAGS: MUST [ cf-0 pf-u af-u zf-mod sf-u of-0 ]
993993

994994
PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
995-
OPERANDS: REG0=GPR32_R():w:d MEM0:r:d IMM0:r:d
995+
OPERANDS: REG0=VGPR32_R():w:d MEM0:r:d IMM0:r:d
996996
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[mm] MOD!=3 REG[rrr] RM[nnn] MODRM() UIMM32()
997-
OPERANDS: REG0=GPRy_R():w:y MEM0:r:y IMM0:r:d
997+
OPERANDS: REG0=VGPRy_R():w:y MEM0:r:y IMM0:r:d
998998

999999
PATTERN: XOPV 0x10 VNP not64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
1000-
OPERANDS: REG0=GPR32_R():w:d REG1=GPR32_B():r:d IMM0:r:d
1000+
OPERANDS: REG0=VGPR32_R():w:d REG1=VGPR32_B():r:d IMM0:r:d
10011001
PATTERN: XOPV 0x10 VNP mode64 VL128 NOVSR XMAPA MOD[0b11] MOD=3 REG[rrr] RM[nnn] UIMM32()
1002-
OPERANDS: REG0=GPRy_R():w:y REG1=GPRy_B():r:y IMM0:r:d
1002+
OPERANDS: REG0=VGPRy_R():w:y REG1=VGPRy_B():r:y IMM0:r:d
10031003
}
10041004

10051005
{
@@ -1018,9 +1018,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MOD
10181018
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
10191019

10201020
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
1021-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1021+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
10221022
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
1023-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1023+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
10241024
}
10251025

10261026
{
@@ -1039,9 +1039,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b010] RM[nnn] MOD
10391039
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
10401040

10411041
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
1042-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1042+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
10431043
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b010] RM[nnn]
1044-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1044+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
10451045
}
10461046

10471047
{
@@ -1060,9 +1060,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b011] RM[nnn] MOD
10601060
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
10611061

10621062
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
1063-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1063+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
10641064
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b011] RM[nnn]
1065-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1065+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
10661066
}
10671067

10681068
{
@@ -1081,9 +1081,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b100] RM[nnn] MOD
10811081
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
10821082

10831083
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
1084-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1084+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
10851085
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b100] RM[nnn]
1086-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1086+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
10871087
}
10881088

10891089
{
@@ -1102,9 +1102,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b101] RM[nnn] MOD
11021102
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
11031103

11041104
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
1105-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1105+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
11061106
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b101] RM[nnn]
1107-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1107+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
11081108
}
11091109

11101110
{
@@ -1123,9 +1123,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MOD
11231123
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
11241124

11251125
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
1126-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1126+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
11271127
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
1128-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1128+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
11291129
}
11301130

11311131
{
@@ -1144,9 +1144,9 @@ PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b111] RM[nnn] MOD
11441144
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
11451145

11461146
PATTERN: XOPV 0x01 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
1147-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1147+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
11481148
PATTERN: XOPV 0x01 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b111] RM[nnn]
1149-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1149+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
11501150
}
11511151

11521152
{
@@ -1165,9 +1165,9 @@ PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b001] RM[nnn] MOD
11651165
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
11661166

11671167
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
1168-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1168+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
11691169
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
1170-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1170+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
11711171
}
11721172

11731173
{
@@ -1186,9 +1186,9 @@ PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[mm] MOD!=3 REG[0b110] RM[nnn] MOD
11861186
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:y
11871187

11881188
PATTERN: XOPV 0x02 VNP not64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
1189-
OPERANDS: REG0=VGPR32_N():w:d REG1=GPR32_B():r:d
1189+
OPERANDS: REG0=VGPR32_N():w:d REG1=VGPR32_B():r:d
11901190
PATTERN: XOPV 0x02 VNP mode64 VL128 XMAP9 MOD[0b11] MOD=3 REG[0b110] RM[nnn]
1191-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPRy_B():r:y
1191+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPRy_B():r:y
11921192
}
11931193

11941194
{
@@ -1200,7 +1200,7 @@ EXTENSION: XOP
12001200
ATTRIBUTES: AMDONLY
12011201

12021202
PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b000] RM[nnn]
1203-
OPERANDS: REG0=GPRy_B():w:y
1203+
OPERANDS: REG0=VGPRy_B():w:y
12041204
}
12051205

12061206
{
@@ -1212,7 +1212,7 @@ EXTENSION: XOP
12121212
ATTRIBUTES: AMDONLY
12131213

12141214
PATTERN: XOPV 0x12 VNP VL128 NOVSR XMAP9 MOD[0b11] MOD=3 REG[0b001] RM[nnn]
1215-
OPERANDS: REG0=GPRy_B():w:y
1215+
OPERANDS: REG0=VGPRy_B():w:y
12161216
}
12171217

12181218
{
@@ -1229,7 +1229,7 @@ PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b000] RM[nnn] MODRM() U
12291229
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d
12301230

12311231
PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b000] RM[nnn] UIMM32()
1232-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d
1232+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d
12331233
}
12341234

12351235
{
@@ -1244,5 +1244,5 @@ PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[mm] MOD!=3 REG[0b001] RM[nnn] MODRM() UI
12441244
OPERANDS: REG0=VGPRy_N():w:y MEM0:r:d IMM0:r:d
12451245

12461246
PATTERN: XOPV 0x12 VNP VL128 XMAPA MOD[0b11] MOD=3 REG[0b001] RM[nnn] UIMM32()
1247-
OPERANDS: REG0=VGPRy_N():w:y REG1=GPR32_B():r:y IMM0:r:d
1247+
OPERANDS: REG0=VGPRy_N():w:y REG1=VGPR32_B():r:y IMM0:r:d
12481248
}

‎datafiles/hswbmi/hsw-reg-table.txt

+12-1
Original file line numberDiff line numberDiff line change
@@ -16,7 +16,18 @@
1616
#
1717
#END_LEGAL
1818

19-
# VGPRy_N is used by AMD XOP only but the lower level stuff is used by HSW NI
19+
# VGPRy_N, VGPRy_B, and VGPRy_R are used by AMD XOP.
20+
# Only but the lower level stuff is used by HSW NI.
21+
22+
xed_reg_enum_t VGPRy_R()::
23+
EOSZ=1 | OUTREG=VGPR32_R()
24+
EOSZ=2 | OUTREG=VGPR32_R()
25+
EOSZ=3 | OUTREG=VGPR64_R()
26+
27+
xed_reg_enum_t VGPRy_B()::
28+
EOSZ=1 | OUTREG=VGPR32_B()
29+
EOSZ=2 | OUTREG=VGPR32_B()
30+
EOSZ=3 | OUTREG=VGPR64_B()
2031

2132
xed_reg_enum_t VGPRy_N()::
2233
EOSZ=1 | OUTREG=VGPR32_N()

0 commit comments

Comments
 (0)