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rflags reported as 32 bits wide when decoding "in eax, 0x3" instruction #320

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xusheng6 opened this issue Jan 22, 2024 · 2 comments
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accepted bug upcoming release A fix/support will be available with the upcoming external release

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@xusheng6
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$ obj/wkit/examples/obj/xed-ex1 -64 e503
Attempting to decode: e5 03 
iclass IN	category IO	ISA-extension BASE	ISA-set I86
instruction-length 2
operand-width 32
effective-operand-width 32
effective-address-width 64
stack-address-width 64
iform-enum-name IN_OeAX_IMMb
iform-enum-name-dispatch (zero based) 3
iclass-max-iform-dispatch 4
Nominal opcode position 0
Nominal opcode 0xe5
Operands
#   TYPE               DETAILS        VIS  RW       OC2 BITS BYTES NELEM ELEMSZ   ELEMTYPE   REGCLASS
#   ====               =======        ===  ==       === ==== ===== ===== ======   ========   ========
0   REG0              REG0=EAX   IMPLICIT   W         V   32     4     1     32        INT        GPR
1   IMM0               0x3(8b)   EXPLICIT   R         B    8     1     1      8       UINT    INVALID
2   REG1           REG1=RFLAGS SUPPRESSED   R         Y   32     4     1     32        INT      FLAGS
Memory Operands
  MemopBytes = 0
FLAGS:
   reads-rflags iopl-tst 
       read:                          iopl  mask=0x3000
    written:                                mask=0x0
  undefined:                                mask=0x0
ATTRIBUTES: NOTSX SCALABLE 
ISA SET: [I86]
@kkhalail
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Thanks for your report.
A fix will be available with the upcoming external release.

@marjevan marjevan added the upcoming release A fix/support will be available with the upcoming external release label Apr 1, 2024
@marjevan
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marjevan commented Apr 3, 2024

Solved this in 6d87b54

@marjevan marjevan closed this as completed Apr 3, 2024
andreas-abel pushed a commit to andreas-abel/XED-to-XML that referenced this issue Mar 23, 2025
This release updates XED according to Intel's latest APX spec (Rev-04), April 2024.
It includes:
  - Remove promoted SHA and KeyLocker EVEX instructions
  - Encoding update for URDMSR/UWRMSR
  - Addition of missing CPUID sensitivity for promoted POPCNT EVEX instruction
  - Update the handling of EVEX.U and reinterpretation to X4


General:
  - Enable a secured build using a new `--security-level` mfile.py knob (1->Medium, 2->High, 3->Highest).
    The default level is 1 (will be raised to 2 in a future release)
    Please expect performance degradation with level 3.
  - Drop the ICC/ICL build options using mfile.py

Add:
  - AMX: Support the restriction of illegal register combination (Solves intelxed#303)
  - Disassembler: Print sequential registers using "+(N-1)" notation
  - Add ENC2 support for Intel APX architecture (TBD: REX2 for EGPR support)
  - Add ENC2 support for KOP instructions

Fix:
  - ISA definition fixes (APX/MOVDIR64B missing operands, Fix CPUID for SYS{ENTER,EXIT}, fix MMX extensions)
  - RFLAGS: Fix width definition and wrong duplicated operands for several instructions (Solves intelxed#320)
  - Fix CPL definition for ENQCMDS (Solves intelxed#311)
  - Fix CPL definition for LGDT (Solves intelxed#312) 
  - Fix CPL definition for VMCALL (Solves intelxed#313)
  - Several bug fixes and improvements for the ENC2 library. 
     For a list of unsupported IFORMS, please check the `enc2_unsupported_ref.json` file.
  - Fix build with the clang built of llvm-project trunk (Solves intelxed#315)
  
Modify:
  - Improve Python code quality 
    (Solves intelxed#314)
    (Solves intelxed#317)


We express our gratitude to all members of the XED community for their valuable contributions.


Co-authored-by: marjevan <marjevan@users.noreply.github.com>
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