From 86266dade5d7f7c61095a2149bd313258443a166 Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Mon, 9 Jul 2018 12:51:43 -0600
Subject: [PATCH 01/13] support of block designs including development boards

---
 ipbb/depparser/VivadoProjectMaker.py | 34 ++++++++++++++++++++++++++--
 1 file changed, 32 insertions(+), 2 deletions(-)

diff --git a/ipbb/depparser/VivadoProjectMaker.py b/ipbb/depparser/VivadoProjectMaker.py
index 1b0ac273..53403986 100644
--- a/ipbb/depparser/VivadoProjectMaker.py
+++ b/ipbb/depparser/VivadoProjectMaker.py
@@ -2,6 +2,8 @@
 import time
 import os
 import collections
+import glob
+import subprocess
 
 from string import Template as tmpl
 
@@ -24,7 +26,8 @@ class VivadoProjectMaker(object):
         '.xci': 'sources_1',
         '.ngc': 'sources_1',
         '.edn': 'sources_1',
-        '.edf': 'sources_1'
+        '.edf': 'sources_1',
+        '.bd': 'sources_1'
         # Legacy ISE files
         # '.ucf': 'ise_1',
         # '.xco': 'ise_1',
@@ -61,6 +64,16 @@ def write(self, aTarget, aScriptVariables, aComponentPaths, aCommandList, aLibs,
             )
         )
 
+        # for block designs of development boards
+        if 'board_part' not in aScriptVariables:
+            pass
+        else:
+            write(
+            'set_property BOARD_PART {board_part} [current_project]'.format(
+                **aScriptVariables
+            )
+        )
+
         write(
             'if {[string equal [get_filesets -quiet constrs_1] ""]} {create_fileset -constrset constrs_1}')
         write(
@@ -95,6 +108,23 @@ def write(self, aTarget, aScriptVariables, aComponentPaths, aCommandList, aLibs,
 
                 lXciBasenames.append(lName)
                 lXciTargetFiles.append(lTargetFile)
+
+            # Support block designs
+            elif lExt == '.bd': # import pdb; pdb.set_trace()
+                
+                fl=glob.glob(lPath+'/*') # delete build artefacts to include recursive submodules
+                fl.remove(lPath+'/'+lBasename) # do not delete the design
+                if os.path.exists(lPath+'/hdl'): # do not delete hdl file if it exists
+                    fl.remove(lPath+'/hdl')
+                for file in fl:
+                    subprocess.Popen(['rm', '-rf', file])
+
+                # hard write to add, open, and close board design
+                write(str('add_files -fileset sources_1 {'+lPath+'/'+lBasename+'}'))
+                write(str('open_bd_design {'+lPath+'/'+lBasename+'}')) # open design to add all submodules
+                write('close_bd_design [current_bd_design]')
+                write(str('generate_target all [get_files '+lPath+'/'+lBasename+']')) # get all submodules
+
             else:
                 if src.Include:
 
@@ -128,7 +158,7 @@ def write(self, aTarget, aScriptVariables, aComponentPaths, aCommandList, aLibs,
         write('set_property top top [current_fileset]')
 
         write('set_property "steps.synth_design.args.flatten_hierarchy" "none" [get_runs synth_1]')
-
+        
         for i in lXciBasenames:
             write('upgrade_ip [get_ips {0}]'.format(i))
         for i in lXciTargetFiles:

From e8fef1c89d5b2b7879c0f0952a131565f3ae7a40 Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Mon, 9 Jul 2018 12:56:31 -0600
Subject: [PATCH 02/13] support of block designs including development boards

---
 ipbb/depparser/VivadoProjectMaker.py | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/ipbb/depparser/VivadoProjectMaker.py b/ipbb/depparser/VivadoProjectMaker.py
index 53403986..9095b36f 100644
--- a/ipbb/depparser/VivadoProjectMaker.py
+++ b/ipbb/depparser/VivadoProjectMaker.py
@@ -158,7 +158,7 @@ def write(self, aTarget, aScriptVariables, aComponentPaths, aCommandList, aLibs,
         write('set_property top top [current_fileset]')
 
         write('set_property "steps.synth_design.args.flatten_hierarchy" "none" [get_runs synth_1]')
-        
+
         for i in lXciBasenames:
             write('upgrade_ip [get_ips {0}]'.format(i))
         for i in lXciTargetFiles:

From 387d6bb0323c34473aecf10fb170771479be64b5 Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Tue, 10 Jul 2018 10:10:27 -0600
Subject: [PATCH 03/13] rm if exsist to enable git folder repo

---
 ipbb/cli/repo.py | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/ipbb/cli/repo.py b/ipbb/cli/repo.py
index f5484ec8..1bb10f5b 100644
--- a/ipbb/cli/repo.py
+++ b/ipbb/cli/repo.py
@@ -76,11 +76,11 @@ def git(env, repo, branch, dest):
     lRepoName = splitext(basename(lUrl.path))[0] if dest is None else dest
     lRepoLocalPath = join(env.work.path, kSourceDir, lRepoName)
 
-    # Check for 
-    if exists(lRepoLocalPath):
-        raise click.ClickException(
-            'Repository already exists \'%s\'' % lRepoLocalPath
-            )
+    # Check for #    import pdb; pdb.set_trace()
+#    if exists(lRepoLocalPath):
+#        raise click.ClickException(
+#            'Repository already exists \'%s\'' % lRepoLocalPath
+#            )
 
     if branch is not None:
         lLsRemote = sh.git('ls-remote', '-h','-t', repo, branch)
@@ -402,4 +402,4 @@ def status(env):
 @srcs.command('find', short_help="Find src files.")
 @click.pass_obj
 def find(env):
-    sh.find(env.srcdir,'-name', '*.vhd', _out=sys.stdout)
\ No newline at end of file
+    sh.find(env.srcdir,'-name', '*.vhd', _out=sys.stdout)

From 6dc2c0c1615b79da08275deffc0d0f0b62f9fffb Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Tue, 10 Jul 2018 10:25:51 -0600
Subject: [PATCH 04/13] glein hack

---
 ipbb/cli/repo.py | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/ipbb/cli/repo.py b/ipbb/cli/repo.py
index 1bb10f5b..15dd68cf 100644
--- a/ipbb/cli/repo.py
+++ b/ipbb/cli/repo.py
@@ -76,7 +76,7 @@ def git(env, repo, branch, dest):
     lRepoName = splitext(basename(lUrl.path))[0] if dest is None else dest
     lRepoLocalPath = join(env.work.path, kSourceDir, lRepoName)
 
-    # Check for #    import pdb; pdb.set_trace()
+    # Check for #glein: #    import pdb; pdb.set_trace()
 #    if exists(lRepoLocalPath):
 #        raise click.ClickException(
 #            'Repository already exists \'%s\'' % lRepoLocalPath
@@ -122,7 +122,7 @@ def git(env, repo, branch, dest):
     if dest is not None:
         lArgs += [dest]
 
-    sh.git(*lArgs, _out=sys.stdout, _cwd=env.srcdir)
+    sh.git(*lArgs)#glein: , _out=sys.stdout, _cwd=env.srcdir)
 
     if branch is not None:
 

From 2a6dfac520ceef04bf53766284059c717e219bb4 Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Tue, 10 Jul 2018 15:21:52 -0600
Subject: [PATCH 05/13] add check for .git extension

---
 ipbb/cli/repo.py | 18 +++++++++++-------
 1 file changed, 11 insertions(+), 7 deletions(-)

diff --git a/ipbb/cli/repo.py b/ipbb/cli/repo.py
index 15dd68cf..35e6fefc 100644
--- a/ipbb/cli/repo.py
+++ b/ipbb/cli/repo.py
@@ -72,15 +72,19 @@ def git(env, repo, branch, dest):
     # Maybe not necessary
 
     lUrl = urlparse(repo)
-    # Strip '.git' at the end
-    lRepoName = splitext(basename(lUrl.path))[0] if dest is None else dest
+    # Strip '.git' at the end if it exists, this supports git in a folder
+    if 'git' in lUrl.path:
+        lRepoName = splitext(basename(lUrl.path))[0] if dest is None else dest
+    else:
+        lRepoName = lUrl.path if dest is None else dest
+
     lRepoLocalPath = join(env.work.path, kSourceDir, lRepoName)
 
-    # Check for #glein: #    import pdb; pdb.set_trace()
-#    if exists(lRepoLocalPath):
-#        raise click.ClickException(
-#            'Repository already exists \'%s\'' % lRepoLocalPath
-#            )
+    # Check for
+    if exists(lRepoLocalPath):
+        raise click.ClickException(
+            'Repository already exists \'%s\'' % lRepoLocalPath
+            )
 
     if branch is not None:
         lLsRemote = sh.git('ls-remote', '-h','-t', repo, branch)

From 9d8f8bd768ff25248956da8c05fc0bf38f6593e5 Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Wed, 15 Aug 2018 15:56:59 -0600
Subject: [PATCH 06/13] add vivado sim support plus doc

---
 ipbb/cli/vivado.py   | 48 +++++++++++++++++++++++++++++++++++
 vivado_simulation.md | 59 ++++++++++++++++++++++++++++++++++++++++++++
 2 files changed, 107 insertions(+)
 create mode 100644 vivado_simulation.md

diff --git a/ipbb/cli/vivado.py b/ipbb/cli/vivado.py
index 6a1b4f2c..8e0d54f1 100644
--- a/ipbb/cli/vivado.py
+++ b/ipbb/cli/vivado.py
@@ -8,6 +8,7 @@
 import sys
 import sh
 import time
+import re
 
 # Elements
 from os.path import join, split, exists, splitext, abspath, basename
@@ -20,6 +21,8 @@
 from ..depparser.VivadoProjectMaker import VivadoProjectMaker
 from ..tools.xilinx import VivadoOpen, VivadoConsoleError, VivadoSnoozer
 
+# Debugging and testing
+#import pdb; pdb.set_trace()
 
 # ------------------------------------------------------------------------------
 def ensureVivado(env):
@@ -259,6 +262,51 @@ def synth(env, jobs):
     secho("\n{}: Synthesis completed successfully.\n".format(env.currentproj.name), fg='green')
 # ------------------------------------------------------------------------------
 
+# ------------------------------------------------------------------------------
+@vivado.command('sim', short_help='Run the simulation step on the specified dependency.')
+@click.option('-rf', '--run-for', metavar='<time> <unit>',type=(int, str), default=(0,'us'), help = "Specify the duration of the simulation of <time> <unit> in addition to the default 1 us.")
+@click.option('-g', '--GUI-mode', is_flag=True, help = "Show simulation in Vivado interface.")
+@click.pass_obj
+def sim(env, run_for, gui_mode):
+
+	lSessionId = 'sim'
+
+	#print("I got {}, and {}.".format(run_for,gui_mode))
+
+	# Check
+	lVivProjPath = join(env.currentproj.path, 'top', 'top.xpr')
+	if not exists(lVivProjPath):
+		raise click.ClickException("Vivado project %s does not exist" % lVivProjPath, fg='red')
+
+	ensureVivado(env)
+
+    #find the test bench name
+	proj_file = open(lVivProjPath, 'r')
+	proj_file_text = proj_file.read()
+	tb_file = re.search('tb_.+\.',proj_file_text).group(0)
+	tb_file = tb_file[0:len(tb_file) - 1]
+	proj_file.close()
+
+	from ..tools.xilinx import VivadoOpen, VivadoConsoleError
+	try:
+		with VivadoOpen(lSessionId, echo=env.vivadoEcho) as lConsole:
+			lConsole('open_project {}'.format(lVivProjPath)) #open the project in Vivado
+			lConsole('set_property top {} [get_filesets sim_1]'.format(tb_file)) #set the top file
+			lConsole('set_property source_mgmt_mode All [current_project]')
+			lConsole('update_compile_order -fileset sources_1') #update compile order
+			
+			lConsole(["launch_simulation"]) #run the simulation in Vivado for 1000ns
+			if run_for[0] != 0:
+				lConsole('run {}{}'.format(run_for[0],run_for[1])) #extend simulation for time specified
+			lConsole("start_gui" if gui_mode else "") #start GUI when specified
+
+	except VivadoConsoleError as lExc:
+		echoVivadoConsoleError(lExc)
+		raise click.Abort()
+
+	secho("\n{}: Simulation completed successfully.\n".format(env.currentproj.name), fg='green')
+
+# ------------------------------------------------------------------------------
 
 # ------------------------------------------------------------------------------
 @vivado.command('impl', short_help='Run the implementation step on the current project.')
diff --git a/vivado_simulation.md b/vivado_simulation.md
new file mode 100644
index 00000000..016d3f21
--- /dev/null
+++ b/vivado_simulation.md
@@ -0,0 +1,59 @@
+
+
+In case of a library module:
+	#initial checks:
+
+		- Make sure that your library module is in lib/hdl/design
+		- Make sure that the library dependency file is in lib/cfg
+
+	#prepare library module project:
+	#Let us assume we start on the general ipbb project directory
+
+		- Source the ipbb enviroment
+			command: source ../ipbb/env.sh #change the path if necessary
+		- Change directory and make simulation directory
+			commands:
+				cd src/fpga/lib/cfg
+				mkdir sim #if it doesn't exist already
+				cd sim
+		- Create dependency file for the simulation
+			commands:
+				touch $PROJ_NAME.dep (example: touch stub_if.dep)
+			add the original dependency file and the test bench:
+				example content of dependency file:
+					include ../../lib/hdl/cfg/stub_if.dep #dependency
+					src ../../lib/hdl/tb/stub_if/tb_mux64.vhd #test bench
+					#if you need to incorporate an ip-core:
+						example: src ../../framework/hdl/ip/xilinx/ila/ila_0/sim/ila_0.vhd
+		- Source the Vivado build enviroment
+			command: source $VIVADO_PATH_SH
+			example: source /opt/Xilinx/Vivado/2018.2/settings64.sh
+		- Create new simulation project (recommended: $PROJ_NAME_sim) with the simulation dependency file
+			command: ipbb proj create vivado $PROJ_NAME fpga:./ -t $PROJ_PATH
+			example: ipbb proj create vivado stub_if_sim fpga:./ -t ../../lib/cfg/sim/stub_if.dep
+
+	#make the project:
+	#Do this step for any new change in the simulation dependency file.
+
+		- Make the project
+			commands:
+				cd proj/$PROJ_NAME
+				ipbb vivado make-project
+			example:
+				cd proj/stub_if_sim
+				ipbb vivado make-project
+
+	#Simulate your project
+		command: ipbb vivado sim
+
+		To get help in all the options for running this command, use $ipbb vivado sim -h
+		Content of the help:
+			Usage: ipbb vivado sim [OPTIONS]
+
+			Options:
+			  -rf, --run-for <time> <unit>  Specify the duration of the simulation of
+			                                <time> <unit> in addition to the default 1 us.
+			  -g, --GUI-mode                Show simulation in Vivado interface.
+			  -h, --help                    Show this message and exit.
+
+All the changes for the ipbb folder are in the file: ipbb/ipbb/cli/vivado.py(265:312)

From 145d741a8930a28d1cce7617cf1264343736b69f Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Tue, 21 Aug 2018 10:41:58 -0600
Subject: [PATCH 07/13] add intro to doc

---
 vivado_simulation.md | 90 +++++++++++++++++++++++++++++++++-----------
 1 file changed, 67 insertions(+), 23 deletions(-)

diff --git a/vivado_simulation.md b/vivado_simulation.md
index 016d3f21..ec1a5851 100644
--- a/vivado_simulation.md
+++ b/vivado_simulation.md
@@ -1,4 +1,12 @@
+This is the documentations for the Vivado simulation environment. It goes through setting up the environment for libraries modules and full-FPGA designs. It also include documentations for using the simulation and its options.
 
+This is written by
+Musaab Al-Bakry
+mual3221@colorado.edu
+
+Supervised
+Robert Glein
+robert.glein@colorado.edu
 
 In case of a library module:
 	#initial checks:
@@ -19,12 +27,16 @@ In case of a library module:
 		- Create dependency file for the simulation
 			commands:
 				touch $PROJ_NAME.dep (example: touch stub_if.dep)
-			add the original dependency file and the test bench:
+			add the original dependency file, the test bench, and the board information:
 				example content of dependency file:
-					include ../../lib/hdl/cfg/stub_if.dep #dependency
+					include ../../lib/cfg/stub_if.dep #dependency
 					src ../../lib/hdl/tb/stub_if/tb_mux64.vhd #test bench
 					#if you need to incorporate an ip-core:
 						example: src ../../framework/hdl/ip/xilinx/ila/ila_0/sim/ila_0.vhd
+					#For the board information:
+						example:
+							setup ../../framework/cfg/vcu118/settings_vu.tcl
+							include ../../framework/cfg/vcu118/vu9p.dep
 		- Source the Vivado build enviroment
 			command: source $VIVADO_PATH_SH
 			example: source /opt/Xilinx/Vivado/2018.2/settings64.sh
@@ -32,28 +44,60 @@ In case of a library module:
 			command: ipbb proj create vivado $PROJ_NAME fpga:./ -t $PROJ_PATH
 			example: ipbb proj create vivado stub_if_sim fpga:./ -t ../../lib/cfg/sim/stub_if.dep
 
-	#make the project:
-	#Do this step for any new change in the simulation dependency file.
+In case of a full-FPGA design:
+	#initial checks:
+
+		- Make sure that your library module is in framework/hdl/design/$BOARD_NAME
+		- Make sure that the library dependency file is in framework/cfg/$BOARD_NAME
+
+	#prepare library module project:
+	#Let us assume we start on the general ipbb project directory
 
-		- Make the project
+		- Source the ipbb enviroment
+			command: source ../ipbb/env.sh #change the path if necessary
+		- Change directory and make simulation directory
+			commands:
+				cd src/fpga/framework/cfg/vcu118
+				mkdir sim #if it doesn't exist already
+				cd sim
+		- Create dependency file for the simulation
 			commands:
-				cd proj/$PROJ_NAME
-				ipbb vivado make-project
-			example:
-				cd proj/stub_if_sim
-				ipbb vivado make-project
-
-	#Simulate your project
-		command: ipbb vivado sim
-
-		To get help in all the options for running this command, use $ipbb vivado sim -h
-		Content of the help:
-			Usage: ipbb vivado sim [OPTIONS]
-
-			Options:
-			  -rf, --run-for <time> <unit>  Specify the duration of the simulation of
-			                                <time> <unit> in addition to the default 1 us.
-			  -g, --GUI-mode                Show simulation in Vivado interface.
-			  -h, --help                    Show this message and exit.
+				touch $PROJ_NAME.dep (example: touch top_vcu118.dep)
+			add the original dependency file and the test bench:
+				example content of dependency file:
+					include ../../framework/cfg/vcu118/top_vcu118.dep #dependency
+					src ../../framework/hdl/tb/tb_top_vcu118.vhd #test bench
+					#if you need to incorporate an ip-core:
+						example: src ../../framework/hdl/ip/xilinx/ila/ila_0/sim/ila_0.vhd
+		- Source the Vivado build enviroment
+			command: source $VIVADO_PATH_SH
+			example: source /opt/Xilinx/Vivado/2018.2/settings64.sh
+		- Create new simulation project (recommended: $PROJ_NAME_sim) with the simulation dependency file
+			command: ipbb proj create vivado $PROJ_NAME fpga:./ -t $PROJ_PATH
+			example: ipbb proj create vivado vcu118_blink_led_sim fpga:./ -t ../../framework/cfg/vcu118/sim/vcu118_blink_led.dep
+
+make the project:
+Do this step for any new change in the simulation dependency file.
+
+	#Make the project
+		commands:
+			cd proj/$PROJ_NAME
+			ipbb vivado make-project
+		example:
+			cd proj/stub_if_sim
+			ipbb vivado make-project
+
+Simulate your project
+	command: ipbb vivado sim
+
+	To get help in all the options for running this command, use $ipbb vivado sim -h
+	Content of the help:
+		Usage: ipbb vivado sim [OPTIONS]
+
+		Options:
+		  -rf, --run-for <time> <unit>  Specify the duration of the simulation of
+		                                <time> <unit> in addition to the default 1 us.
+		  -g, --GUI-mode                Show simulation in Vivado interface.
+		  -h, --help                    Show this message and exit.
 
 All the changes for the ipbb folder are in the file: ipbb/ipbb/cli/vivado.py(265:312)

From dd7d7b091f35d8978e0d6c2964eb1f94947e84ed Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Tue, 25 Sep 2018 14:32:21 -0600
Subject: [PATCH 08/13] correct vivado sim error

---
 ipbb/cli/vivado.py | 17 ++++++++++++++++-
 1 file changed, 16 insertions(+), 1 deletion(-)

diff --git a/ipbb/cli/vivado.py b/ipbb/cli/vivado.py
index 8e0d54f1..8d225e8e 100644
--- a/ipbb/cli/vivado.py
+++ b/ipbb/cli/vivado.py
@@ -262,6 +262,18 @@ def synth(env, jobs):
     secho("\n{}: Synthesis completed successfully.\n".format(env.currentproj.name), fg='green')
 # ------------------------------------------------------------------------------
 
+# ------------------------------------------------------------------------------
+def getIPCoresCompiled(aConsole, proj):
+	lVivProjPath = proj.path
+	print(lVivProjPath)
+	lIPCoresPath = join(lVivProjPath, 'top', 'top.srcs', 'sources_1', 'ip')
+	for folder in next(os.walk(lIPCoresPath))[1]:
+		if not os.path.isdir(join(lIPCoresPath, folder, 'sim')):
+			secho("Simulation directory does not exist for %s. Compiling the ip-core."%(folder), fg='yellow')
+			aConsole('generate_target all [get_files %s/top/top.srcs/sources_1/ip/%s/%s.xci]' % (lVivProjPath, folder, folder))
+			aConsole('export_ip_user_files -of_objects [get_files %s/top/top.srcs/sources_1/ip/%s/%s.xci] -no_script -sync -force -quiet' % (lVivProjPath,folder,folder))
+			aConsole('export_simulation -of_objects [get_files %s/top/top.srcs/sources_1/ip/%s/%s.xci] -directory %s/top/top.ip_user_files/sim_scripts -ip_user_files_dir %s/top/top.ip_user_files -ipstatic_source_dir %s/top/top.ip_user_files/ipstatic -lib_map_path [list {modelsim=%s/top/top.cache/compile_simlib/modelsim} {questa=%s/top/top.cache/compile_simlib/questa} {ies=%s/top/top.cache/compile_simlib/ies} {xcelium=%s/top/top.cache/compile_simlib/xcelium} {vcs=%s/top/top.cache/compile_simlib/vcs} {riviera=%s/top/top.cache/compile_simlib/riviera}] -use_ip_compiled_libs -force -quiet' %(lVivProjPath, folder, folder, lVivProjPath, lVivProjPath, lVivProjPath, lVivProjPath, lVivProjPath, lVivProjPath, lVivProjPath, lVivProjPath, lVivProjPath))
+
 # ------------------------------------------------------------------------------
 @vivado.command('sim', short_help='Run the simulation step on the specified dependency.')
 @click.option('-rf', '--run-for', metavar='<time> <unit>',type=(int, str), default=(0,'us'), help = "Specify the duration of the simulation of <time> <unit> in addition to the default 1 us.")
@@ -280,7 +292,7 @@ def sim(env, run_for, gui_mode):
 
 	ensureVivado(env)
 
-    #find the test bench name
+	#find the test bench name
 	proj_file = open(lVivProjPath, 'r')
 	proj_file_text = proj_file.read()
 	tb_file = re.search('tb_.+\.',proj_file_text).group(0)
@@ -295,6 +307,9 @@ def sim(env, run_for, gui_mode):
 			lConsole('set_property source_mgmt_mode All [current_project]')
 			lConsole('update_compile_order -fileset sources_1') #update compile order
 			
+			getIPCoresCompiled(lConsole, env.currentproj)
+			
+            #commented for testing
 			lConsole(["launch_simulation"]) #run the simulation in Vivado for 1000ns
 			if run_for[0] != 0:
 				lConsole('run {}{}'.format(run_for[0],run_for[1])) #extend simulation for time specified

From 1815e53e8a84a4d290c3ff17cacf6c284cff2c20 Mon Sep 17 00:00:00 2001
From: musaab <mual3221@colorado.edu>
Date: Thu, 27 Sep 2018 14:13:53 -0600
Subject: [PATCH 09/13] simulation documentation

---
 vivado_simulation.md | 103 +++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 103 insertions(+)
 create mode 100644 vivado_simulation.md

diff --git a/vivado_simulation.md b/vivado_simulation.md
new file mode 100644
index 00000000..ec1a5851
--- /dev/null
+++ b/vivado_simulation.md
@@ -0,0 +1,103 @@
+This is the documentations for the Vivado simulation environment. It goes through setting up the environment for libraries modules and full-FPGA designs. It also include documentations for using the simulation and its options.
+
+This is written by
+Musaab Al-Bakry
+mual3221@colorado.edu
+
+Supervised
+Robert Glein
+robert.glein@colorado.edu
+
+In case of a library module:
+	#initial checks:
+
+		- Make sure that your library module is in lib/hdl/design
+		- Make sure that the library dependency file is in lib/cfg
+
+	#prepare library module project:
+	#Let us assume we start on the general ipbb project directory
+
+		- Source the ipbb enviroment
+			command: source ../ipbb/env.sh #change the path if necessary
+		- Change directory and make simulation directory
+			commands:
+				cd src/fpga/lib/cfg
+				mkdir sim #if it doesn't exist already
+				cd sim
+		- Create dependency file for the simulation
+			commands:
+				touch $PROJ_NAME.dep (example: touch stub_if.dep)
+			add the original dependency file, the test bench, and the board information:
+				example content of dependency file:
+					include ../../lib/cfg/stub_if.dep #dependency
+					src ../../lib/hdl/tb/stub_if/tb_mux64.vhd #test bench
+					#if you need to incorporate an ip-core:
+						example: src ../../framework/hdl/ip/xilinx/ila/ila_0/sim/ila_0.vhd
+					#For the board information:
+						example:
+							setup ../../framework/cfg/vcu118/settings_vu.tcl
+							include ../../framework/cfg/vcu118/vu9p.dep
+		- Source the Vivado build enviroment
+			command: source $VIVADO_PATH_SH
+			example: source /opt/Xilinx/Vivado/2018.2/settings64.sh
+		- Create new simulation project (recommended: $PROJ_NAME_sim) with the simulation dependency file
+			command: ipbb proj create vivado $PROJ_NAME fpga:./ -t $PROJ_PATH
+			example: ipbb proj create vivado stub_if_sim fpga:./ -t ../../lib/cfg/sim/stub_if.dep
+
+In case of a full-FPGA design:
+	#initial checks:
+
+		- Make sure that your library module is in framework/hdl/design/$BOARD_NAME
+		- Make sure that the library dependency file is in framework/cfg/$BOARD_NAME
+
+	#prepare library module project:
+	#Let us assume we start on the general ipbb project directory
+
+		- Source the ipbb enviroment
+			command: source ../ipbb/env.sh #change the path if necessary
+		- Change directory and make simulation directory
+			commands:
+				cd src/fpga/framework/cfg/vcu118
+				mkdir sim #if it doesn't exist already
+				cd sim
+		- Create dependency file for the simulation
+			commands:
+				touch $PROJ_NAME.dep (example: touch top_vcu118.dep)
+			add the original dependency file and the test bench:
+				example content of dependency file:
+					include ../../framework/cfg/vcu118/top_vcu118.dep #dependency
+					src ../../framework/hdl/tb/tb_top_vcu118.vhd #test bench
+					#if you need to incorporate an ip-core:
+						example: src ../../framework/hdl/ip/xilinx/ila/ila_0/sim/ila_0.vhd
+		- Source the Vivado build enviroment
+			command: source $VIVADO_PATH_SH
+			example: source /opt/Xilinx/Vivado/2018.2/settings64.sh
+		- Create new simulation project (recommended: $PROJ_NAME_sim) with the simulation dependency file
+			command: ipbb proj create vivado $PROJ_NAME fpga:./ -t $PROJ_PATH
+			example: ipbb proj create vivado vcu118_blink_led_sim fpga:./ -t ../../framework/cfg/vcu118/sim/vcu118_blink_led.dep
+
+make the project:
+Do this step for any new change in the simulation dependency file.
+
+	#Make the project
+		commands:
+			cd proj/$PROJ_NAME
+			ipbb vivado make-project
+		example:
+			cd proj/stub_if_sim
+			ipbb vivado make-project
+
+Simulate your project
+	command: ipbb vivado sim
+
+	To get help in all the options for running this command, use $ipbb vivado sim -h
+	Content of the help:
+		Usage: ipbb vivado sim [OPTIONS]
+
+		Options:
+		  -rf, --run-for <time> <unit>  Specify the duration of the simulation of
+		                                <time> <unit> in addition to the default 1 us.
+		  -g, --GUI-mode                Show simulation in Vivado interface.
+		  -h, --help                    Show this message and exit.
+
+All the changes for the ipbb folder are in the file: ipbb/ipbb/cli/vivado.py(265:312)

From cf01ba9d4a813fbeb88063ea50a196644c1c6f97 Mon Sep 17 00:00:00 2001
From: musaab <mual3221@colorado.edu>
Date: Tue, 9 Oct 2018 13:10:23 -0600
Subject: [PATCH 10/13] extended vivado simulation by hash check

---
 ipbb/cli/vivado.py   |  29 ++++++++++--
 vivado_simulation.md | 103 -------------------------------------------
 2 files changed, 25 insertions(+), 107 deletions(-)
 delete mode 100644 vivado_simulation.md

diff --git a/ipbb/cli/vivado.py b/ipbb/cli/vivado.py
index 8d225e8e..6de1955e 100644
--- a/ipbb/cli/vivado.py
+++ b/ipbb/cli/vivado.py
@@ -9,6 +9,7 @@
 import sh
 import time
 import re
+import hashlib
 
 # Elements
 from os.path import join, split, exists, splitext, abspath, basename
@@ -278,13 +279,12 @@ def getIPCoresCompiled(aConsole, proj):
 @vivado.command('sim', short_help='Run the simulation step on the specified dependency.')
 @click.option('-rf', '--run-for', metavar='<time> <unit>',type=(int, str), default=(0,'us'), help = "Specify the duration of the simulation of <time> <unit> in addition to the default 1 us.")
 @click.option('-g', '--GUI-mode', is_flag=True, help = "Show simulation in Vivado interface.")
+@click.option('-c', '--iocheck', is_flag=True, help = "Compare simulation output text to the golden output in golden_hash.txt")
 @click.pass_obj
-def sim(env, run_for, gui_mode):
+def sim(env, run_for, gui_mode, iocheck):
 
 	lSessionId = 'sim'
 
-	#print("I got {}, and {}.".format(run_for,gui_mode))
-
 	# Check
 	lVivProjPath = join(env.currentproj.path, 'top', 'top.xpr')
 	if not exists(lVivProjPath):
@@ -300,7 +300,7 @@ def sim(env, run_for, gui_mode):
 	proj_file.close()
 
 	from ..tools.xilinx import VivadoOpen, VivadoConsoleError
-	try:
+	try: #prepare and run simulation
 		with VivadoOpen(lSessionId, echo=env.vivadoEcho) as lConsole:
 			lConsole('open_project {}'.format(lVivProjPath)) #open the project in Vivado
 			lConsole('set_property top {} [get_filesets sim_1]'.format(tb_file)) #set the top file
@@ -319,6 +319,27 @@ def sim(env, run_for, gui_mode):
 		echoVivadoConsoleError(lExc)
 		raise click.Abort()
 
+	if iocheck: #perform check on the textio output and golden output
+		md5 = hashlib.md5()
+		with open("../../src/fpga/framework/hdl/tb/vcu118/golden_hash.txt", 'r') as g:
+			f = open("../../src/fpga/framework/hdl/tb/vcu118/output_text.txt", 'r')
+			md5.update(f.read()) #feed file to md5sum
+			hash_key = md5.hexdigest()
+			for line in g.readlines():
+				if line[0] != '#': #ignore comments in golden_hash.txt
+					vals = line.split(',')
+					if vals[1] == hash_key: #catch matching hash
+						hash_key = True
+						print("Output matched golden output!")
+						break
+
+			if hash_key != True:
+				raise click.ClickException(click.style("Simulation output does not match any golden output.",fg='red'))
+
+		# except Exception as error:
+		# 	print("Error: golden_hash.txt not found")
+		# 	raise click.Abort()
+
 	secho("\n{}: Simulation completed successfully.\n".format(env.currentproj.name), fg='green')
 
 # ------------------------------------------------------------------------------
diff --git a/vivado_simulation.md b/vivado_simulation.md
deleted file mode 100644
index ec1a5851..00000000
--- a/vivado_simulation.md
+++ /dev/null
@@ -1,103 +0,0 @@
-This is the documentations for the Vivado simulation environment. It goes through setting up the environment for libraries modules and full-FPGA designs. It also include documentations for using the simulation and its options.
-
-This is written by
-Musaab Al-Bakry
-mual3221@colorado.edu
-
-Supervised
-Robert Glein
-robert.glein@colorado.edu
-
-In case of a library module:
-	#initial checks:
-
-		- Make sure that your library module is in lib/hdl/design
-		- Make sure that the library dependency file is in lib/cfg
-
-	#prepare library module project:
-	#Let us assume we start on the general ipbb project directory
-
-		- Source the ipbb enviroment
-			command: source ../ipbb/env.sh #change the path if necessary
-		- Change directory and make simulation directory
-			commands:
-				cd src/fpga/lib/cfg
-				mkdir sim #if it doesn't exist already
-				cd sim
-		- Create dependency file for the simulation
-			commands:
-				touch $PROJ_NAME.dep (example: touch stub_if.dep)
-			add the original dependency file, the test bench, and the board information:
-				example content of dependency file:
-					include ../../lib/cfg/stub_if.dep #dependency
-					src ../../lib/hdl/tb/stub_if/tb_mux64.vhd #test bench
-					#if you need to incorporate an ip-core:
-						example: src ../../framework/hdl/ip/xilinx/ila/ila_0/sim/ila_0.vhd
-					#For the board information:
-						example:
-							setup ../../framework/cfg/vcu118/settings_vu.tcl
-							include ../../framework/cfg/vcu118/vu9p.dep
-		- Source the Vivado build enviroment
-			command: source $VIVADO_PATH_SH
-			example: source /opt/Xilinx/Vivado/2018.2/settings64.sh
-		- Create new simulation project (recommended: $PROJ_NAME_sim) with the simulation dependency file
-			command: ipbb proj create vivado $PROJ_NAME fpga:./ -t $PROJ_PATH
-			example: ipbb proj create vivado stub_if_sim fpga:./ -t ../../lib/cfg/sim/stub_if.dep
-
-In case of a full-FPGA design:
-	#initial checks:
-
-		- Make sure that your library module is in framework/hdl/design/$BOARD_NAME
-		- Make sure that the library dependency file is in framework/cfg/$BOARD_NAME
-
-	#prepare library module project:
-	#Let us assume we start on the general ipbb project directory
-
-		- Source the ipbb enviroment
-			command: source ../ipbb/env.sh #change the path if necessary
-		- Change directory and make simulation directory
-			commands:
-				cd src/fpga/framework/cfg/vcu118
-				mkdir sim #if it doesn't exist already
-				cd sim
-		- Create dependency file for the simulation
-			commands:
-				touch $PROJ_NAME.dep (example: touch top_vcu118.dep)
-			add the original dependency file and the test bench:
-				example content of dependency file:
-					include ../../framework/cfg/vcu118/top_vcu118.dep #dependency
-					src ../../framework/hdl/tb/tb_top_vcu118.vhd #test bench
-					#if you need to incorporate an ip-core:
-						example: src ../../framework/hdl/ip/xilinx/ila/ila_0/sim/ila_0.vhd
-		- Source the Vivado build enviroment
-			command: source $VIVADO_PATH_SH
-			example: source /opt/Xilinx/Vivado/2018.2/settings64.sh
-		- Create new simulation project (recommended: $PROJ_NAME_sim) with the simulation dependency file
-			command: ipbb proj create vivado $PROJ_NAME fpga:./ -t $PROJ_PATH
-			example: ipbb proj create vivado vcu118_blink_led_sim fpga:./ -t ../../framework/cfg/vcu118/sim/vcu118_blink_led.dep
-
-make the project:
-Do this step for any new change in the simulation dependency file.
-
-	#Make the project
-		commands:
-			cd proj/$PROJ_NAME
-			ipbb vivado make-project
-		example:
-			cd proj/stub_if_sim
-			ipbb vivado make-project
-
-Simulate your project
-	command: ipbb vivado sim
-
-	To get help in all the options for running this command, use $ipbb vivado sim -h
-	Content of the help:
-		Usage: ipbb vivado sim [OPTIONS]
-
-		Options:
-		  -rf, --run-for <time> <unit>  Specify the duration of the simulation of
-		                                <time> <unit> in addition to the default 1 us.
-		  -g, --GUI-mode                Show simulation in Vivado interface.
-		  -h, --help                    Show this message and exit.
-
-All the changes for the ipbb folder are in the file: ipbb/ipbb/cli/vivado.py(265:312)

From 9a4aa078082576e5982f5627dd34760c38dcff87 Mon Sep 17 00:00:00 2001
From: musaab <mual3221@colorado.edu>
Date: Tue, 9 Oct 2018 14:06:20 -0600
Subject: [PATCH 11/13] added generalization for different boards

---
 ipbb/cli/vivado.py | 21 +++++++++++++--------
 1 file changed, 13 insertions(+), 8 deletions(-)

diff --git a/ipbb/cli/vivado.py b/ipbb/cli/vivado.py
index 6de1955e..3669cde3 100644
--- a/ipbb/cli/vivado.py
+++ b/ipbb/cli/vivado.py
@@ -295,8 +295,12 @@ def sim(env, run_for, gui_mode, iocheck):
 	#find the test bench name
 	proj_file = open(lVivProjPath, 'r')
 	proj_file_text = proj_file.read()
-	tb_file = re.search('tb_.+\.',proj_file_text).group(0)
-	tb_file = tb_file[0:len(tb_file) - 1]
+	tb_path = re.search('[^/]+/tb_.+\.',proj_file_text).group(0)
+
+	tb_path = tb_path[0:len(tb_path) - 1].split('/')
+	board = tb_path[0]
+	tb_file = tb_path[1]
+
 	proj_file.close()
 
 	from ..tools.xilinx import VivadoOpen, VivadoConsoleError
@@ -321,20 +325,21 @@ def sim(env, run_for, gui_mode, iocheck):
 
 	if iocheck: #perform check on the textio output and golden output
 		md5 = hashlib.md5()
-		with open("../../src/fpga/framework/hdl/tb/vcu118/golden_hash.txt", 'r') as g:
-			f = open("../../src/fpga/framework/hdl/tb/vcu118/output_text.txt", 'r')
+		with open("../../src/fpga/framework/hdl/tb/{}/golden_hash.txt".format(board), 'r') as g:
+			f = open("../../src/fpga/framework/hdl/tb/{}/output_text.txt".format(board), 'r')
 			md5.update(f.read()) #feed file to md5sum
 			hash_key = md5.hexdigest()
+			hash_key_check = False
 			for line in g.readlines():
 				if line[0] != '#': #ignore comments in golden_hash.txt
 					vals = line.split(',')
 					if vals[1] == hash_key: #catch matching hash
-						hash_key = True
-						print("Output matched golden output!")
+						hash_key_check = True
+						print("Output matched golden output! Calculated hash is: {}".format(hash_key))
 						break
 
-			if hash_key != True:
-				raise click.ClickException(click.style("Simulation output does not match any golden output.",fg='red'))
+			if hash_key_check != True:
+				raise click.ClickException(click.style("Simulation output does not match any golden output. Calculated hash is: {}".format(hash_key),fg='red'))
 
 		# except Exception as error:
 		# 	print("Error: golden_hash.txt not found")

From 864ab37adc0c53e198cebd125abb7f500e400cef Mon Sep 17 00:00:00 2001
From: musaab <mual3221@colorado.edu>
Date: Thu, 25 Oct 2018 13:33:58 -0600
Subject: [PATCH 12/13] Extended ipb-prog with probe files

---
 ipbb/scripts/programmer.py | 7 ++++---
 ipbb/tools/xilinx.py       | 6 +++---
 2 files changed, 7 insertions(+), 6 deletions(-)

diff --git a/ipbb/scripts/programmer.py b/ipbb/scripts/programmer.py
index 521b9f79..4bd95449 100755
--- a/ipbb/scripts/programmer.py
+++ b/ipbb/scripts/programmer.py
@@ -124,9 +124,10 @@ def _validateDevice(ctx, param, value):
 @vivado.command('program')
 @click.argument('deviceid', callback=_validateDevice)
 @click.argument('bitfile', type=click.Path(exists=True))
-@click.option('-v/-q', 'aVerbosity', default=False)
+@click.option('-p', '--probe', type=click.File(), default=None, help="Probe file")
+@click.option('-v/-q', 'aVerbosity', default=False, help="Turns verbosity on/off. Default is -q (quiet).")
 @click.pass_obj
-def program(obj, deviceid, bitfile, aVerbosity):
+def program(obj, deviceid, bitfile, probe, aVerbosity):
 
     target, device = deviceid
 
@@ -196,7 +197,7 @@ def program(obj, deviceid, bitfile, aVerbosity):
 
         if click.confirm(style("Bitfile {0} will be loaded on {1}.\nDo you want to continue?".format(bitfile, lTarget), fg='yellow')):
             echo("Programming {}".format(lTarget))
-            v.programDevice(device, bitfile)
+            v.programDevice(device, bitfile, probe.name if probe else None)
             echo("Done.")
             secho("{} successfully programmed on {}".format(bitfile, lTarget), fg='green')
         else:
diff --git a/ipbb/tools/xilinx.py b/ipbb/tools/xilinx.py
index 31ac5408..1fce701e 100644
--- a/ipbb/tools/xilinx.py
+++ b/ipbb/tools/xilinx.py
@@ -508,7 +508,7 @@ def getHwDevices(self):
     # --------------------------------------------------------------
 
     # --------------------------------------------------------------
-    def programDevice(self, device, bitfile):
+    def programDevice(self, device, bitfile, probe):
         from os.path import abspath, normpath
 
         bitpath = abspath(normpath(bitfile))
@@ -517,9 +517,9 @@ def programDevice(self, device, bitfile):
 
         self.execute('current_hw_device {0}'.format(device))
         self.execute(
-            'refresh_hw_device -update_hw_probes false [current_hw_device]'
+            'refresh_hw_device -update_hw_probes {} [current_hw_device]'.format("True" if probe else "False")
         )
-        self.execute('set_property PROBES.FILE {{}} [current_hw_device]')
+        self.execute('set_property PROBES.FILE {{{0}}} [current_hw_device]'.format(probe if probe else ""))
         self.execute(
             'set_property PROGRAM.FILE {{{0}}} [current_hw_device]'.format(bitpath)
         )

From d31a0c6409d22333848c1ebe3ebac756e5b681ca Mon Sep 17 00:00:00 2001
From: Robert Glein <robert.glein@colorado.edu>
Date: Wed, 31 Oct 2018 18:59:05 -0600
Subject: [PATCH 13/13] add support for dat files

---
 ipbb/depparser/VivadoProjectMaker.py | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/ipbb/depparser/VivadoProjectMaker.py b/ipbb/depparser/VivadoProjectMaker.py
index 0659c70b..ce6969e3 100644
--- a/ipbb/depparser/VivadoProjectMaker.py
+++ b/ipbb/depparser/VivadoProjectMaker.py
@@ -27,7 +27,8 @@ class VivadoProjectMaker(object):
         '.ngc': 'sources_1',
         '.edn': 'sources_1',
         '.edf': 'sources_1',
-        '.bd': 'sources_1'
+        '.bd': 'sources_1',
+        '.dat': 'sources_1'
         # Legacy ISE files
         # '.ucf': 'ise_1',
         # '.xco': 'ise_1',