Rename wiring.Interface to wiring.PureInterface

Due to Amaranth renaming its Interface class to PureInterface in commit
amaranth-lang/amaranth@0cdcab0
importing anything that uses wiring.Interface fails. This commit introduces
necessary renames to make it compatible with the latest Amaranth.

Internal-tag: [#52252]
Signed-off-by: Krzysztof Obłonczek <[email protected]>

Author: koblonczek

amaranth_soc/csr/bus.py

@@ -10,7 +10,7 @@
 __all__ = ["Element", "Signature", "Interface", "Decoder", "Multiplexer"]
 
 
-class Element(wiring.Interface):
+class Element(wiring.PureInterface):
     class Access(enum.Enum):
         """Register access mode.
 
@@ -138,7 +138,7 @@ def __repr__(self):
     access : :class:`Element.Access`
         Register access mode.
     path : iter(:class:`str`)
-        Path to this CSR interface. Optional. See :class:`wiring.Interface`.
+        Path to this CSR interface. Optional. See :class:`wiring.PureInterface`.
 
     Raises
     ------
@@ -280,7 +280,7 @@ def __repr__(self):
         return f"csr.Signature({self.members!r})"
 
 
-class Interface(wiring.Interface):
+class Interface(wiring.PureInterface):
     """CPU-side CSR interface.
 
     A low-level interface to a set of atomically readable and writable peripheral CSR registers.
@@ -307,7 +307,7 @@ class Interface(wiring.Interface):
     memory_map: :class:`MemoryMap`
         Memory map of the bus. Optional. See :class:`Signature`.
     path : iter(:class:`str`)
-        Path to this CSR interface. Optional. See :class:`wiring.Interface`.
+        Path to this CSR interface. Optional. See :class:`wiring.PureInterface`.
 
     Raises
     ------

amaranth_soc/event.py

@@ -6,7 +6,7 @@
 __all__ = ["Source", "EventMap", "Monitor"]
 
 
-class Source(wiring.Interface):
+class Source(wiring.PureInterface):
     class Trigger(enum.Enum):
         """Event trigger mode."""
         LEVEL = "level"
@@ -110,7 +110,7 @@ def __repr__(self):
     trigger : :class:`Source.Trigger`
         Trigger mode. An event can be edge- or level-triggered by the input line.
     path : iter(:class:`str`)
-        Path to this event source interface. Optional. See :class:`wiring.Interface`.
+        Path to this event source interface. Optional. See :class:`wiring.PureInterface`.
 
     Attributes
     ----------

amaranth_soc/wishbone/bus.py

@@ -235,7 +235,7 @@ def __repr__(self):
         return f"wishbone.Signature({self.members!r})"
 
 
-class Interface(wiring.Interface):
+class Interface(wiring.PureInterface):
     """Wishbone bus interface.
 
     Note that the data width of the underlying memory map of the interface is equal to port
@@ -255,7 +255,7 @@ class Interface(wiring.Interface):
     memory_map: :class:`MemoryMap`
         Memory map of the bus. Optional. See :class:`Signature`.
     path : iter(:class:`str`)
-        Path to this Wishbone interface. Optional. See :class:`wiring.Interface`.
+        Path to this Wishbone interface. Optional. See :class:`wiring.PureInterface`.
 
     Raises
     ------