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0xdaryl0xdaryl
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Merge pull request eclipse-omr#7517 from Spencer-Comin/ordered-opaque
Support opaque and acquire/release memory semantics
2 parents 7c87fb1 + c0c31e8 commit edad43f

37 files changed

+322
-196
lines changed

‎compiler/aarch64/codegen/OMRTreeEvaluator.cpp

+8-19
Original file line numberDiff line numberDiff line change
@@ -6117,7 +6117,8 @@ TR::Register *commonLoadEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic op, i
61176117

61186118
TR::Register *commonLoadEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic op, int32_t size, TR::Register *targetReg, TR::CodeGenerator *cg)
61196119
{
6120-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
6120+
TR::Symbol *sym = node->getSymbolReference()->getSymbol();
6121+
bool needSync = cg->comp()->target().isSMP() && sym->isAtLeastOrStrongerThanAcquireRelease();
61216122

61226123
node->setRegister(targetReg);
61236124
TR::MemoryReference *tempMR = TR::MemoryReference::createWithRootLoadOrStore(cg, node);
@@ -6190,7 +6191,8 @@ OMR::ARM64::TreeEvaluator::aloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
61906191
TR::TreeEvaluator::generateVFTMaskInstruction(cg, node, tempReg);
61916192
}
61926193

6193-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
6194+
TR::Symbol *sym = node->getSymbolReference()->getSymbol();
6195+
bool needSync = cg->comp()->target().isSMP() && sym->isAtLeastOrStrongerThanAcquireRelease();
61946196
if (needSync)
61956197
{
61966198
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ishld);
@@ -6240,16 +6242,7 @@ TR::Register *commonStoreEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic op,
62406242
{
62416243
TR::MemoryReference *tempMR = TR::MemoryReference::createWithRootLoadOrStore(cg, node);
62426244
tempMR->validateImmediateOffsetAlignment(node, size, cg);
6243-
6244-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
6245-
bool lazyVolatile = false;
6246-
if (node->getSymbolReference()->getSymbol()->isShadow() &&
6247-
node->getSymbolReference()->getSymbol()->isOrdered() && cg->comp()->target().isSMP())
6248-
{
6249-
needSync = true;
6250-
lazyVolatile = true;
6251-
}
6252-
6245+
TR::Symbol *sym = node->getSymbolReference()->getSymbol();
62536246
TR::Node *valueChild;
62546247

62556248
if (node->getOpCode().isIndirect())
@@ -6261,7 +6254,7 @@ TR::Register *commonStoreEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic op,
62616254
valueChild = node->getFirstChild();
62626255
}
62636256

6264-
if (needSync)
6257+
if (cg->comp()->target().isSMP() && sym->isAtLeastOrStrongerThanAcquireRelease())
62656258
{
62666259
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ishst);
62676260
}
@@ -6316,13 +6309,9 @@ TR::Register *commonStoreEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic op,
63166309
generateMemSrc1Instruction(cg, op, node, tempMR, cg->evaluate(valueChild));
63176310
}
63186311

6319-
if (needSync)
6312+
if (cg->comp()->target().isSMP() && sym->isVolatile())
63206313
{
6321-
// ordered and lazySet operations will not generate a post-write sync
6322-
if (!lazyVolatile)
6323-
{
6324-
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);
6325-
}
6314+
generateSynchronizationInstruction(cg, TR::InstOpCode::dmb, node, TR::InstOpCode::ish);
63266315
}
63276316

63286317
if (valueChildRoot != NULL)

‎compiler/arm/codegen/FPTreeEvaluator.cpp

+20-14
Original file line numberDiff line numberDiff line change
@@ -1202,7 +1202,8 @@ TR::Register *OMR::ARM::TreeEvaluator::floadEvaluator(TR::Node *node, TR::CodeGe
12021202
trgReg = floatTrgReg;
12031203
}
12041204

1205-
if (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
1205+
if (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() &&
1206+
cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
12061207
{
12071208
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb, node);
12081209
}
@@ -1249,7 +1250,8 @@ TR::Register *OMR::ARM::TreeEvaluator::dloadEvaluator(TR::Node *node, TR::CodeGe
12491250
trgReg = doubleTrgReg;
12501251
}
12511252

1252-
if (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
1253+
if (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() &&
1254+
cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
12531255
{
12541256
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb, node);
12551257
}
@@ -1264,7 +1266,8 @@ TR::Register *OMR::ARM::TreeEvaluator::fstoreEvaluator(TR::Node *node, TR::CodeG
12641266
TR::Register *sourceReg = cg->evaluate(firstChild);
12651267
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 4, cg);
12661268

1267-
if (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
1269+
if (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() &&
1270+
cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
12681271
{
12691272
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb, node);
12701273
}
@@ -1320,7 +1323,8 @@ TR::Register *OMR::ARM::TreeEvaluator::dstoreEvaluator(TR::Node *node, TR::CodeG
13201323
TR::Register *sourceReg = cg->evaluate(firstChild);
13211324
bool isUnresolved = node->getSymbolReference()->isUnresolved();
13221325

1323-
if (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
1326+
if (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() &&
1327+
cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
13241328
{
13251329
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb, node);
13261330
}
@@ -1391,7 +1395,8 @@ TR::Register *OMR::ARM::TreeEvaluator::fstoreiEvaluator(TR::Node *node, TR::Code
13911395
TR::Register *sourceReg = cg->evaluate(secondChild);
13921396
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, 4, cg);
13931397

1394-
if (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
1398+
if (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() &&
1399+
cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
13951400
{
13961401
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb, node);
13971402
}
@@ -1445,7 +1450,8 @@ TR::Register *OMR::ARM::TreeEvaluator::dstoreiEvaluator(TR::Node *node, TR::Code
14451450
TR::Node *secondChild = node->getSecondChild();
14461451
TR::Register *sourceReg = cg->evaluate(secondChild);
14471452

1448-
if (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
1453+
if (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() &&
1454+
cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
14491455
{
14501456
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb, node);
14511457
}
@@ -1882,7 +1888,7 @@ TR::Register *OMR::ARM::TreeEvaluator::i2fEvaluator(TR::Node *node, TR::CodeGene
18821888
(firstChild->getOpCodeValue() == TR::iload || firstChild->getOpCodeValue() == TR::iloadi) &&
18831889
(firstChild->getNumChildren() > 0) &&
18841890
(firstChild->getFirstChild()->getNumChildren() == 1) &&
1885-
!(firstChild->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
1891+
!(firstChild->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP()))
18861892
{
18871893
// Coming from memory, last use. Use flds to save the move
18881894
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(firstChild, 4, cg);
@@ -1935,7 +1941,7 @@ TR::Register *OMR::ARM::TreeEvaluator::i2dEvaluator(TR::Node *node, TR::CodeGene
19351941
(firstChild->getOpCodeValue() == TR::iload || firstChild->getOpCodeValue() == TR::iloadi) &&
19361942
(firstChild->getNumChildren() > 0) &&
19371943
(firstChild->getFirstChild()->getNumChildren() == 1) &&
1938-
!(firstChild->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
1944+
!(firstChild->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP()))
19391945
{
19401946
// Coming from memory, last use
19411947
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(firstChild, 4, cg);
@@ -2007,7 +2013,7 @@ TR::Register *OMR::ARM::TreeEvaluator::f2dEvaluator(TR::Node *node, TR::CodeGene
20072013
(firstChild->getOpCodeValue() == TR::fload || firstChild->getOpCodeValue() == TR::floadi) &&
20082014
(firstChild->getNumChildren() > 0) &&
20092015
(firstChild->getFirstChild()->getNumChildren() == 1) &&
2010-
!(firstChild->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
2016+
!(firstChild->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP()))
20112017
{
20122018
// Coming from memory, last use
20132019
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(firstChild, 4, cg);
@@ -2062,7 +2068,7 @@ TR::Register *OMR::ARM::TreeEvaluator::f2iEvaluator(TR::Node *node, TR::CodeGene
20622068
(firstChild->getOpCodeValue() == TR::fload || firstChild->getOpCodeValue() == TR::floadi) &&
20632069
(firstChild->getNumChildren() > 0) &&
20642070
(firstChild->getFirstChild()->getNumChildren() == 1) &&
2065-
!(firstChild->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
2071+
!(firstChild->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP()))
20662072
{
20672073
// Coming from memory, last use
20682074
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(firstChild, 4, cg);
@@ -2102,7 +2108,7 @@ TR::Register *OMR::ARM::TreeEvaluator::d2iEvaluator(TR::Node *node, TR::CodeGene
21022108
(firstChild->getOpCodeValue() == TR::dload || firstChild->getOpCodeValue() == TR::dloadi) &&
21032109
(firstChild->getNumChildren() > 0) &&
21042110
(firstChild->getFirstChild()->getNumChildren() == 1) &&
2105-
!(firstChild->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
2111+
!(firstChild->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP()))
21062112
{
21072113
// Coming from memory, last use
21082114
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(firstChild, 4, cg);
@@ -2175,7 +2181,7 @@ TR::Register *OMR::ARM::TreeEvaluator::d2fEvaluator(TR::Node *node, TR::CodeGene
21752181
(firstChild->getOpCodeValue() == TR::dload || firstChild->getOpCodeValue() == TR::dloadi) &&
21762182
(firstChild->getNumChildren() > 0) &&
21772183
(firstChild->getFirstChild()->getNumChildren() == 1) &&
2178-
!(firstChild->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP()))
2184+
!(firstChild->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP()))
21792185
{
21802186
// Coming from memory, last use
21812187
TR::Register *tempReg = cg->allocateRegister(TR_FPR);
@@ -3140,12 +3146,12 @@ TR::Register *OMR::ARM::TreeEvaluator::fRegStoreEvaluator(TR::Node *node, TR::Co
31403146

31413147
TR::Register *OMR::ARM::TreeEvaluator::fmaxEvaluator(TR::Node *node, TR::CodeGenerator *cg)
31423148
{
3143-
return NULL;
3149+
return NULL;
31443150
}
31453151

31463152
TR::Register *OMR::ARM::TreeEvaluator::fminEvaluator(TR::Node *node, TR::CodeGenerator *cg)
31473153
{
3148-
return NULL;
3154+
return NULL;
31493155
}
31503156

31513157
#endif

‎compiler/arm/codegen/OMRTreeEvaluator.cpp

+10-10
Original file line numberDiff line numberDiff line change
@@ -3221,7 +3221,7 @@ TR::Instruction *loadAddressConstant(TR::CodeGenerator *cg, TR::Node * node, int
32213221
TR::Register *OMR::ARM::TreeEvaluator::iloadEvaluator(TR::Node *node, TR::CodeGenerator *cg)
32223222
{
32233223
TR::Register *tempReg;
3224-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3224+
bool needSync = node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP();
32253225

32263226
tempReg = cg->allocateRegister();
32273227
if (node->getSymbolReference()->getSymbol()->isInternalPointer())
@@ -3326,7 +3326,7 @@ TR::Register *OMR::ARM::TreeEvaluator::aloadEvaluator(TR::Node *node, TR::CodeGe
33263326
}
33273327

33283328
TR::Register *tempReg;
3329-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3329+
bool needSync = node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP();
33303330

33313331
if (!node->getSymbolReference()->getSymbol()->isInternalPointer())
33323332
{
@@ -3370,7 +3370,7 @@ TR::Register *OMR::ARM::TreeEvaluator::lloadEvaluator(TR::Node *node, TR::CodeGe
33703370
TR::RegisterPair *trgReg = cg->allocateRegisterPair(lowReg, highReg);
33713371
TR::Compilation *comp = cg->comp();
33723372
bool bigEndian = cg->comp()->target().cpu.isBigEndian();
3373-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3373+
bool needSync = (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP());
33743374

33753375
if (needSync && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
33763376
{
@@ -3422,7 +3422,7 @@ TR::Register *OMR::ARM::TreeEvaluator::commonLoadEvaluator(TR::Node *node, TR::
34223422
{
34233423
TR::Register *tempReg = node->setRegister(cg->allocateRegister());
34243424
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, memSize, cg);
3425-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3425+
bool needSync = (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP());
34263426
generateTrg1MemInstruction(cg, memToRegOp, node, tempReg, tempMR);
34273427
if (needSync && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
34283428
{
@@ -3440,7 +3440,7 @@ TR::Register *OMR::ARM::TreeEvaluator::awrtbarEvaluator(TR::Node *node, TR::Code
34403440
TR::Node *firstChild = node->getFirstChild();
34413441
TR::Register *sourceRegister;
34423442
bool killSource = false;
3443-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3443+
bool needSync = (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP());
34443444

34453445
if (firstChild->getReferenceCount() > 1 && firstChild->getRegister() != NULL)
34463446
{
@@ -3490,7 +3490,7 @@ TR::Register *OMR::ARM::TreeEvaluator::awrtbariEvaluator(TR::Node *node, TR::Cod
34903490
TR::Node *secondChild = node->getSecondChild();
34913491
TR::Register *sourceRegister;
34923492
bool killSource = false;
3493-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3493+
bool needSync = (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP());
34943494

34953495
/* comp->useCompressedPointers() is false for 32bit environment, leaving the compressed pointer support unimplemented. */
34963496
if (secondChild->getReferenceCount() > 1 && secondChild->getRegister() != NULL)
@@ -3547,7 +3547,7 @@ TR::Register *OMR::ARM::TreeEvaluator::lstoreEvaluator(TR::Node *node, TR::CodeG
35473547
valueChild = node->getFirstChild();
35483548
}
35493549
bool bigEndian = cg->comp()->target().cpu.isBigEndian();
3550-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3550+
bool needSync = (node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease() && cg->comp()->target().isSMP());
35513551
TR::Register *valueReg = cg->evaluate(valueChild);
35523552

35533553
if (needSync && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
@@ -3612,7 +3612,7 @@ TR::Register *OMR::ARM::TreeEvaluator::istoreEvaluator(TR::Node *node, TR::CodeG
36123612
TR::Register *OMR::ARM::TreeEvaluator::commonStoreEvaluator(TR::Node *node, TR::InstOpCode::Mnemonic memToRegOp, int32_t memSize, TR::CodeGenerator *cg)
36133613
{
36143614
TR::MemoryReference *tempMR = new (cg->trHeapMemory()) TR::MemoryReference(node, memSize, cg);
3615-
bool needSync = (node->getSymbolReference()->getSymbol()->isSyncVolatile() && cg->comp()->target().isSMP());
3615+
const bool supportsDMB = (cg->comp()->target().isSMP() && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor);
36163616
TR::Node *valueChild;
36173617
if (node->getOpCode().isIndirect())
36183618
{
@@ -3623,12 +3623,12 @@ TR::Register *OMR::ARM::TreeEvaluator::commonStoreEvaluator(TR::Node *node, TR::
36233623
valueChild = node->getFirstChild();
36243624
}
36253625

3626-
if (needSync && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
3626+
if (supportsDMB && node->getSymbolReference()->getSymbol()->isAtLeastOrStrongerThanAcquireRelease())
36273627
{
36283628
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb_st, node);
36293629
}
36303630
generateMemSrc1Instruction(cg, memToRegOp, node, tempMR, cg->evaluate(valueChild));
3631-
if (needSync && cg->comp()->target().cpu.id() != TR_DefaultARMProcessor)
3631+
if (supportsDMB && node->getSymbolReference()->getSymbol()->isVolatile())
36323632
{
36333633
generateInstruction(cg, (cg->comp()->target().cpu.id() == TR_ARMv6) ? TR::InstOpCode::dmb_v6 : TR::InstOpCode::dmb, node);
36343634
}

‎compiler/compile/OMRSymbolReferenceTable.cpp

+2-2
Original file line numberDiff line numberDiff line change
@@ -102,8 +102,6 @@ OMR::SymbolReferenceTable::SymbolReferenceTable(size_t sizeHint, TR::Compilation
102102
_numInternalPointers(0),
103103
_ObjectNewInstanceImplSymRef(0),
104104
_knownObjectSymrefsByObjectIndex(comp->trMemory()),
105-
_unsafeSymRefs(0),
106-
_unsafeVolatileSymRefs(0),
107105
_availableAutos(comp->trMemory()),
108106
_vtableEntrySymbolRefs(comp->trMemory()),
109107
_classLoaderSymbolRefs(comp->trMemory()),
@@ -125,6 +123,8 @@ OMR::SymbolReferenceTable::SymbolReferenceTable(size_t sizeHint, TR::Compilation
125123
baseArray.element(i) = 0;
126124
_size_hint = sizeHint;
127125

126+
for (int i = 0; i < TR::Symbol::numberOfMemoryOrderings; i++)
127+
_unsafeSymRefs[i] = NULL;
128128
}
129129

130130

‎compiler/compile/OMRSymbolReferenceTable.hpp

+1-2
Original file line numberDiff line numberDiff line change
@@ -948,8 +948,7 @@ class SymbolReferenceTable
948948

949949
TR_Array<TR_BitVector *> _knownObjectSymrefsByObjectIndex;
950950

951-
TR_Array<TR::SymbolReference *> * _unsafeSymRefs;
952-
TR_Array<TR::SymbolReference *> * _unsafeVolatileSymRefs;
951+
TR_Array<TR::SymbolReference *> * _unsafeSymRefs[TR::Symbol::numberOfMemoryOrderings];
953952

954953
List<TR::SymbolReference> _availableAutos;
955954
List<TR::SymbolReference> _vtableEntrySymbolRefs;

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