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Automatic merge of 'master' into merge (2024-04-05 00:04)
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‎.mailmap

+4-2
Original file line numberDiff line numberDiff line change
@@ -340,7 +340,8 @@ Lee Jones <[email protected]> <[email protected]>
340340
Lee Jones <[email protected]> <[email protected]>
341341
Lee Jones <[email protected]> <[email protected]>
342342
Lee Jones <[email protected]> <[email protected]>
343-
Leonard Crestez <[email protected]> Leonard Crestez <[email protected]>
343+
Leonard Crestez <[email protected]> <[email protected]>
344+
Leonard Crestez <[email protected]> <[email protected]>
344345
Leonardo Bras <[email protected]> <[email protected]>
345346
Leonard Göhrs <[email protected]>
346347
Leonid I Ananiev <[email protected]>
@@ -497,7 +498,8 @@ Prasad Sodagudi <[email protected]> <[email protected]>
497498
Punit Agrawal <[email protected]> <[email protected]>
498499
Qais Yousef <[email protected]> <[email protected]>
499500
Qais Yousef <[email protected]> <[email protected]>
500-
Quentin Monnet <[email protected]> <[email protected]>
501+
Quentin Monnet <[email protected]> <[email protected]>
502+
Quentin Monnet <[email protected]> <[email protected]>
501503
Quentin Perret <[email protected]> <[email protected]>
502504
Rafael J. Wysocki <[email protected]> <[email protected]>
503505
Rajeev Nandan <[email protected]> <[email protected]>

‎Documentation/arch/riscv/vm-layout.rst

+5-11
Original file line numberDiff line numberDiff line change
@@ -144,14 +144,8 @@ passing 0 into the hint address parameter of mmap. On CPUs with an address space
144144
smaller than sv48, the CPU maximum supported address space will be the default.
145145

146146
Software can "opt-in" to receiving VAs from another VA space by providing
147-
a hint address to mmap. A hint address passed to mmap will cause the largest
148-
address space that fits entirely into the hint to be used, unless there is no
149-
space left in the address space. If there is no space available in the requested
150-
address space, an address in the next smallest available address space will be
151-
returned.
152-
153-
For example, in order to obtain 48-bit VA space, a hint address greater than
154-
:code:`1 << 47` must be provided. Note that this is 47 due to sv48 userspace
155-
ending at :code:`1 << 47` and the addresses beyond this are reserved for the
156-
kernel. Similarly, to obtain 57-bit VA space addresses, a hint address greater
157-
than or equal to :code:`1 << 56` must be provided.
147+
a hint address to mmap. When a hint address is passed to mmap, the returned
148+
address will never use more bits than the hint address. For example, if a hint
149+
address of `1 << 40` is passed to mmap, a valid returned address will never use
150+
bits 41 through 63. If no mappable addresses are available in that range, mmap
151+
will return `MAP_FAILED`.

‎Documentation/arch/x86/resctrl.rst

+5-5
Original file line numberDiff line numberDiff line change
@@ -45,7 +45,7 @@ mount options are:
4545
Enable code/data prioritization in L2 cache allocations.
4646
"mba_MBps":
4747
Enable the MBA Software Controller(mba_sc) to specify MBA
48-
bandwidth in MBps
48+
bandwidth in MiBps
4949
"debug":
5050
Make debug files accessible. Available debug files are annotated with
5151
"Available only with debug option".
@@ -526,7 +526,7 @@ threads start using more cores in an rdtgroup, the actual bandwidth may
526526
increase or vary although user specified bandwidth percentage is same.
527527

528528
In order to mitigate this and make the interface more user friendly,
529-
resctrl added support for specifying the bandwidth in MBps as well. The
529+
resctrl added support for specifying the bandwidth in MiBps as well. The
530530
kernel underneath would use a software feedback mechanism or a "Software
531531
Controller(mba_sc)" which reads the actual bandwidth using MBM counters
532532
and adjust the memory bandwidth percentages to ensure::
@@ -573,13 +573,13 @@ Memory b/w domain is L3 cache.
573573

574574
MB:<cache_id0>=bandwidth0;<cache_id1>=bandwidth1;...
575575

576-
Memory bandwidth Allocation specified in MBps
577-
---------------------------------------------
576+
Memory bandwidth Allocation specified in MiBps
577+
----------------------------------------------
578578

579579
Memory bandwidth domain is L3 cache.
580580
::
581581

582-
MB:<cache_id0>=bw_MBps0;<cache_id1>=bw_MBps1;...
582+
MB:<cache_id0>=bw_MiBps0;<cache_id1>=bw_MiBps1;...
583583

584584
Slow Memory Bandwidth Allocation (SMBA)
585585
---------------------------------------

‎Documentation/devicetree/bindings/i2c/qcom,i2c-cci.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -270,7 +270,7 @@ examples:
270270
271271
port {
272272
ov7251_ep: endpoint {
273-
data-lanes = <0 1>;
273+
data-lanes = <0>;
274274
link-frequencies = /bits/ 64 <240000000 319200000>;
275275
remote-endpoint = <&csiphy3_ep>;
276276
};

‎Documentation/devicetree/bindings/i2c/st,nomadik-i2c.yaml

+43-6
Original file line numberDiff line numberDiff line change
@@ -14,31 +14,30 @@ description: The Nomadik I2C host controller began its life in the ST
1414
maintainers:
1515
- Linus Walleij <[email protected]>
1616

17-
allOf:
18-
- $ref: /schemas/i2c/i2c-controller.yaml#
19-
2017
# Need a custom select here or 'arm,primecell' will match on lots of nodes
2118
select:
2219
properties:
2320
compatible:
2421
contains:
2522
enum:
2623
- st,nomadik-i2c
24+
- mobileye,eyeq5-i2c
2725
required:
2826
- compatible
2927

3028
properties:
3129
compatible:
3230
oneOf:
33-
# The variant found in STn8815
3431
- items:
3532
- const: st,nomadik-i2c
3633
- const: arm,primecell
37-
# The variant found in DB8500
3834
- items:
3935
- const: stericsson,db8500-i2c
4036
- const: st,nomadik-i2c
4137
- const: arm,primecell
38+
- items:
39+
- const: mobileye,eyeq5-i2c
40+
- const: arm,primecell
4241

4342
reg:
4443
maxItems: 1
@@ -55,7 +54,7 @@ properties:
5554
- items:
5655
- const: mclk
5756
- const: apb_pclk
58-
# Clock name in DB8500
57+
# Clock name in DB8500 or EyeQ5
5958
- items:
6059
- const: i2cclk
6160
- const: apb_pclk
@@ -70,6 +69,16 @@ properties:
7069
minimum: 1
7170
maximum: 400000
7271

72+
mobileye,olb:
73+
$ref: /schemas/types.yaml#/definitions/phandle-array
74+
items:
75+
- items:
76+
- description: Phandle to OLB system controller node.
77+
- description: Platform-wide controller ID (integer starting from zero).
78+
description:
79+
The phandle pointing to OLB system controller node, with the I2C
80+
controller index.
81+
7382
required:
7483
- compatible
7584
- reg
@@ -79,6 +88,20 @@ required:
7988

8089
unevaluatedProperties: false
8190

91+
allOf:
92+
- $ref: /schemas/i2c/i2c-controller.yaml#
93+
- if:
94+
properties:
95+
compatible:
96+
contains:
97+
const: mobileye,eyeq5-i2c
98+
then:
99+
required:
100+
- mobileye,olb
101+
else:
102+
properties:
103+
mobileye,olb: false
104+
82105
examples:
83106
- |
84107
#include <dt-bindings/interrupt-controller/irq.h>
@@ -111,5 +134,19 @@ examples:
111134
clocks = <&i2c0clk>, <&pclki2c0>;
112135
clock-names = "mclk", "apb_pclk";
113136
};
137+
- |
138+
#include <dt-bindings/interrupt-controller/mips-gic.h>
139+
i2c@300000 {
140+
compatible = "mobileye,eyeq5-i2c", "arm,primecell";
141+
reg = <0x300000 0x1000>;
142+
interrupt-parent = <&gic>;
143+
interrupts = <GIC_SHARED 1 IRQ_TYPE_LEVEL_HIGH>;
144+
clock-frequency = <400000>;
145+
#address-cells = <1>;
146+
#size-cells = <0>;
147+
clocks = <&i2c_ser_clk>, <&i2c_clk>;
148+
clock-names = "i2cclk", "apb_pclk";
149+
mobileye,olb = <&olb 0>;
150+
};
114151
115152
...

‎Documentation/devicetree/bindings/riscv/cpus.yaml

+5-1
Original file line numberDiff line numberDiff line change
@@ -110,7 +110,11 @@ properties:
110110
const: 1
111111

112112
compatible:
113-
const: riscv,cpu-intc
113+
oneOf:
114+
- items:
115+
- const: andestech,cpu-intc
116+
- const: riscv,cpu-intc
117+
- const: riscv,cpu-intc
114118

115119
interrupt-controller: true
116120

‎Documentation/devicetree/bindings/riscv/extensions.yaml

+7
Original file line numberDiff line numberDiff line change
@@ -477,5 +477,12 @@ properties:
477477
latency, as ratified in commit 56ed795 ("Update
478478
riscv-crypto-spec-vector.adoc") of riscv-crypto.
479479

480+
- const: xandespmu
481+
description:
482+
The Andes Technology performance monitor extension for counter overflow
483+
and privilege mode filtering. For more details, see Counter Related
484+
Registers in the AX45MP datasheet.
485+
https://www.andestech.com/wp-content/uploads/AX45MP-1C-Rev.-5.0.0-Datasheet.pdf
486+
480487
additionalProperties: true
481488
...

‎Documentation/devicetree/bindings/sound/cirrus,cs42l43.yaml

+6-5
Original file line numberDiff line numberDiff line change
@@ -185,11 +185,12 @@ properties:
185185

186186
gpio-ranges:
187187
items:
188-
- description: A phandle to the CODEC pinctrl node
189-
minimum: 0
190-
- const: 0
191-
- const: 0
192-
- const: 3
188+
- items:
189+
- description: A phandle to the CODEC pinctrl node
190+
minimum: 0
191+
- const: 0
192+
- const: 0
193+
- const: 3
193194

194195
patternProperties:
195196
"-state$":

‎Documentation/devicetree/bindings/timer/cdns,ttc.yaml

+21-1
Original file line numberDiff line numberDiff line change
@@ -32,12 +32,23 @@ properties:
3232
description: |
3333
Bit width of the timer, necessary if not 16.
3434
35+
"#pwm-cells":
36+
const: 3
37+
3538
required:
3639
- compatible
3740
- reg
38-
- interrupts
3941
- clocks
4042

43+
allOf:
44+
- if:
45+
not:
46+
required:
47+
- "#pwm-cells"
48+
then:
49+
required:
50+
- interrupts
51+
4152
additionalProperties: false
4253

4354
examples:
@@ -50,3 +61,12 @@ examples:
5061
clocks = <&cpu_clk 3>;
5162
timer-width = <32>;
5263
};
64+
65+
- |
66+
pwm: pwm@f8002000 {
67+
compatible = "cdns,ttc";
68+
reg = <0xf8002000 0x1000>;
69+
clocks = <&cpu_clk 3>;
70+
timer-width = <32>;
71+
#pwm-cells = <3>;
72+
};

‎Documentation/devicetree/bindings/timer/nxp,sysctr-timer.yaml

+3-1
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,9 @@ description: |
1818
1919
properties:
2020
compatible:
21-
const: nxp,sysctr-timer
21+
enum:
22+
- nxp,imx95-sysctr-timer
23+
- nxp,sysctr-timer
2224

2325
reg:
2426
maxItems: 1

‎Documentation/devicetree/bindings/timer/ralink,cevt-systick.yaml

+38
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,38 @@
1+
# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
2+
%YAML 1.2
3+
---
4+
$id: http://devicetree.org/schemas/timer/ralink,cevt-systick.yaml#
5+
$schema: http://devicetree.org/meta-schemas/core.yaml#
6+
7+
title: System tick counter present in Ralink family SoCs
8+
9+
maintainers:
10+
- Sergio Paracuellos <[email protected]>
11+
12+
properties:
13+
compatible:
14+
const: ralink,cevt-systick
15+
16+
reg:
17+
maxItems: 1
18+
19+
interrupts:
20+
maxItems: 1
21+
22+
required:
23+
- compatible
24+
- reg
25+
- interrupts
26+
27+
additionalProperties: false
28+
29+
examples:
30+
- |
31+
systick@d00 {
32+
compatible = "ralink,cevt-systick";
33+
reg = <0xd00 0x10>;
34+
35+
interrupt-parent = <&cpuintc>;
36+
interrupts = <7>;
37+
};
38+
...

‎Documentation/devicetree/bindings/timer/renesas,ostm.yaml

+1-1
Original file line numberDiff line numberDiff line change
@@ -23,7 +23,7 @@ properties:
2323
- enum:
2424
- renesas,r7s72100-ostm # RZ/A1H
2525
- renesas,r7s9210-ostm # RZ/A2M
26-
- renesas,r9a07g043-ostm # RZ/G2UL
26+
- renesas,r9a07g043-ostm # RZ/G2UL and RZ/Five
2727
- renesas,r9a07g044-ostm # RZ/G2{L,LC}
2828
- renesas,r9a07g054-ostm # RZ/V2L
2929
- const: renesas,ostm # Generic

‎Documentation/devicetree/bindings/timer/renesas,tmu.yaml

+16-2
Original file line numberDiff line numberDiff line change
@@ -46,7 +46,19 @@ properties:
4646

4747
interrupts:
4848
minItems: 2
49-
maxItems: 3
49+
items:
50+
- description: Underflow interrupt, channel 0
51+
- description: Underflow interrupt, channel 1
52+
- description: Underflow interrupt, channel 2
53+
- description: Input capture interrupt, channel 2
54+
55+
interrupt-names:
56+
minItems: 2
57+
items:
58+
- const: tuni0
59+
- const: tuni1
60+
- const: tuni2
61+
- const: ticpi2
5062

5163
clocks:
5264
maxItems: 1
@@ -100,7 +112,9 @@ examples:
100112
reg = <0xffd80000 0x30>;
101113
interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>,
102114
<GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>,
103-
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
115+
<GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>,
116+
<GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
117+
interrupt-names = "tuni0", "tuni1", "tuni2", "ticpi2";
104118
clocks = <&mstp0_clks R8A7779_CLK_TMU0>;
105119
clock-names = "fck";
106120
power-domains = <&sysc R8A7779_PD_ALWAYS_ON>;

‎Documentation/devicetree/bindings/timer/samsung,exynos4210-mct.yaml

+2
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ properties:
2626
- items:
2727
- enum:
2828
- axis,artpec8-mct
29+
- google,gs101-mct
2930
- samsung,exynos3250-mct
3031
- samsung,exynos5250-mct
3132
- samsung,exynos5260-mct
@@ -127,6 +128,7 @@ allOf:
127128
contains:
128129
enum:
129130
- axis,artpec8-mct
131+
- google,gs101-mct
130132
- samsung,exynos5260-mct
131133
- samsung,exynos5420-mct
132134
- samsung,exynos5433-mct

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