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LiteX: driver for MMCM
Original authors: Pawel Czarnecki <[email protected]>, Mateusz Holenko <[email protected]> DT bindings and documentation: Geert Uytterhoeven <[email protected]> Signed-off-by: Pawel Czarnecki <[email protected]> Signed-off-by: Mateusz Holenko <[email protected]> Signed-off-by: Geert Uytterhoeven <[email protected]> FIXME1: not updated or tested for 32-bit CSR data width, 64-bit CPU (gls) FIXME2: if possible, replace calls to '_litex_[get|set]_reg()' with the appropriate 'litex_[read|write][8|16|32|64]()'. If the size of a LiteX CSR access can't be determined at compile time, we should make available a set of public 'litex_[get|set]_reg()' methods that add 'BUG_ON(reg_size > sizeof(u64) || reg_size < 1)' on top of the call to '_litex_[get|set]_reg()'.
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‎Documentation/devicetree/bindings/clock/litex,clock.yaml

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# SPDX-License-Identifier: GPL-2.0
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/clock/litex,clock.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: LiteX clock control driver
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description: |
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Common clock driver with MMCM unit for dynamic reconfiguration
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of up to 7 clock outputs with ability to change frequency, duty
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cycle and phase offset
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maintainers:
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- Karol Gugala <[email protected]>
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- Mateusz Holenko <[email protected]>
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properties:
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compatible:
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const: litex,clock
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reg:
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description: Base address and lengths of the register space
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"#clock-cells":
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description:
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Number of cells in a clock specifier;
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Typically 0 for nodes with a single clock output
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and 1 for nodes with multiple clock outputs.
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const: 1
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"#address-cells":
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description:
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Number of cells that are needed to form the base address
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part in the reg property.
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const: 1
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"#size-cells":
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description:
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Used to state how many cells are in each field of a reg property
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const: 0
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clock-output-names:
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description:
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List of strings of clock output signal names indexed
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by the first cell in the clock specifier.
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minItems: 1
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maxItems: 7
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items:
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- const: CLKOUT0
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- const: CLKOUT1
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- const: CLKOUT2
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- const: CLKOUT3
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- const: CLKOUT4
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- const: CLKOUT5
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- const: CLKOUT6
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litex,nclkout:
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description: Number of desired clock outputs
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 7
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litex,lock-timeout:
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description: Number of ms to wait for MMCM to assert LOCK signal
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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litex,drdy-timeout:
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description: Number of ms to wait for MMCM to assert DRDY signal
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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litex,sys-clock-freq:
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description: System clock frequency
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$ref: /schemas/types.yaml#/definitions/uint32
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patternProperties:
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"^CLKOUT[0-6]$":
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description:
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Child node representing configurable clock outputs of MMCM unit
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type: object
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properties:
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compatible:
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const: litex,clock
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reg:
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description: clock output ID, zero-based numbering
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litex,clock-frequency:
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description: default frequency in Hz for clock output
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1587000
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maximum: 100000000
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litex,clock-phase:
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description: default phase offset given in degrees
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 0
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maximum: 359
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litex,clock-duty-num:
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description: default duty cycle numerator value
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 100
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litex,clock-duty-den:
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description: default duty cycle denominator value
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$ref: /schemas/types.yaml#/definitions/uint32
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minimum: 1
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maximum: 100
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required:
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- compatible
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- "#clock-cells"
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- clock-output-names
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- reg
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- litex,clock-frequency
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- litex,clock-phase
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- litex,clock-duty-num
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- litex,clock-duty-den
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required:
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- compatible
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- reg
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- "#clock-cells"
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- "#address-cells"
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- "#size-cells"
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- clock-output-names
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- litex,nclkout
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- CLKOUTx
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additionalProperties: false
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examples:
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- |
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clk0: clock-controller@f0003000 {
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compatible = "litex,clk";
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reg = <0x0 0xf0003000>, <0x0 0x100>;
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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clock-output-names = "CLKOUT0",
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"CLKOUT1",
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"CLKOUT2",
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"CLKOUT3",
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"CLKOUT4",
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"CLKOUT5",
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"CLKOUT6";
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litex,nclkout = <7>;
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CLKOUT0: CLKOUT0@0 {
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT0";
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reg = <0>;
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litex,clock-frequency = <50000000>;
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litex,clock-phase = <0>;
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litex,clock-duty = <50>;
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};
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CLKOUT1: CLKOUT1@1 {
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT1";
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reg = <1>;
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litex,clock-frequency = <50000000>;
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litex,clock-phase = <90>;
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litex,clock-duty = <50>;
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};
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CLKOUT2: CLKOUT2@2 {
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT2";
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reg = <2>;
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litex,clock-frequency = <25000000>;
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litex,clock-phase = <0>;
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litex,clock-duty = <25>;
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};
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CLKOUT3: CLKOUT3@3 {
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT3";
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reg = <3>;
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litex,clock-frequency = <12500000>;
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litex,clock-phase = <0>;
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litex,clock-duty = <75>;
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};
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CLKOUT4: CLKOUT4@4 {
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT4";
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reg = <4>;
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litex,clock-frequency = <6250000>;
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litex,clock-phase = <0>;
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litex,clock-duty = <50>;
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};
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CLKOUT5: CLKOUT5@5 {
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT5";
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reg = <5>;
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litex,clock-frequency = <3125000>;
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litex,clock-phase = <0>;
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litex,clock-duty = <50>;
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};
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CLKOUT6: CLKOUT6@6 {
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compatible = "litex,clk";
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#clock-cells = <0>;
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clock-output-names = "CLKOUT6";
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reg = <6>;
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litex,clock-frequency = <1562500>;
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litex,clock-phase = <0>;
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litex,clock-duty = <5>;
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};
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};
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...

‎drivers/clk/Kconfig

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Not all features of the PLL are currently supported
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by the driver.
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config COMMON_CLK_LITEX
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tristate "LiteX Clock control support"
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depends on COMMON_CLK && OF && LITEX_SOC_CONTROLLER
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help
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Clock control support for LiteX SoC builder, utilising MMCM unit and DRP registers
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source "drivers/clk/actions/Kconfig"
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source "drivers/clk/analogbits/Kconfig"
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source "drivers/clk/baikal-t1/Kconfig"

‎drivers/clk/Makefile

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obj-$(CONFIG_COMMON_CLK_K210) += clk-k210.o
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obj-$(CONFIG_LMK04832) += clk-lmk04832.o
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obj-$(CONFIG_COMMON_CLK_LAN966X) += clk-lan966x.o
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obj-$(CONFIG_COMMON_CLK_LITEX) += clk-litex.o
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obj-$(CONFIG_COMMON_CLK_LOCHNAGAR) += clk-lochnagar.o
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obj-$(CONFIG_MACH_LOONGSON32) += clk-loongson1.o
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obj-$(CONFIG_COMMON_CLK_LOONGSON2) += clk-loongson2.o

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