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Merge commit 'c5947082c48a673b822d51b1deb2cafc2cecab31'
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‎pythondata_cpu_cva6/system_verilog/.gitmodules

-3
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,6 @@
11
[submodule "corev_apu/axi_mem_if"]
22
path = corev_apu/axi_mem_if
33
url = https://github.com/pulp-platform/axi_mem_if.git
4-
[submodule "corev_apu/fpga-support"]
5-
path = corev_apu/fpga-support
6-
url = https://github.com/pulp-platform/fpga-support.git
74
[submodule "common/submodules/common_cells"]
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path = common/submodules/common_cells
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url = https://github.com/pulp-platform/common_cells.git

‎pythondata_cpu_cva6/system_verilog/Bender.yml

+1-1
Original file line numberDiff line numberDiff line change
@@ -163,7 +163,7 @@ sources:
163163
- corev_apu/axi/src/axi_mux.sv
164164
- corev_apu/axi/src/axi_demux.sv
165165
- corev_apu/axi/src/axi_xbar.sv
166-
- corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
166+
- common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv
167167
- common/submodules/common_cells/src/sync.sv
168168
- common/submodules/common_cells/src/popcount.sv
169169
- common/submodules/common_cells/src/unread.sv

‎pythondata_cpu_cva6/system_verilog/Makefile

+2-1
Original file line numberDiff line numberDiff line change
@@ -203,6 +203,7 @@ src := $(filter-out core/ariane_regfile.sv, $(wildcard core/*.sv))
203203
corev_apu/axi/src/axi_mux.sv \
204204
corev_apu/axi/src/axi_demux.sv \
205205
corev_apu/axi/src/axi_xbar.sv \
206+
common/local/techlib/fpga/rtl/SyncSpRamBeNx64.sv \
206207
common/submodules/common_cells/src/unread.sv \
207208
common/submodules/common_cells/src/sync.sv \
208209
common/submodules/common_cells/src/cdc_2phase.sv \
@@ -254,7 +255,7 @@ copro_src := $(addprefix $(root-dir), $(copro_src))
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uart_src := $(wildcard corev_apu/fpga/src/apb_uart/src/*.vhd)
255256
uart_src := $(addprefix $(root-dir), $(uart_src))
256257

257-
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) corev_apu/src/tech_cells_generic/src/fpga/tc_sram_xilinx.sv common/local/util/tc_sram_xilinx_wrapper.sv
258+
fpga_src := $(wildcard corev_apu/fpga/src/*.sv) $(wildcard corev_apu/fpga/src/bootrom/*.sv) $(wildcard corev_apu/fpga/src/ariane-ethernet/*.sv) common/local/util/tc_sram_fpga_wrapper.sv
258259
fpga_src := $(addprefix $(root-dir), $(fpga_src))
259260

260261
# look for testbenches

‎pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncDpRam.sv

+182
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,182 @@
1+
// Copyright 2014 ETH Zurich and University of Bologna.
2+
// Copyright and related rights are licensed under the Solderpad Hardware
3+
// License, Version 0.51 (the "License"); you may not use this file except in
4+
// compliance with the License. You may obtain a copy of the License at
5+
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
6+
// or agreed to in writing, software, hardware and materials distributed under
7+
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
8+
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
9+
// specific language governing permissions and limitations under the License.
10+
11+
/**
12+
* Inferable, Synchronous Dual-Port RAM
13+
*
14+
* This module is designed to work with both Xilinx and Altera tools by following the respective
15+
* guidelines:
16+
* - Xilinx UG901 Vivado Design Suite User Guide: Synthesis (p. 106)
17+
* - Altera Quartus II Handbook Volume 1: Design and Synthesis (p. 768)
18+
*
19+
* Current Maintainers:
20+
* - Michael Schaffner <[email protected]>
21+
*/
22+
23+
// this automatically switches the behavioral description
24+
// pragma translate_off
25+
`define SIMULATION
26+
// pragma translate_on
27+
28+
module SyncDpRam
29+
#(
30+
parameter ADDR_WIDTH = 10,
31+
parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower
32+
parameter DATA_WIDTH = 32,
33+
parameter OUT_REGS = 0,
34+
parameter SIM_INIT = 0 // for simulation only, will not be synthesized
35+
// 0: no init, 1: zero init, 2: random init
36+
// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
37+
)(
38+
input logic Clk_CI,
39+
input logic Rst_RBI,
40+
// port A
41+
input logic CSelA_SI,
42+
input logic WrEnA_SI,
43+
input logic [DATA_WIDTH-1:0] WrDataA_DI,
44+
input logic [ADDR_WIDTH-1:0] AddrA_DI,
45+
output logic [DATA_WIDTH-1:0] RdDataA_DO,
46+
// port B
47+
input logic CSelB_SI,
48+
input logic WrEnB_SI,
49+
input logic [DATA_WIDTH-1:0] WrDataB_DI,
50+
input logic [ADDR_WIDTH-1:0] AddrB_DI,
51+
output logic [DATA_WIDTH-1:0] RdDataB_DO
52+
);
53+
54+
////////////////////////////
55+
// signals, localparams
56+
////////////////////////////
57+
58+
logic [DATA_WIDTH-1:0] RdDataA_DN;
59+
logic [DATA_WIDTH-1:0] RdDataA_DP;
60+
logic [DATA_WIDTH-1:0] RdDataB_DN;
61+
logic [DATA_WIDTH-1:0] RdDataB_DP;
62+
logic [DATA_WIDTH-1:0] Mem_DP [DATA_DEPTH-1:0];
63+
64+
////////////////////////////
65+
// XILINX/ALTERA implementation
66+
////////////////////////////
67+
68+
`ifdef SIMULATION
69+
always_ff @(posedge Clk_CI)
70+
begin
71+
automatic logic [DATA_WIDTH-1:0] val;
72+
if(Rst_RBI == 1'b0 && SIM_INIT>0) begin
73+
for(int k=0; k<DATA_DEPTH;k++) begin
74+
if(SIM_INIT==1) val = '0;
75+
`ifndef VERILATOR
76+
else if(SIM_INIT==2) void'(randomize(val));
77+
`endif
78+
Mem_DP[k] = val;
79+
end
80+
end else begin
81+
if (CSelA_SI) begin
82+
if (WrEnA_SI) begin
83+
Mem_DP[AddrA_DI] <= WrDataA_DI;
84+
end
85+
else
86+
begin
87+
RdDataA_DN <= Mem_DP[AddrA_DI];
88+
end
89+
end
90+
91+
if (CSelB_SI) begin
92+
if (WrEnB_SI) begin
93+
Mem_DP[AddrB_DI] <= WrDataB_DI;
94+
end
95+
else
96+
begin
97+
RdDataB_DN <= Mem_DP[AddrB_DI];
98+
end
99+
end
100+
end
101+
end
102+
`endif
103+
104+
////////////////////////////
105+
// XILINX/ALTERA implementation
106+
////////////////////////////
107+
108+
`ifndef SIMULATION
109+
always_ff @(posedge Clk_CI)
110+
begin
111+
if (CSelA_SI) begin
112+
if (WrEnA_SI) begin
113+
Mem_DP[AddrA_DI] <= WrDataA_DI;
114+
end
115+
else
116+
begin
117+
RdDataA_DN <= Mem_DP[AddrA_DI];
118+
end
119+
end
120+
end
121+
122+
always_ff @(posedge Clk_CI)
123+
begin
124+
if (CSelB_SI) begin
125+
if (WrEnB_SI) begin
126+
Mem_DP[AddrB_DI] <= WrDataB_DI;
127+
end
128+
else
129+
begin
130+
RdDataB_DN <= Mem_DP[AddrB_DI];
131+
end
132+
end
133+
end
134+
`endif
135+
136+
////////////////////////////
137+
// optional output regs
138+
////////////////////////////
139+
140+
// output regs
141+
generate
142+
if (OUT_REGS>0) begin : g_outreg
143+
always_ff @(posedge Clk_CI or negedge Rst_RBI) begin
144+
if(Rst_RBI == 1'b0)
145+
begin
146+
RdDataA_DP <= 0;
147+
RdDataB_DP <= 0;
148+
end
149+
else
150+
begin
151+
RdDataA_DP <= RdDataA_DN;
152+
RdDataB_DP <= RdDataB_DN;
153+
end
154+
end
155+
end
156+
endgenerate // g_outreg
157+
158+
// output reg bypass
159+
generate
160+
if (OUT_REGS==0) begin : g_oureg_byp
161+
assign RdDataA_DP = RdDataA_DN;
162+
assign RdDataB_DP = RdDataB_DN;
163+
end
164+
endgenerate// g_oureg_byp
165+
166+
assign RdDataA_DO = RdDataA_DP;
167+
assign RdDataB_DO = RdDataB_DP;
168+
169+
////////////////////////////
170+
// assertions
171+
////////////////////////////
172+
173+
// pragma translate_off
174+
assert property
175+
(@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
176+
else $error("depth out of bounds");
177+
assert property
178+
(@(posedge Clk_CI) (CSelA_SI & CSelB_SI & WrEnA_SI & WrEnB_SI) |-> (AddrA_DI != AddrB_DI))
179+
else $error("A and B write to the same address");
180+
// pragma translate_on
181+
182+
endmodule // SyncDpRam

‎pythondata_cpu_cva6/system_verilog/common/local/techlib/fpga/rtl/SyncSpRam.sv

+118
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,118 @@
1+
// Copyright 2014 ETH Zurich and University of Bologna.
2+
// Copyright and related rights are licensed under the Solderpad Hardware
3+
// License, Version 0.51 (the "License"); you may not use this file except in
4+
// compliance with the License. You may obtain a copy of the License at
5+
// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
6+
// or agreed to in writing, software, hardware and materials distributed under
7+
// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
8+
// CONDITIONS OF ANY KIND, either express or implied. See the License for the
9+
// specific language governing permissions and limitations under the License.
10+
11+
/**
12+
* Inferable, Synchronous Single-Port RAM
13+
*
14+
* This module is designed to work with both Xilinx and Altera tools by following the respective
15+
* guidelines:
16+
* - Xilinx UG901 Vivado Design Suite User Guide: Synthesis (p. 106)
17+
* - Altera Quartus II Handbook Volume 1: Design and Synthesis (p. 768)
18+
*
19+
* Current Maintainers:
20+
* - Michael Schaffner <[email protected]>
21+
*/
22+
23+
module SyncSpRam
24+
#(
25+
parameter ADDR_WIDTH = 10,
26+
parameter DATA_DEPTH = 1024, // usually 2**ADDR_WIDTH, but can be lower
27+
parameter DATA_WIDTH = 32,
28+
parameter OUT_REGS = 0,
29+
parameter SIM_INIT = 0 // for simulation only, will not be synthesized
30+
// 0: no init, 1: zero init, 2: random init
31+
// note: on verilator, 2 is not supported. define the VERILATOR macro to work around.
32+
)(
33+
input logic Clk_CI,
34+
input logic Rst_RBI,
35+
input logic CSel_SI,
36+
input logic WrEn_SI,
37+
input logic [ADDR_WIDTH-1:0] Addr_DI,
38+
input logic [DATA_WIDTH-1:0] WrData_DI,
39+
output logic [DATA_WIDTH-1:0] RdData_DO
40+
);
41+
42+
////////////////////////////
43+
// signals, localparams
44+
////////////////////////////
45+
46+
logic [DATA_WIDTH-1:0] RdData_DN;
47+
logic [DATA_WIDTH-1:0] RdData_DP;
48+
logic [DATA_WIDTH-1:0] Mem_DP [DATA_DEPTH-1:0];
49+
50+
////////////////////////////
51+
// XILINX/ALTERA implementation
52+
////////////////////////////
53+
54+
always_ff @(posedge Clk_CI)
55+
begin
56+
//pragma translate_off
57+
automatic logic [DATA_WIDTH-1:0] val;
58+
if(Rst_RBI == 1'b0 && SIM_INIT>0) begin
59+
for(int k=0; k<DATA_DEPTH;k++) begin
60+
if(SIM_INIT==1) val = '0;
61+
`ifndef VERILATOR
62+
else if(SIM_INIT==2) void'(randomize(val));
63+
`endif
64+
Mem_DP[k] = val;
65+
end
66+
end else
67+
//pragma translate_on
68+
if (CSel_SI) begin
69+
if (WrEn_SI) begin
70+
Mem_DP[Addr_DI] <= WrData_DI;
71+
end
72+
else
73+
begin
74+
RdData_DN <= Mem_DP[Addr_DI];
75+
end
76+
end
77+
end
78+
79+
////////////////////////////
80+
// optional output regs
81+
////////////////////////////
82+
83+
// output regs
84+
generate
85+
if (OUT_REGS>0) begin : g_outreg
86+
always_ff @(posedge Clk_CI or negedge Rst_RBI) begin
87+
if(Rst_RBI == 1'b0)
88+
begin
89+
RdData_DP <= 0;
90+
end
91+
else
92+
begin
93+
RdData_DP <= RdData_DN;
94+
end
95+
end
96+
end
97+
endgenerate // g_outreg
98+
99+
// output reg bypass
100+
generate
101+
if (OUT_REGS==0) begin : g_oureg_byp
102+
assign RdData_DP = RdData_DN;
103+
end
104+
endgenerate// g_oureg_byp
105+
106+
assign RdData_DO = RdData_DP;
107+
108+
////////////////////////////
109+
// assertions
110+
////////////////////////////
111+
112+
// pragma translate_off
113+
assert property
114+
(@(posedge Clk_CI) (longint'(2)**longint'(ADDR_WIDTH) >= longint'(DATA_DEPTH)))
115+
else $error("depth out of bounds");
116+
// pragma translate_on
117+
118+
endmodule // SyncSpRam

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