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Merge commit '187944c417f04c144b9730445052aec0fc93620a'
2 parents 373b664 + 187944c commit 19293a8

25 files changed

+706
-300
lines changed

‎pythondata_cpu_ibex/system_verilog/doc/02_user/integration.rst

+6
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,7 @@ Instantiation Template
2626
.RegFile ( ibex_pkg::RegFileFF ),
2727
.ICache ( 0 ),
2828
.ICacheECC ( 0 ),
29+
.ICacheScramble ( 0 ),
2930
.BranchPrediction ( 0 ),
3031
.SecureIbex ( 0 ),
3132
.RndCnstLfsrSeed ( ibex_pkg::RndCnstLfsrSeedDefault ),
@@ -131,6 +132,9 @@ Parameters
131132
| ``ICacheECC`` | bit | 0 | *EXPERIMENTAL* Enable SECDED ECC protection in ICache (if |
132133
| | | | ICache == 1) |
133134
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
135+
| ``ICacheScramble`` | bit | 0 | *EXPERIMENTAL* Enabling this parameter replaces tag and data RAMs of |
136+
| | | | ICache with scrambling RAM primitives. |
137+
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
134138
| ``BranchPrediction`` | bit | 0 | *EXPERIMENTAL* Enable Static branch prediction |
135139
+------------------------------+---------------------+------------+-----------------------------------------------------------------------+
136140
| ``SecureIbex`` | bit | 0 | *EXPERIMENTAL* Enable various additional features targeting |
@@ -193,6 +197,8 @@ Interfaces
193197
| ``data_*`` | Load-store unit interface, see :ref:`load-store-unit` |
194198
+-------------------------+------------------------------------------------------------------------+
195199
| ``irq_*`` | Interrupt inputs, see :ref:`exceptions-interrupts` |
200+
+-------------------------+-------------------------+-----+----------------------------------------+
201+
| ``scramble_*`` | Scrambling key interface, see :ref:`icache` |
196202
+-------------------------+------------------------------------------------------------------------+
197203
| ``debug_*`` | Debug interface, see :ref:`debug-support` |
198204
+-------------------------+------------------------------------------------------------------------+

‎pythondata_cpu_ibex/system_verilog/doc/03_reference/icache.rst

+6
Original file line numberDiff line numberDiff line change
@@ -93,6 +93,12 @@ Indicative RAM sizes for common configurations are given in the table below:
9393
| 4kB, 4 way, 64bit line | 4 x 128 x 22bit | 4 x 128 x 64bit |
9494
+------------------------------+-----------------+------------------+
9595

96+
If ICacheScramble parameter is enabled, all RAM primitives are replaced with scrambling RAM primitive.
97+
For more information about how scrambling works internally (see :file:`vendor/lowrisc_ip/ip/prim/doc/prim_ram_1p_scr.md`).
98+
Interface for receiving scrambling key follows req / ack protocol.
99+
Ibex first requests a new ephemeral key by asserting the request (`scramble_req_o) and when a fresh valid key is indicated by `scramble_key_valid_i, it deasserts the request.
100+
Note that in current implementation, it is assumed req/ack protocol is synchronized before arriving to Ibex top level.
101+
96102
Sub Unit Description
97103
--------------------
98104

‎pythondata_cpu_ibex/system_verilog/dv/riscv_compliance/ibex_riscv_compliance.core

+15-9
Original file line numberDiff line numberDiff line change
@@ -5,24 +5,23 @@ CAPI=2:
55
name: "lowrisc:ibex:ibex_riscv_compliance:0.1"
66
description: "Ibex simulation for RISC-V compliance testing (using Verilator)"
77
filesets:
8-
files_sim_verilator:
8+
files_sim:
99
depend:
10-
- lowrisc:dv_verilator:memutil_verilator
11-
- lowrisc:dv_verilator:simutil_verilator
1210
- lowrisc:ibex:ibex_top_tracing
1311
- lowrisc:ibex:sim_shared
14-
1512
files:
1613
- rtl/ibex_riscv_compliance.sv
17-
- ibex_riscv_compliance.cc: { file_type: cppSource }
1814
- rtl/riscv_testutil.sv
1915
file_type: systemVerilogSource
2016

21-
files_verilator_waiver:
17+
files_verilator:
18+
depend:
19+
- lowrisc:dv_verilator:memutil_verilator
20+
- lowrisc:dv_verilator:simutil_verilator
2221
files:
22+
- ibex_riscv_compliance.cc: { file_type: cppSource }
2323
- lint/verilator_waiver.vlt: {file_type: vlt}
2424

25-
2625
parameters:
2726
RV32E:
2827
datatype: int
@@ -102,12 +101,18 @@ parameters:
102101
default: 0
103102
description: "Enables security hardening features (EXPERIMENTAL) [0/1]"
104103

104+
ICacheScramble:
105+
datatype: int
106+
paramtype: vlogparam
107+
default: 0
108+
description: "Enables ICache scrambling feature (EXPERIMENTAL) [0/1]"
109+
105110
targets:
106111
sim:
107112
default_tool: verilator
108113
filesets:
109-
- tool_verilator ? (files_verilator_waiver)
110-
- files_sim_verilator
114+
- files_sim
115+
- tool_verilator ? (files_verilator)
111116
parameters:
112117
- RV32E
113118
- RV32M
@@ -122,6 +127,7 @@ targets:
122127
- PMPGranularity
123128
- PMPNumRegions
124129
- SecureIbex
130+
- ICacheScramble
125131
toplevel: ibex_riscv_compliance
126132
tools:
127133
verilator:

‎pythondata_cpu_ibex/system_verilog/dv/riscv_compliance/rtl/ibex_riscv_compliance.sv

+48-42
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,7 @@ module ibex_riscv_compliance (
2828
parameter bit ICacheECC = 1'b0;
2929
parameter bit BranchPredictor = 1'b0;
3030
parameter bit SecureIbex = 1'b0;
31+
parameter bit ICacheScramble = 1'b0;
3132

3233
logic clk_sys, rst_sys_n;
3334

@@ -80,7 +81,6 @@ module ibex_riscv_compliance (
8081
assign cfg_device_addr_base[TestUtilDevice] = 32'h20000;
8182
assign cfg_device_addr_mask[TestUtilDevice] = ~32'h3FF; // 1 kB
8283

83-
8484
bus #(
8585
.NrDevices (NrDevices),
8686
.NrHosts (NrHosts ),
@@ -127,53 +127,59 @@ module ibex_riscv_compliance (
127127
.ICacheECC (ICacheECC ),
128128
.BranchPredictor (BranchPredictor ),
129129
.SecureIbex (SecureIbex ),
130+
.ICacheScramble (ICacheScramble ),
130131
.DmHaltAddr (32'h00000000 ),
131132
.DmExceptionAddr (32'h00000000 )
132133
) u_top (
133-
.clk_i (clk_sys ),
134-
.rst_ni (rst_sys_n ),
134+
.clk_i (clk_sys ),
135+
.rst_ni (rst_sys_n ),
135136

136-
.test_en_i ('b0 ),
137-
.scan_rst_ni (1'b1 ),
138-
.ram_cfg_i ('b0 ),
137+
.test_en_i ('b0 ),
138+
.scan_rst_ni (1'b1 ),
139+
.ram_cfg_i ('b0 ),
139140

140-
.hart_id_i (32'b0 ),
141+
.hart_id_i (32'b0 ),
141142
// First instruction executed is at 0x0 + 0x80
142-
.boot_addr_i (32'h00000000 ),
143-
144-
.instr_req_o (host_req[CoreI] ),
145-
.instr_gnt_i (host_gnt[CoreI] ),
146-
.instr_rvalid_i (host_rvalid[CoreI]),
147-
.instr_addr_o (host_addr[CoreI] ),
148-
.instr_rdata_i (host_rdata[CoreI] ),
149-
.instr_rdata_intg_i ('0 ),
150-
.instr_err_i (host_err[CoreI] ),
151-
152-
.data_req_o (host_req[CoreD] ),
153-
.data_gnt_i (host_gnt[CoreD] ),
154-
.data_rvalid_i (host_rvalid[CoreD]),
155-
.data_we_o (host_we[CoreD] ),
156-
.data_be_o (host_be[CoreD] ),
157-
.data_addr_o (host_addr[CoreD] ),
158-
.data_wdata_o (host_wdata[CoreD] ),
159-
.data_wdata_intg_o ( ),
160-
.data_rdata_i (host_rdata[CoreD] ),
161-
.data_rdata_intg_i ('0 ),
162-
.data_err_i (host_err[CoreD] ),
163-
164-
.irq_software_i (1'b0 ),
165-
.irq_timer_i (1'b0 ),
166-
.irq_external_i (1'b0 ),
167-
.irq_fast_i (15'b0 ),
168-
.irq_nm_i (1'b0 ),
169-
170-
.debug_req_i ('b0 ),
171-
.crash_dump_o ( ),
172-
173-
.fetch_enable_i ('b1 ),
174-
.alert_minor_o ( ),
175-
.alert_major_o ( ),
176-
.core_sleep_o ( )
143+
.boot_addr_i (32'h00000000 ),
144+
145+
.instr_req_o (host_req[CoreI] ),
146+
.instr_gnt_i (host_gnt[CoreI] ),
147+
.instr_rvalid_i (host_rvalid[CoreI]),
148+
.instr_addr_o (host_addr[CoreI] ),
149+
.instr_rdata_i (host_rdata[CoreI] ),
150+
.instr_rdata_intg_i ('0 ),
151+
.instr_err_i (host_err[CoreI] ),
152+
153+
.data_req_o (host_req[CoreD] ),
154+
.data_gnt_i (host_gnt[CoreD] ),
155+
.data_rvalid_i (host_rvalid[CoreD]),
156+
.data_we_o (host_we[CoreD] ),
157+
.data_be_o (host_be[CoreD] ),
158+
.data_addr_o (host_addr[CoreD] ),
159+
.data_wdata_o (host_wdata[CoreD] ),
160+
.data_wdata_intg_o ( ),
161+
.data_rdata_i (host_rdata[CoreD] ),
162+
.data_rdata_intg_i ('0 ),
163+
.data_err_i (host_err[CoreD] ),
164+
165+
.irq_software_i (1'b0 ),
166+
.irq_timer_i (1'b0 ),
167+
.irq_external_i (1'b0 ),
168+
.irq_fast_i (15'b0 ),
169+
.irq_nm_i (1'b0 ),
170+
171+
.scramble_key_valid_i ('0 ),
172+
.scramble_key_i ('0 ),
173+
.scramble_nonce_i ('0 ),
174+
.scramble_req_o ( ),
175+
176+
.debug_req_i ('b0 ),
177+
.crash_dump_o ( ),
178+
179+
.fetch_enable_i ('b1 ),
180+
.alert_minor_o ( ),
181+
.alert_major_o ( ),
182+
.core_sleep_o ( )
177183
);
178184

179185
// SRAM block for instruction and data storage

‎pythondata_cpu_ibex/system_verilog/dv/uvm/core_ibex/ibex_dv.f

+21
Original file line numberDiff line numberDiff line change
@@ -24,13 +24,34 @@
2424
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_39_32_dec.sv
2525
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_enc.sv
2626
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_inv_72_64_dec.sv
27+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_prince.sv
28+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_subst_perm.sv
29+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_enc.sv
30+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_28_22_dec.sv
31+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_enc.sv
32+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_39_32_dec.sv
33+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_enc.sv
34+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_72_64_dec.sv
2735

2836
// Until this list is generated by FuseSoC, we have to use manually generated
2937
// wrappers around the prim_* modules to instantiate the prim_generic_* ones,
3038
// see https://github.com/lowRISC/ibex/issues/893.
3139
${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_pkg.sv
40+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_util_pkg.sv
3241
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_pkg.sv
42+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_dec.sv
43+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_22_16_enc.sv
44+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_dec.sv
45+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_64_57_enc.sv
46+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_dec.sv
47+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_22_16_enc.sv
48+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_dec.sv
49+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_39_32_enc.sv
50+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_dec.sv
51+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_secded_hamming_72_64_enc.sv
3352
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_pkg.sv
53+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_adv.sv
54+
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim/rtl/prim_ram_1p_scr.sv
3455
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_ram_1p.sv
3556
${PRJ_DIR}/dv/uvm/core_ibex/common/prim/prim_ram_1p.sv
3657
${PRJ_DIR}/vendor/lowrisc_ip/ip/prim_generic/rtl/prim_generic_clock_gating.sv

‎pythondata_cpu_ibex/system_verilog/dv/uvm/core_ibex/tb/core_ibex_tb_top.sv

+41-33
Original file line numberDiff line numberDiff line change
@@ -10,6 +10,7 @@ module core_ibex_tb_top;
1010
import core_ibex_test_pkg::*;
1111

1212
wire clk;
13+
wire scramble_req;
1314
wire rst_n;
1415

1516
clk_rst_if ibex_clk_if(.clk(clk), .rst_n(rst_n));
@@ -63,6 +64,7 @@ module core_ibex_tb_top;
6364
parameter bit ICacheECC = 1'b0;
6465
parameter bit BranchPredictor = 1'b0;
6566
parameter bit SecureIbex = 1'b0;
67+
parameter bit ICacheScramble = 1'b0;
6668

6769
ibex_top_tracing #(
6870
.DmHaltAddr (32'h`BOOT_ADDR + 'h0 ),
@@ -79,6 +81,7 @@ module core_ibex_tb_top;
7981
.ICache (ICache ),
8082
.ICacheECC (ICacheECC ),
8183
.SecureIbex (SecureIbex ),
84+
.ICacheScramble (ICacheScramble ),
8285
.BranchPredictor (BranchPredictor )
8386
) dut (
8487
.clk_i (clk ),
@@ -91,39 +94,44 @@ module core_ibex_tb_top;
9194
.hart_id_i (32'b0 ),
9295
.boot_addr_i (32'h`BOOT_ADDR ), // align with spike boot address
9396

94-
.instr_req_o (instr_mem_vif.request),
95-
.instr_gnt_i (instr_mem_vif.grant ),
96-
.instr_rvalid_i (instr_mem_vif.rvalid ),
97-
.instr_addr_o (instr_mem_vif.addr ),
98-
.instr_rdata_i (instr_mem_vif.rdata ),
99-
.instr_rdata_intg_i (instr_mem_vif.rintg ),
100-
.instr_err_i (instr_mem_vif.error ),
101-
102-
.data_req_o (data_mem_vif.request ),
103-
.data_gnt_i (data_mem_vif.grant ),
104-
.data_rvalid_i (data_mem_vif.rvalid ),
105-
.data_addr_o (data_mem_vif.addr ),
106-
.data_we_o (data_mem_vif.we ),
107-
.data_be_o (data_mem_vif.be ),
108-
.data_rdata_i (data_mem_vif.rdata ),
109-
.data_rdata_intg_i (data_mem_vif.rintg ),
110-
.data_wdata_o (data_mem_vif.wdata ),
111-
.data_wdata_intg_o (data_mem_vif.wintg ),
112-
.data_err_i (data_mem_vif.error ),
113-
114-
.irq_software_i (irq_vif.irq_software ),
115-
.irq_timer_i (irq_vif.irq_timer ),
116-
.irq_external_i (irq_vif.irq_external ),
117-
.irq_fast_i (irq_vif.irq_fast ),
118-
.irq_nm_i (irq_vif.irq_nm ),
119-
120-
.debug_req_i (dut_if.debug_req ),
121-
.crash_dump_o ( ),
122-
123-
.fetch_enable_i (dut_if.fetch_enable ),
124-
.alert_minor_o (dut_if.alert_minor ),
125-
.alert_major_o (dut_if.alert_major ),
126-
.core_sleep_o (dut_if.core_sleep )
97+
.instr_req_o (instr_mem_vif.request ),
98+
.instr_gnt_i (instr_mem_vif.grant ),
99+
.instr_rvalid_i (instr_mem_vif.rvalid ),
100+
.instr_addr_o (instr_mem_vif.addr ),
101+
.instr_rdata_i (instr_mem_vif.rdata ),
102+
.instr_rdata_intg_i (instr_mem_vif.rintg ),
103+
.instr_err_i (instr_mem_vif.error ),
104+
105+
.data_req_o (data_mem_vif.request ),
106+
.data_gnt_i (data_mem_vif.grant ),
107+
.data_rvalid_i (data_mem_vif.rvalid ),
108+
.data_addr_o (data_mem_vif.addr ),
109+
.data_we_o (data_mem_vif.we ),
110+
.data_be_o (data_mem_vif.be ),
111+
.data_rdata_i (data_mem_vif.rdata ),
112+
.data_rdata_intg_i (data_mem_vif.rintg ),
113+
.data_wdata_o (data_mem_vif.wdata ),
114+
.data_wdata_intg_o (data_mem_vif.wintg ),
115+
.data_err_i (data_mem_vif.error ),
116+
117+
.irq_software_i (irq_vif.irq_software ),
118+
.irq_timer_i (irq_vif.irq_timer ),
119+
.irq_external_i (irq_vif.irq_external ),
120+
.irq_fast_i (irq_vif.irq_fast ),
121+
.irq_nm_i (irq_vif.irq_nm ),
122+
123+
.scramble_key_valid_i ('0 ),
124+
.scramble_key_i ('0 ),
125+
.scramble_nonce_i ('0 ),
126+
.scramble_req_o ( ),
127+
128+
.debug_req_i (dut_if.debug_req ),
129+
.crash_dump_o ( ),
130+
131+
.fetch_enable_i (dut_if.fetch_enable ),
132+
.alert_minor_o (dut_if.alert_minor ),
133+
.alert_major_o (dut_if.alert_major ),
134+
.core_sleep_o (dut_if.core_sleep )
127135
);
128136

129137
// We should never see any alerts triggered in normal testing

‎pythondata_cpu_ibex/system_verilog/dv/uvm/icache/dv/ibex_icache_sim.core

+1
Original file line numberDiff line numberDiff line change
@@ -15,6 +15,7 @@ filesets:
1515
files_dv:
1616
depend:
1717
- lowrisc:dv:ibex_icache_test
18+
- lowrisc:prim:ram_1p_scr
1819
files:
1920
- tb/tb.sv
2021
file_type: systemVerilogSource

‎pythondata_cpu_ibex/system_verilog/dv/uvm/icache/dv/ibex_icache_sim_cfg.hjson

+5-3
Original file line numberDiff line numberDiff line change
@@ -23,17 +23,19 @@
2323
// Import additional common sim cfg files.
2424
import_cfgs: [
2525
// Project wide common sim cfg file
26-
"{proj_root}/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson"
26+
"{proj_root}/vendor/lowrisc_ip/dv/tools/dvsim/common_sim_cfg.hjson",
27+
"{proj_root}/vendor/lowrisc_ip/dv/verilator/memutil_dpi_scrambled_opts.hjson"
2728
]
2829

2930
build_modes: [
3031
{
3132
name: default
32-
en_build_modes: ["{tool}_icache_ecc"]
33+
en_build_modes: ["{tool}_icache_ecc",
34+
"{tool}_memutil_dpi_scrambled_build_opts"]
3335
}
3436
{
3537
name: vcs_icache_ecc
36-
build_opts: ["-gv tb.ICacheECC=1"]
38+
build_opts: ["-gv tb.ICacheECC=1 -gv tb.ICacheScramble=0"]
3739
}
3840
{
3941
name: riviera_icache_ecc

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