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‎pythondata_cpu_ibex/system_verilog/.clang-format

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BasedOnStyle: Google
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AllowShortIfStatementsOnASingleLine: false
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AllowShortLoopsOnASingleLine: false
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DerivePointerAlignment: false
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PointerAlignment: Right

‎pythondata_cpu_ibex/system_verilog/.github/ISSUE_TEMPLATE/bug.md

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---
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name: Report a bug in Ibex
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title: Report a bug in Ibex
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about: Have you found a bug in Ibex or associated tooling?
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labels: Type:Bug
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---
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<!--
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Thank you for your interest in Ibex. We are continuously improving Ibex, and your bug report will help us with that. To help us understand and reproduce your problem as quickly as possible we have prepared a little template below.
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No text in blocks starting with < !-- will be shown in the final bug report.
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You can also copy/paste images into the bug report, and you can attach files to it by simply dragging them into the issue window.
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-->
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## Observed Behavior
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<!--
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Please describe the problem you saw. Include waveforms (in VCD or Verilator/GtkWave FST format only please) and log files if possible.
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-->
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## Expected Behavior
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<!-- Please describe the behavior you expected to see instead. -->
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## Steps to reproduce the issue
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<!--
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Please help us to reproduce the issue you're seeing by including a detailed description of what you did to get to the problem.
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For example:
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* What command did you run? (Also include the output of the command.)
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* What parameters/defines did you set?
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* Did you make modifications to the source code?
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-->
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## My Environment
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<!--
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Let us know how you're using Ibex. This helps us to better understand your problem and find a solution more quickly.
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-->
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**EDA tool and version:**
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<!--
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If you are using an EDA tool to work with Ibex let us know which tool and which version you're using.
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For example, "Xilinx Vivado 2020.1" or "Synopsys VCS 2020.03-SP1"
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-->
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**Operating system:**
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<!--
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Please let us know the operating system/Linux distribution you're using.
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For example "Ubuntu Linux 18.04" or "CentOS 7.3".
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-->
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**Version of the Ibex source code:**
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<!--
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Which version of the Ibex source code are you using?
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You can call `git rev-parse HEAD` in your Ibex source directory to get this information.
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Please also let us know if you have made changes to the code.
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-->

‎pythondata_cpu_ibex/system_verilog/.github/ISSUE_TEMPLATE/question.md

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---
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name: Ask a question related to Ibex
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title: Ask a question related to Ibex
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about: Do you have a question about (the use of) Ibex?
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labels: Type:Question
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---
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<!--
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Thank you for your interest in Ibex. To help us understand your question as quickly as possible we have prepared a little template below.
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No text in blocks starting with < !-- will be shown in the final bug report.
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You can also copy/paste images into the question, and you can attach files to it by simply dragging them into the issue window.
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-->
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<!--
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Please ask your question after this block of text, adding as much detail as possible.
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If your question is related to a specification (e.g. the RISC-V Specification), a part of our source code, or our documentation we appreciate a link or a quote from the relevant text.
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-->
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## My Environment
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<!--
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Let us know how you're using Ibex. This helps us to better understand your problem and find a solution more quickly.
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-->
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**EDA tool and version:**
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<!--
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If you are using an EDA tool to work with Ibex let us know which tool and which version you're using.
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For example, "Xilinx Vivado 2020.1" or "Synopsys VCS 2020.03-SP1"
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-->
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**Operating system:**
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<!--
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Please let us know the operating system/Linux distribution you're using.
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For example "Ubuntu Linux 18.04" or "CentOS 7.3".
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-->
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**Version of the Ibex source code:**
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<!--
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Which version of the Ibex source code are you using?
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You can call `git rev-parse HEAD` in your Ibex source directory to get this information.
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Please also let us know if you have made changes to the code.
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-->

‎pythondata_cpu_ibex/system_verilog/.gitignore

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# Build output
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build
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# Common editor/IDE config and temporary files
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.project
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.vscode/
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.sw[a-p]
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tags
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*~
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# ibex_tracer log file
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trace_core_*.log
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# Simple system output files
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ibex_simple_system.log
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ibex_simple_system_pcount.csv
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# Python cache files
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__pycache__
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# This is generated by VCS when running DV simulations with WAVE=1.
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/dv/uvm/core_ibex/ucli.key
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# This is generated by UVM when running simulations and doesn't seem
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# to be something you can disable.
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/dv/uvm/core_ibex/tr_db.log
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# This is the default output directory in dv/uvm/core_ibex and
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# contains auto-generated files from building and running tests.
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/dv/uvm/core_ibex/out
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# This is generated by Questa tool when running DV simulations
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modelsim.ini
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# This is generated by Xcelium when running DV simulations, even with WAVE=0
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/dv/uvm/core_ibex/waves.shm

‎pythondata_cpu_ibex/system_verilog/.svlint.toml

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# Copyright lowRISC contributors.
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# Licensed under the Apache License, Version 2.0, see LICENSE for details.
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# SPDX-License-Identifier: Apache-2.0
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#
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# Rules for svlint, a SystemVerilog linter commonly used in editors.
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# The configuration matches the lowRISC SystemVerilog style guide at
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# https://github.com/lowRISC/style-guides/blob/master/VerilogCodingStyle.md.
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# See https://github.com/dalance/svlint/blob/master/RULES.md for a list of rules.
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[option]
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exclude_paths = ["build.*", "sw/.*", ".sv.tpl$", "vendor/.*"]
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[rules]
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case_default = true
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enum_with_type = true
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for_with_begin = true
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function_same_as_system_function = true
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function_with_automatic = true
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generate_for_with_label = true
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generate_if_with_label = true
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generate_keyword_forbidden = true
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generate_keyword_required = false
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genvar_declaration_in_loop = true
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genvar_declaration_out_loop = false
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if_with_begin = true
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inout_with_tri = false
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input_with_var = false
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interface_port_with_modport = false
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legacy_always = false
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level_sensitive_always = true
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loop_variable_declaration = true
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non_ansi_module = true
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output_with_var = false
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parameter_in_package = false
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priority_keyword = true
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tab_character = true
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unique0_keyword = false
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unique_keyword = false
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wire_reg = true
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generate_keyword = false
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tab_charactor = false
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genvar_declaration = false

‎pythondata_cpu_ibex/system_verilog/CONTRIBUTING.md

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## Git Considerations
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- Create your branch to commit your changes and then create a Pull Request.
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- Separate subject from body with a blank line.
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- Limit the subject line to 50 characters.
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- Capitalize the subject line.
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- Do not end the subject line with a period.
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- Use the imperative mood in the subject line.
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- Use the present tense ("Add feature" not "Added feature").
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- Wrap the body at 72 characters.
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- Use the body to explain what and why vs. how.
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For a detailed why and how please refer to one of the multiple [resources](https://chris.beams.io/posts/git-commit/) regarding git commit messages.
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If you use `vi` for your commit message, consider to put the following snippet inside your `~/.vimrc`:
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```
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autocmd Filetype gitcommit setlocal spell textwidth=72
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```

‎pythondata_cpu_ibex/system_verilog/CREDITS.md

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Credits
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=======
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Ibex has originally been developed by the PULP team at ETH Zürich and
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University of Bologna under the name Zero-riscy. In December 2018, Ibex has
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been contributed to lowRISC who is maintaining and advancing the design since
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then.
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Throughout the years, Ibex has seen contributions from many people and we at
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lowRISC are very thankful for all of them. This file lists the many people who
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contributed to what is called Ibex today. If you made a contribution to Ibex
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in the form of source code, bug reports, testing, marketing, or any other form,
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please feel free to open a pull request to get your name added to this file.
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- Alex Bradbury
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- Andreas Traber
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- Antonio Pullini
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- Eunchan Kim
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- Florian Zaruba
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- Francesco Conti
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- Germain Haugou
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- Greg Chadwick
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- Igor Loi
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- Ioannis Karageorgos
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- Markus Wegmann
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- Ivan Ribeiro
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- Matthias Baer
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- Michael Gautschi
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- Michael Schaffner
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- Nils Graf
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- Noah Huesser
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- Noam Gallmann
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- Pasquale Davide Schiavone
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- Philipp Wagner
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- Pirmin Vogel
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- Rahul Behl
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- Rhys Thomas
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- Renzo Andri
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- Robert Schilling
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- Scott Johnson
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- Stefan Wallentowitz
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- Sven Stucki
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- Tao Liu
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- Tobias Wölfel
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- Tom Roberts
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- Udi Jonnalagadda

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