Merge commit '02ccf9e5d066fbb8132ba712314558da974c3601'

Author: timvideos-robot

pythondata_cpu_ibex/system_verilog/.gitignore

@@ -18,19 +18,6 @@ ibex_simple_system_pcount.csv
 # Python cache files
 __pycache__
 
-# This is generated by VCS when running DV simulations with WAVE=1.
-/dv/uvm/core_ibex/ucli.key
-
-# This is generated by UVM when running simulations and doesn't seem
-# to be something you can disable.
-/dv/uvm/core_ibex/tr_db.log
-
-# This is the default output directory in dv/uvm/core_ibex and
-# contains auto-generated files from building and running tests.
-/dv/uvm/core_ibex/out
-
 # This is generated by Questa tool when running DV simulations
 modelsim.ini
 
-# This is generated by Xcelium when running DV simulations, even with WAVE=0
-/dv/uvm/core_ibex/waves.shm

pythondata_cpu_ibex/system_verilog/__init__.py

@@ -67,6 +67,7 @@ steps:
       displayName: Run RISC-V Compliance test for Ibex RV32IMC for ${{ config }}
 
     - bash: |
+        source ci/setup-cosim.sh
         # Build simple system with co-simulation
         fusesoc --cores-root=. run --target=sim --setup --build lowrisc:ibex:ibex_simple_system_cosim $IBEX_CONFIG_OPTS
 

pythondata_cpu_ibex/system_verilog/ci/ibex-rtl-ci-steps.yml

@@ -33,9 +33,9 @@ case "$ID-$VERSION_ID" in
     $SUDO_CMD apt-get update
 
     # Make spike-cosim repository available
-    curl -Ls https://download.opensuse.org/repositories/home:gac_lowrisc/xUbuntu_18.04/Release.key | $SUDO_CMD apt-key add -
-    $SUDO_CMD sh -c "echo 'deb http://download.opensuse.org/repositories/home:/gac_lowrisc/xUbuntu_18.04/ /' > /etc/apt/sources.list.d/spike-cosim.list" sudo apt update
-    $SUDO_CMD apt-get update
+    #curl -Ls https://download.opensuse.org/repositories/home:gac_lowrisc/xUbuntu_18.04/Release.key | $SUDO_CMD apt-key add -
+    #$SUDO_CMD sh -c "echo 'deb http://download.opensuse.org/repositories/home:/gac_lowrisc/xUbuntu_18.04/ /' > /etc/apt/sources.list.d/spike-cosim.list" sudo apt update
+    #$SUDO_CMD apt-get update
 
     # Packaged dependencies
     # Install python3-yaml through apt to get a version with libyaml bindings,
@@ -58,28 +58,34 @@ case "$ID-$VERSION_ID" in
         bison \
         libelf-dev \
         clang-format \
+        wget \
         "verilator-$VERILATOR_VERSION" \
-        "ibex-cosim-$IBEX_COSIM_VERSION" \
         xz-utils
 
-      # Python dependencies
-      #
-      # Updating pip and setuptools is required to have these tools properly
-      # parse Python-version metadata, which some packages uses to specify that
-      # an older version of a package must be used for a certain Python version.
-      # If that information is not read, pip installs the latest version, which
-      # then fails to run.
-      $SUDO_CMD pip3 install -U pip setuptools
+    wget https://storage.googleapis.com/ibex-cosim-builds/ibex-cosim-$IBEX_COSIM_VERSION.tar.gz
+    $SUDO_CMD mkdir -p /tools/riscv-isa-sim
+    $SUDO_CMD chmod 777 /tools/riscv-isa-sim
+    $SUDO_CMD tar -C /tools/riscv-isa-sim -xvzf ibex-cosim-$IBEX_COSIM_VERSION.tar.gz --strip-components=1
+    echo "##vso[task.prependpath]/tools/riscv-isa-sim/bin"
+
+    # Python dependencies
+    #
+    # Updating pip and setuptools is required to have these tools properly
+    # parse Python-version metadata, which some packages uses to specify that
+    # an older version of a package must be used for a certain Python version.
+    # If that information is not read, pip installs the latest version, which
+    # then fails to run.
+    $SUDO_CMD pip3 install -U pip setuptools
 
-      $SUDO_CMD pip3 install -r python-requirements.txt
+    $SUDO_CMD pip3 install -r python-requirements.txt
 
-      # Install Verible
-      mkdir -p build/verible
-      cd build/verible
-      curl -Ls -o verible.tar.gz "https://github.com/google/verible/releases/download/$VERIBLE_VERSION/verible-$VERIBLE_VERSION-Ubuntu-$VERSION_ID-$VERSION_CODENAME-x86_64.tar.gz"
-      $SUDO_CMD mkdir -p /tools/verible && $SUDO_CMD chmod 777 /tools/verible
-      tar -C /tools/verible -xf verible.tar.gz --strip-components=1
-      echo "##vso[task.prependpath]/tools/verible/bin"
+    # Install Verible
+    mkdir -p build/verible
+    cd build/verible
+    curl -Ls -o verible.tar.gz "https://github.com/google/verible/releases/download/$VERIBLE_VERSION/verible-$VERIBLE_VERSION-Ubuntu-$VERSION_ID-$VERSION_CODENAME-x86_64.tar.gz"
+    $SUDO_CMD mkdir -p /tools/verible && $SUDO_CMD chmod 777 /tools/verible
+    tar -C /tools/verible -xf verible.tar.gz --strip-components=1
+    echo "##vso[task.prependpath]/tools/verible/bin"
     ;;
 
   *)

pythondata_cpu_ibex/system_verilog/ci/install-build-deps.sh

@@ -0,0 +1,3 @@
+#!/bin/sh
+
+export PKG_CONFIG_PATH=/tools/riscv-isa-sim/lib/pkgconfig:$PATH

pythondata_cpu_ibex/system_verilog/ci/setup-cosim.sh

@@ -7,10 +7,10 @@
 # end up as float otherwise).
 variables:
   VERILATOR_VERSION: "4.104"
-  IBEX_COSIM_VERSION: "0.2"
+  IBEX_COSIM_VERSION: "9b68f2f9"
   RISCV_TOOLCHAIN_TAR_VERSION: "20220210-1"
   RISCV_TOOLCHAIN_TAR_VARIANT: "lowrisc-toolchain-gcc-rv32imcb"
   RISCV_COMPLIANCE_GIT_VERSION: "844c6660ef3f0d9b96957991109dfd80cc4938e2"
   VERIBLE_VERSION: "v0.0-2135-gb534c1fe"
   # lowRISC-internal version numbers of Ibex-specific Spike builds.
-  SPIKE_IBEX_VERSION: "20220308-git-20a886cba76dd80a23b548743ab3c73b19f65e41"
+  SPIKE_IBEX_VERSION: "20220817-git-eccdcb15c3e51b4f7906c7b42fb824f24a4338a2"

pythondata_cpu_ibex/system_verilog/ci/vars.yml

@@ -5,8 +5,8 @@ Ibex is a standards-compliant 32 bit RISC-V processor.
 It follows these specifications:
 
 * `RISC-V Instruction Set Manual, Volume I: User-Level ISA, document version 20190608-Base-Ratified (June 8, 2019) <https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-spec-20190608.pdf>`_
-* `RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20190608-Base-Ratified (June 8, 2019) <https://github.com/riscv/riscv-isa-manual/releases/download/Ratified-IMFDQC-and-Priv-v1.11/riscv-privileged-20190608.pdf>`_.
-  Ibex implements the Machine ISA version 1.11.
+* `RISC-V Instruction Set Manual, Volume II: Privileged Architecture, document version 20211203 (December 4, 2021) <https://github.com/riscv/riscv-isa-manual/releases/download/Priv-v1.12/riscv-privileged-20211203.pdf>`_.
+  Ibex implements the Machine ISA version 1.12.
 * `RISC-V External Debug Support, version 0.13.2 <https://content.riscv.org/wp-content/uploads/2019/03/riscv-debug-release.pdf>`_
 * `RISC-V Bit-Manipulation Extension, version 1.0.0 <https://github.com/riscv/riscv-bitmanip/releases/download/1.0.0/bitmanip-1.0.0-38-g865e7a7.pdf>`_ and `version 0.93 (draft from January 10, 2021) <https://github.com/riscv/riscv-bitmanip/blob/master/bitmanip-0.93.pdf>`_
 * `PMP Enhancements for memory access and execution prevention on Machine mode (Smepmp) version 0.9.3 <https://github.com/riscv/riscv-tee/blob/61455747230a26002d741f64879dd78cc9689323/Smepmp/Smepmp.pdf>`_

pythondata_cpu_ibex/system_verilog/doc/01_overview/compliance.rst

@@ -81,13 +81,13 @@ The possible ``mcause`` values for an internal interrupt as listed below:
 +-------------+-------------------------------------------------------------------------------------------------------------+
 | ``mcause``  | Description                                                                                                 |
 +-------------+-------------------------------------------------------------------------------------------------------------+
-| 0xFFFFFFFE0 | Load integrity error internal interrupt.                                                                    |
+| 0xFFFFFFE0  | Load integrity error internal interrupt.                                                                    |
 |             | Only generated when SecureIbex == 0.                                                                        |
 |             | ``mtval`` gives the faulting address.                                                                       |
 |             | The interrupt will be taken at most one instruction after the faulting load.                                |
 |             | In particular a load or store immediately after a faulting load may execute before the interrupt is taken.  |
 +-------------+-------------------------------------------------------------------------------------------------------------+
-| 0x80000001F | External NMI                                                                                                |
+| 0x8000001F  | External NMI                                                                                                |
 +-------------+-------------------------------------------------------------------------------------------------------------+
 
 Recoverable Non-Maskable Interrupt

pythondata_cpu_ibex/system_verilog/doc/03_reference/exception_interrupts.rst

@@ -33,7 +33,8 @@
 
 SpikeCosim::SpikeCosim(const std::string &isa_string, uint32_t start_pc,
                        uint32_t start_mtvec, const std::string &trace_log_path,
-                       bool secure_ibex, bool icache_en)
+                       bool secure_ibex, bool icache_en,
+                       uint32_t pmp_num_regions, uint32_t pmp_granularity)
     : nmi_mode(false), pending_iside_error(false) {
   FILE *log_file = nullptr;
   if (trace_log_path.length() != 0) {
@@ -52,11 +53,11 @@ SpikeCosim::SpikeCosim(const std::string &isa_string, uint32_t start_pc,
       isa_parser.get(), DEFAULT_VARCH, this, 0, false, log_file, std::cerr);
 #endif
 
+  processor->set_pmp_num(pmp_num_regions);
+  processor->set_pmp_granularity(1 << (pmp_granularity + 2));
   processor->set_ibex_flags(secure_ibex, icache_en);
 
-  processor->set_mmu_capability(IMPL_MMU_SBARE);
-  processor->get_state()->pc = start_pc;
-  processor->get_state()->mtvec->write(start_mtvec);
+  initial_proc_setup(start_pc, start_mtvec);
 
   if (log) {
     processor->set_debug(true);
@@ -437,6 +438,21 @@ void SpikeCosim::leave_nmi_mode() {
 #endif
 }
 
+void SpikeCosim::initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec) {
+  processor->get_state()->pc = start_pc;
+  processor->get_state()->mtvec->write(start_mtvec);
+
+  processor->get_state()->csrmap[CSR_MARCHID] =
+      std::make_shared<const_csr_t>(processor.get(), CSR_MARCHID, IBEX_MARCHID);
+
+  processor->set_mmu_capability(IMPL_MMU_SBARE);
+
+  for (int i = 0; i < processor->TM.count(); ++i) {
+    processor->TM.tdata2_write(processor.get(), i, 0);
+    processor->TM.tdata1_write(processor.get(), i, 0x28001048);
+  }
+}
+
 void SpikeCosim::set_mip(uint32_t mip) {
   processor->get_state()->mip->write_with_mask(0xffffffff, mip);
 }
@@ -461,11 +477,29 @@ void SpikeCosim::set_debug_req(bool debug_req) {
 }
 
 void SpikeCosim::set_mcycle(uint64_t mcycle) {
-  // TODO: Spike decrements mcycle on write to hack around an issue it has with
-  // correctly writing minstret. Preferably this write would use a backdoor
-  // access and avoid that decrement but backdoor access isn't part of the
-  // public CSR interface.
-  processor->get_state()->mcycle->write(mcycle + 1);
+  uint32_t upper_mcycle = mcycle >> 32;
+  uint32_t lower_mcycle = mcycle & 0xffffffff;
+
+  // Spike decrements the MCYCLE CSR when you write to it to hack around an
+  // issue it has with incorrectly setting minstret/mcycle when there's an
+  // explicit write to them. There's no backdoor write available via the public
+  // interface to skip this. To complicate matters we can only write 32 bits at
+  // a time and get a decrement each time.
+
+  // Write the lower half first, incremented twice due to the double decrement
+  processor->get_state()->csrmap[CSR_MCYCLE]->write(lower_mcycle + 2);
+
+  if ((processor->get_state()->csrmap[CSR_MCYCLE]->read() & 0xffffffff) == 0) {
+    // If the lower half is 0 at this point then the upper half will get
+    // decremented, so increment it first.
+    upper_mcycle++;
+  }
+
+  // Set the upper half
+  processor->get_state()->csrmap[CSR_MCYCLEH]->write(upper_mcycle);
+
+  // TODO: Do a neater job of this, a more recent spike release should allow us
+  // to write all 64 bits at once at least.
 }
 
 void SpikeCosim::set_csr(const int csr_num, const uint32_t new_val) {
@@ -500,7 +534,7 @@ void SpikeCosim::clear_errors() { errors.clear(); }
 
 void SpikeCosim::fixup_csr(int csr_num, uint32_t csr_val) {
   switch (csr_num) {
-    case CSR_MSTATUS:
+    case CSR_MSTATUS: {
       reg_t mask =
           MSTATUS_MIE | MSTATUS_MPIE | MSTATUS_MPRV | MSTATUS_MPP | MSTATUS_TW;
 
@@ -511,6 +545,24 @@ void SpikeCosim::fixup_csr(int csr_num, uint32_t csr_val) {
       processor->put_csr(csr_num, new_val);
 #endif
       break;
+    }
+    case CSR_MCAUSE: {
+      uint32_t any_interrupt = csr_val & 0x80000000;
+      uint32_t int_interrupt = csr_val & 0x40000000;
+
+      reg_t new_val = (csr_val & 0x0000001f) | any_interrupt;
+
+      if (any_interrupt && int_interrupt) {
+        new_val |= 0x7fffffe0;
+      }
+
+#ifdef OLD_SPIKE
+      processor->set_csr(csr_num, new_val);
+#else
+      processor->put_csr(csr_num, new_val);
+#endif
+      break;
+    }
   }
 }
 

pythondata_cpu_ibex/system_verilog/dv/cosim/spike_cosim.cc

@@ -5,17 +5,20 @@
 #ifndef SPIKE_COSIM_H_
 #define SPIKE_COSIM_H_
 
+#include <stdint.h>
+
+#include <deque>
+#include <memory>
+#include <string>
+#include <vector>
+
 #include "cosim.h"
 #include "riscv/devices.h"
 #include "riscv/log_file.h"
 #include "riscv/processor.h"
 #include "riscv/simif.h"
 
-#include <stdint.h>
-#include <deque>
-#include <memory>
-#include <string>
-#include <vector>
+#define IBEX_MARCHID 22
 
 class SpikeCosim : public simif_t, public Cosim {
  private:
@@ -66,12 +69,15 @@ class SpikeCosim : public simif_t, public Cosim {
 
   void leave_nmi_mode();
 
+  void initial_proc_setup(uint32_t start_pc, uint32_t start_mtvec);
+
   int insn_cnt;
 
  public:
   SpikeCosim(const std::string &isa_string, uint32_t start_pc,
              uint32_t start_mtvec, const std::string &trace_log_path,
-             bool secure_ibex, bool icache_en);
+             bool secure_ibex, bool icache_en, uint32_t pmp_num_regions,
+             uint32_t pmp_granularity);
 
   // simif_t implementation
   virtual char *addr_to_mem(reg_t addr) override;

pythondata_cpu_ibex/system_verilog/dv/cosim/spike_cosim.h

@@ -33,19 +33,19 @@ RegisterModel::RegisterModel(SimCtrl *sc, CSRParams *params) : simctrl_(sc) {
     }
   }
   // mcountinhibit
-  // - MSBs are always 1: unused counters cannot be enabled
+  // - MSBs are always 0: unused counters cannot be inhibited
   // - Bit 1 is always 0: time cannot be disabled
   uint32_t mcountinhibit_mask =
       (~((0x1 << params->MHPMCounterNum) - 1) << 3) | 0x2;
-  uint32_t mcountinhibit_resval = ~((0x1 << params->MHPMCounterNum) - 1) << 3;
+  uint32_t mcountinhibit_resval = 0;
   register_map_.push_back(std::make_unique<WARLRegister>(
       0x320, &register_map_, mcountinhibit_mask, mcountinhibit_resval));
   // Performance counter setup
   for (unsigned int i = 3; i < 32; i++) {
     uint32_t reg_addr = 0x320 + i;
     if (i < (params->MHPMCounterNum + 3)) {
       register_map_.push_back(std::make_unique<WARLRegister>(
-          reg_addr, &register_map_, 0xFFFFFFFF, 0x1 << i));
+          reg_addr, &register_map_, 0xFFFFFFFF, 0x1 << (i - 3)));
     } else {
       register_map_.push_back(
           std::make_unique<NonImpRegister>(reg_addr, &register_map_));

pythondata_cpu_ibex/system_verilog/dv/cs_registers/model/register_model.cc

@@ -5,8 +5,9 @@
   project:          ibex
 
   // These keys are expected by dvsim.py, so we have to set them to something.
-  doc_server:       bogus.doc.server
-  results_server:   bogus.results.server
+  doc_server:        bogus.doc.server
+  results_server:    bogus.results.server
+  results_html_name: report.html
 
   // Default directory structure for the output
   scratch_base_path:  "{scratch_root}/{dut}.{flow}.{tool}"

pythondata_cpu_ibex/system_verilog/dv/uvm/common_project_cfg.hjson

@@ -0,0 +1,25 @@
+# This is generated by VCS when running DV simulations with WAVE=1.
+ucli.key
+
+# This is generated by UVM when running simulations and doesn't seem
+# to be something you can disable.
+tr_db.log
+
+# This is the default output directory in dv/uvm/core_ibex and
+# contains auto-generated files from building and running tests.
+out
+
+# This is generated by the Makefile based on the ibex configuration
+riscv_dv_extension/riscv_core_setting.sv
+
+# This is generated by Xcelium when running DV simulations, even with WAVE=0
+waves.shm
+
+# Log files generated by Cadence tools when running DV simulations
+xrun.history
+xrun.log
+xmsc.log
+
+# Generated by coverage
+imc.key
+mdv.log