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Dolu1990Dolu1990
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sync verilog with previous commit
1 parent 8542a57 commit 1979a64

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+38
-18
lines changed

‎pythondata_cpu_vexriscv/verilog/VexRiscv_Debug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -4763,6 +4764,7 @@ module VexRiscv (
47634764
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
47644765
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
47654766
assign dBus_rsp_payload_error = 1'b0;
4767+
assign halted = DebugPlugin_haltIt;
47664768
always @(posedge clk) begin
47674769
if(reset) begin
47684770
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

‎pythondata_cpu_vexriscv/verilog/VexRiscv_Full.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfu.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_FullCfuDebug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -46,6 +46,7 @@ module VexRiscv (
4646
input wire dBusWishbone_ERR,
4747
output wire [2:0] dBusWishbone_CTI,
4848
output wire [1:0] dBusWishbone_BTE,
49+
output wire halted,
4950
input wire clk,
5051
input wire reset,
5152
input wire debugReset
@@ -5314,6 +5315,7 @@ module VexRiscv (
53145315
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
53155316
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
53165317
assign dBus_rsp_payload_error = 1'b0;
5318+
assign halted = DebugPlugin_haltIt;
53175319
always @(posedge clk) begin
53185320
if(reset) begin
53195321
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

‎pythondata_cpu_vexriscv/verilog/VexRiscv_FullDebug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -5045,6 +5046,7 @@ module VexRiscv (
50455046
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
50465047
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
50475048
assign dBus_rsp_payload_error = 1'b0;
5049+
assign halted = DebugPlugin_haltIt;
50485050
always @(posedge clk) begin
50495051
if(reset) begin
50505052
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

‎pythondata_cpu_vexriscv/verilog/VexRiscv_IMAC.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_IMACDebug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -5337,6 +5338,7 @@ module VexRiscv (
53375338
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
53385339
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
53395340
assign dBus_rsp_payload_error = 1'b0;
5341+
assign halted = DebugPlugin_haltIt;
53405342
always @(posedge clk) begin
53415343
if(reset) begin
53425344
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

‎pythondata_cpu_vexriscv/verilog/VexRiscv_Linux.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxDebug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -6361,6 +6362,7 @@ module VexRiscv (
63616362
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
63626363
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
63636364
assign dBus_rsp_payload_error = 1'b0;
6365+
assign halted = DebugPlugin_haltIt;
63646366
always @(posedge clk) begin
63656367
if(reset) begin
63666368
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

‎pythondata_cpu_vexriscv/verilog/VexRiscv_LinuxNoDspFmax.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_Lite.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -4258,6 +4259,7 @@ module VexRiscv (
42584259
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
42594260
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
42604261
assign dBus_rsp_error = 1'b0;
4262+
assign halted = DebugPlugin_haltIt;
42614263
always @(posedge clk) begin
42624264
if(reset) begin
42634265
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

‎pythondata_cpu_vexriscv/verilog/VexRiscv_LiteDebugHwBP.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -4266,6 +4267,7 @@ module VexRiscv (
42664267
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
42674268
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
42684269
assign dBus_rsp_error = 1'b0;
4270+
assign halted = DebugPlugin_haltIt;
42694271
always @(posedge clk) begin
42704272
if(reset) begin
42714273
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

‎pythondata_cpu_vexriscv/verilog/VexRiscv_Min.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -3494,6 +3495,7 @@ module VexRiscv (
34943495
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
34953496
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
34963497
assign dBus_rsp_error = 1'b0;
3498+
assign halted = DebugPlugin_haltIt;
34973499
assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_flush = 1'b0;
34983500
always @(posedge clk) begin
34993501
if(reset) begin

‎pythondata_cpu_vexriscv/verilog/VexRiscv_MinDebugHwBP.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -3502,6 +3503,7 @@ module VexRiscv (
35023503
assign dBus_rsp_ready = ((dBus_cmd_halfPipe_valid && (! dBusWishbone_WE)) && dBusWishbone_ACK);
35033504
assign dBus_rsp_data = dBusWishbone_DAT_MISO;
35043505
assign dBus_rsp_error = 1'b0;
3506+
assign halted = DebugPlugin_haltIt;
35053507
assign IBusSimplePlugin_rspJoin_rspBuffer_c_io_flush = 1'b0;
35063508
always @(posedge clk) begin
35073509
if(reset) begin

‎pythondata_cpu_vexriscv/verilog/VexRiscv_Secure.v

+1-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

‎pythondata_cpu_vexriscv/verilog/VexRiscv_SecureDebug.v

+3-1
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// Generator : SpinalHDL v1.9.4 git head : 270018552577f3bb8e5339ee2583c9c22d324215
22
// Component : VexRiscv
3-
// Git hash : 63430af99f84cc1d11d58b556debe1cc3f238c67
3+
// Git hash : 8542a5786b26857f3ef830ae9e72eec031df42d3
44

55
`timescale 1ns/1ps
66

@@ -38,6 +38,7 @@ module VexRiscv (
3838
input wire dBusWishbone_ERR,
3939
output wire [2:0] dBusWishbone_CTI,
4040
output wire [1:0] dBusWishbone_BTE,
41+
output wire halted,
4142
input wire clk,
4243
input wire reset,
4344
input wire debugReset
@@ -8541,6 +8542,7 @@ module VexRiscv (
85418542
assign dBus_rsp_valid = _zz_dBus_rsp_valid;
85428543
assign dBus_rsp_payload_data = dBusWishbone_DAT_MISO_regNext;
85438544
assign dBus_rsp_payload_error = 1'b0;
8545+
assign halted = DebugPlugin_haltIt;
85448546
always @(posedge clk) begin
85458547
if(reset) begin
85468548
IBusCachedPlugin_fetchPc_pcReg <= externalResetVector;

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