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[FIRRTL][firtool] Add --inline-input-only-modules option to firtool (#9332)
This patch adds support for inlining modules that have only input ports (no hardware output or inout ports). Some synthesis tools treat modules without outputs as blackboxes, which can cause synthesis errors. This option allows users to inline such modules to prevent these issues. The implementation includes a new AnnotateInputOnlyModules pass that identifies modules with only input ports and annotates them with InlineAnnotation. A new --inline-input-only-modules command-line option is added to firtool to enable this feature. The pass only annotates private modules that are instantiated in the effective design. Non-hardware ports such as Probe and Integer are not counted as hardware outputs.
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Lines changed: 227 additions & 1 deletion

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‎include/circt/Dialect/FIRRTL/Passes.td‎

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@@ -918,4 +918,21 @@ def LowerDomains : Pass<"firrtl-lower-domains", "firrtl::CircuitOp"> {
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];
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}
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def AnnotateInputOnlyModules : Pass<"firrtl-annotate-input-only-modules",
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"firrtl::CircuitOp"> {
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let summary = "Annotate input-only modules with InlineAnnotation";
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let description = [{
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This pass identifies modules that have only input ports (no output or inout
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ports) and annotates them with `firrtl.passes.InlineAnnotation`. These
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modules don't produce any hardware outputs.
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Inlining these modules is necessary because some synthesis tools treat
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modules without outputs as blackboxes, which can cause synthesis errors.
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}];
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let statistics = [
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Statistic<"numAnnotated", "num-annotated", "Number of modules annotated">
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];
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}
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#endif // CIRCT_DIALECT_FIRRTL_PASSES_TD

‎include/circt/Firtool/Firtool.h‎

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@@ -143,6 +143,8 @@ class FirtoolOptions {
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bool getEmitAllBindFiles() const { return emitAllBindFiles; }
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bool shouldInlineInputOnlyModules() const { return inlineInputOnlyModules; }
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// Setters, used by the CAPI
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FirtoolOptions &setOutputFilename(StringRef name) {
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outputFilename = name;
@@ -392,6 +394,11 @@ class FirtoolOptions {
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return *this;
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}
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FirtoolOptions &setInlineInputOnlyModules(bool value) {
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inlineInputOnlyModules = value;
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return *this;
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}
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private:
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std::string outputFilename;
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@@ -446,6 +453,7 @@ class FirtoolOptions {
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bool lintStaticAsserts;
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bool lintXmrsInDesign;
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bool emitAllBindFiles;
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bool inlineInputOnlyModules;
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};
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void registerFirtoolCLOptions();

‎lib/Dialect/FIRRTL/Transforms/AnnotateInputOnlyModules.cpp‎

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//===----------------------------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file defines the AnnotateInputOnlyModules pass.
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//
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//===----------------------------------------------------------------------===//
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#include "circt/Analysis/FIRRTLInstanceInfo.h"
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#include "circt/Dialect/FIRRTL/AnnotationDetails.h"
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#include "circt/Dialect/FIRRTL/FIRRTLAnnotations.h"
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#include "circt/Dialect/FIRRTL/FIRRTLOps.h"
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#include "circt/Dialect/FIRRTL/Passes.h"
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#include "mlir/Pass/Pass.h"
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#define DEBUG_TYPE "firrtl-annotate-input-only-modules"
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namespace circt {
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namespace firrtl {
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#define GEN_PASS_DEF_ANNOTATEINPUTONLYMODULES
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#include "circt/Dialect/FIRRTL/Passes.h.inc"
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} // namespace firrtl
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} // namespace circt
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using namespace circt;
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using namespace firrtl;
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namespace {
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struct AnnotateInputOnlyModulesPass
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: public circt::firrtl::impl::AnnotateInputOnlyModulesBase<
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AnnotateInputOnlyModulesPass> {
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void runOnOperation() override;
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LogicalResult initialize(MLIRContext *context) override {
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// Cache the inline annotation.
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inlineAnno = DictionaryAttr::getWithSorted(
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context, {{StringAttr::get(context, "class"),
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StringAttr::get(context, inlineAnnoClass)}});
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return success();
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}
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mlir::DictionaryAttr inlineAnno;
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};
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} // end anonymous namespace
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void AnnotateInputOnlyModulesPass::runOnOperation() {
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auto circuit = getOperation();
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bool changed = false;
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auto &instanceInfo = getAnalysis<InstanceInfo>();
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for (auto module : circuit.getOps<FModuleOp>()) {
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// Input only modules.
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if (!instanceInfo.anyInstanceInEffectiveDesign(module) || module.isPublic())
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continue;
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// Check if the module has only input ports (no output ports)
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bool hasHardwareOutputPort =
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llvm::any_of(module.getPorts(), [&](auto port) {
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return port.direction == Direction::Out &&
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type_isa<FIRRTLBaseType>(port.type);
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});
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// If the module has only input ports, add InlineAnnotation
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if (hasHardwareOutputPort)
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continue;
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AnnotationSet annos(module);
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// Check if InlineAnnotation or DontTouchAnnotation exists
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if (annos.hasAnnotation(inlineAnnoClass) || annos.hasDontTouch())
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continue;
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LLVM_DEBUG(llvm::dbgs() << "Annotating inline annotation "
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<< module.getModuleName() << "\n");
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// Create InlineAnnotation
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annos.addAnnotations(ArrayRef<Attribute>{inlineAnno});
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annos.applyToOperation(module);
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++numAnnotated;
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changed = true;
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}
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if (!changed)
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return markAllAnalysesPreserved();
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markAnalysesPreserved<igraph::InstanceGraph, InstanceInfo>();
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}

‎lib/Dialect/FIRRTL/Transforms/CMakeLists.txt‎

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@@ -1,5 +1,6 @@
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add_circt_dialect_library(CIRCTFIRRTLTransforms
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AddSeqMemPorts.cpp
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AnnotateInputOnlyModules.cpp
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AssignOutputDirs.cpp
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BlackBoxReader.cpp
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CheckCombLoops.cpp

‎lib/Firtool/Firtool.cpp‎

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@@ -204,6 +204,13 @@ LogicalResult firtool::populateCHIRRTLToLowFIRRTL(mlir::PassManager &pm,
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pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
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createSimpleCanonicalizerPass());
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pm.addPass(firrtl::createIMDeadCodeElim());
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if (opt.shouldInlineInputOnlyModules()) {
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pm.nest<firrtl::CircuitOp>().addPass(
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firrtl::createAnnotateInputOnlyModules());
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pm.nest<firrtl::CircuitOp>().addPass(firrtl::createInliner());
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pm.nest<firrtl::CircuitOp>().nest<firrtl::FModuleOp>().addPass(
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createSimpleCanonicalizerPass());
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}
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}
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// Always run this, required for legalization.
@@ -760,6 +767,10 @@ struct FirtoolCmdOptions {
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llvm::cl::desc("Emit bindfiles for private modules"),
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llvm::cl::init(false)};
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llvm::cl::opt<bool> inlineInputOnlyModules{
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"inline-input-only-modules", llvm::cl::desc("Inline input-only modules"),
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llvm::cl::init(false)};
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//===----------------------------------------------------------------------===
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// Lint options
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//===----------------------------------------------------------------------===
@@ -811,7 +822,8 @@ circt::firtool::FirtoolOptions::FirtoolOptions()
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disableCSEinClasses(false), selectDefaultInstanceChoice(false),
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symbolicValueLowering(verif::SymbolicValueLowering::ExtModule),
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disableWireElimination(false), lintStaticAsserts(true),
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lintXmrsInDesign(true), emitAllBindFiles(false) {
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lintXmrsInDesign(true), emitAllBindFiles(false),
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inlineInputOnlyModules(false) {
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if (!clOptions.isConstructed())
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return;
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outputFilename = clOptions->outputFilename;
@@ -864,4 +876,5 @@ circt::firtool::FirtoolOptions::FirtoolOptions()
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lintStaticAsserts = clOptions->lintStaticAsserts;
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lintXmrsInDesign = clOptions->lintXmrsInDesign;
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emitAllBindFiles = clOptions->emitAllBindFiles;
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inlineInputOnlyModules = clOptions->inlineInputOnlyModules;
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}

‎test/Dialect/FIRRTL/annotate-input-only-modules.mlir‎

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// RUN: circt-opt --pass-pipeline='builtin.module(firrtl.circuit(firrtl-annotate-input-only-modules))' %s | FileCheck %s
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// Test that modules with non-hardware output ports (Probe, Integer) ARE annotated
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firrtl.circuit "ModuleWithNonHardwareOutput" {
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// CHECK-LABEL: firrtl.module @ModuleWithNonHardwareOutput
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firrtl.module @ModuleWithNonHardwareOutput(in %a: !firrtl.uint<8>, out %p: !firrtl.probe<uint<8>>, out %i: !firrtl.integer) {
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%child_x, %child_probe, %child_int = firrtl.instance child @ChildWithNonHardwareOutput(in x: !firrtl.uint<8>, out probe: !firrtl.probe<uint<8>>, out int: !firrtl.integer)
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firrtl.matchingconnect %child_x, %a : !firrtl.uint<8>
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firrtl.ref.define %p, %child_probe : !firrtl.probe<uint<8>>
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firrtl.propassign %i, %child_int : !firrtl.integer
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}
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// CHECK-LABEL: firrtl.module private @ChildWithNonHardwareOutput
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// CHECK-SAME: attributes {annotations = [{class = "firrtl.passes.InlineAnnotation"}]}
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firrtl.module private @ChildWithNonHardwareOutput(in %x: !firrtl.uint<8>, out %probe: !firrtl.probe<uint<8>>, out %int: !firrtl.integer) {
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%0 = firrtl.ref.send %x : !firrtl.uint<8>
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firrtl.ref.define %probe, %0 : !firrtl.probe<uint<8>>
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%c42_i = firrtl.integer 42
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firrtl.propassign %int, %c42_i : !firrtl.integer
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}
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}
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// Test that modules with existing annotations are preserved
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firrtl.circuit "ExistingAnnotations" {
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// CHECK-LABEL: firrtl.module @ExistingAnnotations
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firrtl.module @ExistingAnnotations(in %a: !firrtl.uint<8>) {
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%child_x = firrtl.instance child @ChildWithAnnotation(in x: !firrtl.uint<8>)
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firrtl.matchingconnect %child_x, %a : !firrtl.uint<8>
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}
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// CHECK-LABEL: firrtl.module private @ChildWithAnnotation
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// CHECK-SAME: annotations = [{class = "some.other.Annotation"}, {class = "firrtl.passes.InlineAnnotation"}]
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firrtl.module private @ChildWithAnnotation(in %x: !firrtl.uint<8>) attributes {annotations = [{class = "some.other.Annotation"}]} {
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}
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}
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// Test public modules are NOT annotated (even if input-only)
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firrtl.circuit "PublicInputOnly" {
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// CHECK-LABEL: firrtl.module @PublicInputOnly
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// CHECK-NOT: InlineAnnotation
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firrtl.module @PublicInputOnly(in %a: !firrtl.uint<8>) {
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}
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}
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firrtl.circuit "ModuleWithDontTouch" {
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// CHECK-LABEL: firrtl.module @ModuleWithDontTouch
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firrtl.module @ModuleWithDontTouch(in %a: !firrtl.uint<8>) {
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%child_x = firrtl.instance child @ChildWithNonHardwareOutput(in x: !firrtl.uint<8>)
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firrtl.matchingconnect %child_x, %a : !firrtl.uint<8>
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}
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// CHECK-LABEL: firrtl.module private @ChildWithNonHardwareOutput
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// CHECK-NOT: InlineAnnotation
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firrtl.module private @ChildWithNonHardwareOutput(in %x: !firrtl.uint<8>) attributes {annotations = [{class = "firrtl.transforms.DontTouchAnnotation"}]} {}
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}
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firrtl.circuit "Bound" {
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// CHECK-LABEL: firrtl.module @Bound
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firrtl.module @Bound(in %a: !firrtl.uint<8>) {
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%child_x = firrtl.instance child {doNotPrint} @ChildWithNonHardwareOutput(in x: !firrtl.uint<8>)
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firrtl.matchingconnect %child_x, %a : !firrtl.uint<8>
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}
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// CHECK-LABEL: firrtl.module private @ChildWithNonHardwareOutput
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// CHECK-NOT: InlineAnnotation
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firrtl.module private @ChildWithNonHardwareOutput(in %x: !firrtl.uint<8>) attributes {annotations = [{class = "firrtl.transforms.DontTouchAnnotation"}]} {}
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}

‎test/firtool/input-only.fir‎

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; RUN: firtool %s --inline-input-only-modules | FileCheck %s --check-prefix INLINE
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; RUN: firtool %s | FileCheck %s
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FIRRTL version 5.0.0
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circuit Top:
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; INLINE-NOT: module InputOnly
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; INLINE: `define ref_Top_probe input_probe
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; CHECK: module InputOnly
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; CHECK: `define ref_Top_probe input_only.input_probe
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module InputOnly:
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; Non-hardware ports must not be counted as output
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input input: UInt<1>
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output probe: Probe<UInt<1>>
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output x: Integer
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define probe = probe(input)
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propassign x, Integer(1)
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public module Top:
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input input: UInt<1>
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output probe: Probe<UInt<1>>
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output x: Integer
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inst input_only of InputOnly
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connect input_only.input, input
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define probe = input_only.probe
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propassign x, input_only.x

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