[hw,darjeeling,rtl] Increase CTN window from 1G to 2G

Razer6 · andreaskurth · commit 4b47946a11ac · 2025-10-09T11:13:47.000Z
Signed-off-by: Robert Schilling &lt;rschilling@rivosinc.com&gt;
diff --git a/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson b/hw/top_darjeeling/data/autogen/top_darjeeling.gen.hjson
@@ -3886,7 +3886,7 @@
           data_intg_passthru: "true"
           exec: True
           byte_write: True
-          size: 0x40000000
+          size: 0x80000000
         }
       }
       clock_connections:
@@ -12370,7 +12370,7 @@
               {
                 hart: 0x40000000
               }
-              size_byte: 0x40000000
+              size_byte: 0x80000000
             }
           ]
           xbar: false
diff --git a/hw/top_darjeeling/data/top_darjeeling.hjson b/hw/top_darjeeling/data/top_darjeeling.hjson
@@ -632,7 +632,7 @@
           data_intg_passthru: "true",
           exec: "True",
           byte_write: "True",
-          size: "0x40000000",
+          size: "0x80000000",
         }
       }
     },
diff --git a/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/dv/autogen/xbar_env_pkg__params.sv
@@ -29,7 +29,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h22030000, 32'h2203000f}
     }},
     '{"soc_proxy__ctn", '{
-        '{32'h40000000, 32'h7fffffff}
+        '{32'h40000000, 32'hbfffffff}
     }},
     '{"hmac", '{
         '{32'h21110000, 32'h21111fff}
diff --git a/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson b/hw/top_darjeeling/ip/xbar_main/data/autogen/xbar_main.gen.hjson
@@ -407,7 +407,7 @@
           {
             hart: 0x40000000
           }
-          size_byte: 0x40000000
+          size_byte: 0x80000000
         }
       ]
       xbar: false
diff --git a/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv b/hw/top_darjeeling/ip/xbar_main/dv/autogen/xbar_env_pkg__params.sv
@@ -32,7 +32,7 @@ tl_device_t xbar_devices[$] = '{
         '{32'h22030000, 32'h2203000f}
     }},
     '{"soc_proxy__ctn", '{
-        '{32'h40000000, 32'h7fffffff}
+        '{32'h40000000, 32'hbfffffff}
     }},
     '{"hmac", '{
         '{32'h21110000, 32'h21111fff}
diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/tl_main_pkg.sv
@@ -54,7 +54,7 @@ package tl_main_pkg;
     32'h 007fffff
   };
   localparam logic [31:0] ADDR_MASK_SOC_PROXY__CORE      = 32'h 0000000f;
-  localparam logic [31:0] ADDR_MASK_SOC_PROXY__CTN       = 32'h 3fffffff;
+  localparam logic [31:0] ADDR_SIZE_SOC_PROXY__CTN       = 32'h 80000000;
   localparam logic [31:0] ADDR_MASK_HMAC                 = 32'h 00001fff;
   localparam logic [31:0] ADDR_MASK_KMAC                 = 32'h 00000fff;
   localparam logic [31:0] ADDR_MASK_AES                  = 32'h 000000ff;
diff --git a/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv b/hw/top_darjeeling/ip/xbar_main/rtl/autogen/xbar_main.sv
@@ -1188,8 +1188,8 @@ module xbar_main (
                   ~(ADDR_MASK_SRAM_CTRL_MAIN__RAM)) == ADDR_SPACE_SRAM_CTRL_MAIN__RAM) begin
       dev_sel_s1n_49 = 3'd3;
 
-    end else if ((tl_s1n_49_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_49_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_49_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_49 = 3'd4;
 end
   end
@@ -1285,8 +1285,8 @@ end
                   ~(ADDR_MASK_SRAM_CTRL_MBOX__REGS)) == ADDR_SPACE_SRAM_CTRL_MBOX__REGS) begin
       dev_sel_s1n_55 = 6'd21;
 
-    end else if ((tl_s1n_55_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_55_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_55_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_55 = 6'd22;
 
     end else if ((tl_s1n_55_us_h2d.a_address &
@@ -1430,8 +1430,8 @@ end
                   ~(ADDR_MASK_SRAM_CTRL_MBOX__REGS)) == ADDR_SPACE_SRAM_CTRL_MBOX__REGS) begin
       dev_sel_s1n_87 = 6'd21;
 
-    end else if ((tl_s1n_87_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_87_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_87_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_87 = 6'd22;
 
     end else if ((tl_s1n_87_us_h2d.a_address &
@@ -1515,8 +1515,8 @@ end
                   ~(ADDR_MASK_KMAC)) == ADDR_SPACE_KMAC) begin
       dev_sel_s1n_88 = 4'd6;
 
-    end else if ((tl_s1n_88_us_h2d.a_address &
-                  ~(ADDR_MASK_SOC_PROXY__CTN)) == ADDR_SPACE_SOC_PROXY__CTN) begin
+    end else if (((tl_s1n_88_us_h2d.a_address < (ADDR_SPACE_SOC_PROXY__CTN + ADDR_SIZE_SOC_PROXY__CTN)) &&
+       (tl_s1n_88_us_h2d.a_address >= ADDR_SPACE_SOC_PROXY__CTN))) begin
       dev_sel_s1n_88 = 4'd7;
 
     end else if ((tl_s1n_88_us_h2d.a_address &
diff --git a/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv b/hw/top_darjeeling/rtl/autogen/top_darjeeling_pkg.sv
@@ -187,7 +187,7 @@ package top_darjeeling_pkg;
   /**
    * Peripheral size in bytes for ctn device on soc_proxy in top darjeeling.
    */
-  parameter int unsigned TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES = 32'h40000000;
+  parameter int unsigned TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES = 32'h80000000;
 
   /**
    * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
@@ -547,7 +547,7 @@ package top_darjeeling_pkg;
   /**
    * Memory size for ctn in top darjeeling.
    */
-  parameter int unsigned TOP_DARJEELING_CTN_SIZE_BYTES = 32'h40000000;
+  parameter int unsigned TOP_DARJEELING_CTN_SIZE_BYTES = 32'h80000000;
 
   /**
   * Memory base address for ram_ctn in top darjeeling.
diff --git a/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs b/hw/top_darjeeling/sw/autogen/chip/top_darjeeling.rs
@@ -271,7 +271,7 @@ pub const SOC_PROXY_CTN_BASE_ADDR: usize = 0x40000000;
 /// memory-mapped registers associated with this peripheral should have an
 /// address between #SOC_PROXY_CTN_BASE_ADDR and
 /// `SOC_PROXY_CTN_BASE_ADDR + SOC_PROXY_CTN_SIZE_BYTES`.
-pub const SOC_PROXY_CTN_SIZE_BYTES: usize = 0x40000000;
+pub const SOC_PROXY_CTN_SIZE_BYTES: usize = 0x80000000;
 
 /// Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
 ///
@@ -767,7 +767,7 @@ pub const RV_CORE_IBEX_CFG_SIZE_BYTES: usize = 0x800;
 pub const CTN_BASE_ADDR: usize = 0x40000000;
 
 /// Memory size for ctn in top darjeeling.
-pub const CTN_SIZE_BYTES: usize = 0x40000000;
+pub const CTN_SIZE_BYTES: usize = 0x80000000;
 
 /// Memory base address for ram_ret_aon in top darjeeling.
 pub const RAM_RET_AON_BASE_ADDR: usize = 0x30600000;
diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling.h b/hw/top_darjeeling/sw/autogen/top_darjeeling.h
@@ -352,7 +352,7 @@ extern "C" {
  * address between #TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and
  * `TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES`.
  */
-#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000u
+#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x80000000u
 
 /**
  * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
@@ -993,7 +993,7 @@ extern "C" {
 /**
  * Memory size for ctn in top darjeeling.
  */
-#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000u
+#define TOP_DARJEELING_CTN_SIZE_BYTES 0x80000000u
 
 /**
  * Memory base address for ram_ret_aon in top darjeeling.
diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.h
@@ -32,7 +32,7 @@
 /**
  * Memory size for soc_proxy_ctn in top darjeeling.
  */
-#define TOP_DARJEELING_CTN_SIZE_BYTES 0x40000000
+#define TOP_DARJEELING_CTN_SIZE_BYTES 0x80000000
 
 /**
  * Memory base for sram_ctrl_ret_aon_ram_ret_aon in top darjeeling.
@@ -391,7 +391,7 @@
  * address between #TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR and
  * `TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR + TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES`.
  */
-#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x40000000
+#define TOP_DARJEELING_SOC_PROXY_CTN_SIZE_BYTES 0x80000000
 /**
  * Peripheral base address for regs device on sram_ctrl_ret_aon in top darjeeling.
  *
diff --git a/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld b/hw/top_darjeeling/sw/autogen/top_darjeeling_memory.ld
@@ -14,7 +14,7 @@
  * address for whichever half of the flash contains the corresponding boot stage.
  */
 MEMORY {
-  ctn(rwx) : ORIGIN = 0x40000000, LENGTH = 0x40000000
+  ctn(rwx) : ORIGIN = 0x40000000, LENGTH = 0x80000000
   ram_ret_aon(rwx) : ORIGIN = 0x30600000, LENGTH = 0x1000
   ram_main(rwx) : ORIGIN = 0x10000000, LENGTH = 0x10000
   ram_mbox(rwx) : ORIGIN = 0x11000000, LENGTH = 0x1000

Original file line number	Diff line number	Diff line change
`@@ -3886,7 +3886,7 @@`
`3886`	`3886`	`data_intg_passthru: "true"`
`3887`	`3887`	`exec: True`
`3888`	`3888`	`byte_write: True`
`3889`		`- size: 0x40000000`
	`3889`	`+ size: 0x80000000`
`3890`	`3890`	`}`
`3891`	`3891`	`}`
`3892`	`3892`	`clock_connections:`
`@@ -12370,7 +12370,7 @@`
`12370`	`12370`	`{`
`12371`	`12371`	`hart: 0x40000000`
`12372`	`12372`	`}`
`12373`		`- size_byte: 0x40000000`
	`12373`	`+ size_byte: 0x80000000`
`12374`	`12374`	`}`
`12375`	`12375`	`]`
`12376`	`12376`	`xbar: false`
Original file line number	Diff line number	Diff line change
`@@ -632,7 +632,7 @@`
`632`	`632`	`data_intg_passthru: "true",`
`633`	`633`	`exec: "True",`
`634`	`634`	`byte_write: "True",`
`635`		`- size: "0x40000000",`
	`635`	`+ size: "0x80000000",`
`636`	`636`	`}`
`637`	`637`	`}`
`638`	`638`	`},`
Original file line number	Diff line number	Diff line change
`@@ -407,7 +407,7 @@`
`407`	`407`	`{`
`408`	`408`	`hart: 0x40000000`
`409`	`409`	`}`
`410`		`- size_byte: 0x40000000`
	`410`	`+ size_byte: 0x80000000`
`411`	`411`	`}`
`412`	`412`	`]`
`413`	`413`	`xbar: false`