Skip to content

Commit df9c841

Browse files
pamauryandreaskurth
pamaury
authored and
andreaskurth
committed
[hw] Systematically use memories full name's defines
Each memory appears twice: once using its label name (e.g. eflash) and once using its full name (e.g. flash_ctrl_mem). This commit removes all uses of the label name and switches them to the full name. Signed-off-by: Amaury Pouly <[email protected]>
1 parent 6703790 commit df9c841

File tree

10 files changed

+41
-41
lines changed

10 files changed

+41
-41
lines changed

‎hw/top_darjeeling/dv/env/chip_env_pkg.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -65,10 +65,10 @@ package chip_env_pkg;
6565

6666
// ROM digest parameters
6767
localparam uint Rom0DigestDw = 256;
68-
localparam uint Rom0MaxCheckAddr = top_darjeeling_pkg::TOP_DARJEELING_ROM0_SIZE_BYTES -
68+
localparam uint Rom0MaxCheckAddr = top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES -
6969
(Rom0DigestDw / 8);
7070
localparam uint Rom1DigestDw = 256;
71-
localparam uint Rom1MaxCheckAddr = top_darjeeling_pkg::TOP_DARJEELING_ROM1_SIZE_BYTES -
71+
localparam uint Rom1MaxCheckAddr = top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL1_ROM_SIZE_BYTES -
7272
(Rom1DigestDw / 8);
7373

7474
typedef virtual sw_logger_if sw_logger_vif;

‎hw/top_darjeeling/dv/env/seq_lib/chip_base_vseq.sv‎

Lines changed: 3 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -390,9 +390,9 @@ class chip_base_vseq #(
390390
mem_wr(.ptr(mem), .offset(offset), .data(wdata));
391391
end else begin // if (mem.get_access() == "RW")
392392
int byte_addr = offset * 4;
393-
if (byte_addr >= top_darjeeling_pkg::TOP_DARJEELING_ROM0_BASE_ADDR &&
394-
byte_addr < (top_darjeeling_pkg::TOP_DARJEELING_ROM0_BASE_ADDR +
395-
top_darjeeling_pkg::TOP_DARJEELING_ROM0_SIZE_BYTES)) begin
393+
if (byte_addr >= top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR &&
394+
byte_addr < (top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR +
395+
top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES)) begin
396396
// deposit random data to rom
397397
rom0.rom_encrypt_write32_integ(.addr(byte_addr), .data(wdata),
398398
.key(RndCnstRomCtrl0ScrKey),

‎hw/top_darjeeling/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -113,13 +113,13 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq;
113113

114114
// ePMP address entries
115115
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[0],
116-
epmp_addr_tor(top_darjeeling_pkg::TOP_DARJEELING_ROM0_BASE_ADDR))
116+
epmp_addr_tor(top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR))
117117
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[2],
118-
epmp_addr_napot(top_darjeeling_pkg::TOP_DARJEELING_ROM0_BASE_ADDR,
119-
top_darjeeling_pkg::TOP_DARJEELING_ROM0_SIZE_BYTES))
118+
epmp_addr_napot(top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR,
119+
top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_SIZE_BYTES))
120120
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[5],
121-
epmp_addr_napot(top_darjeeling_pkg::TOP_DARJEELING_RAM_CTN_BASE_ADDR,
122-
top_darjeeling_pkg::TOP_DARJEELING_RAM_CTN_SIZE_BYTES))
121+
epmp_addr_napot(top_darjeeling_pkg::TOP_DARJEELING_SOC_PROXY_RAM_CTN_BASE_ADDR,
122+
top_darjeeling_pkg::TOP_DARJEELING_SOC_PROXY_RAM_CTN_SIZE_BYTES))
123123
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[10], epmp_addr_tor(MMIO_START_ADDRESS))
124124
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[11], epmp_addr_tor(MMIO_END_ADDRESS))
125125
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[13],
@@ -128,8 +128,8 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq;
128128
// PMP NA4 address calculation is the same as the TOR calculation.
129129
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[14], epmp_addr_tor(RAM_STACK_GUARD_ADDRESS))
130130
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[15],
131-
epmp_addr_napot(top_darjeeling_pkg::TOP_DARJEELING_RAM_MAIN_BASE_ADDR,
132-
top_darjeeling_pkg::TOP_DARJEELING_RAM_MAIN_SIZE_BYTES))
131+
epmp_addr_napot(top_darjeeling_pkg::TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR,
132+
top_darjeeling_pkg::TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_SIZE_BYTES))
133133

134134
// Check interrupts.
135135
`DV_CHECK_EQ(cfg.chip_vif.mstatus_mie, 0)

‎hw/top_darjeeling/dv/tb/tb.sv‎

Lines changed: 6 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -379,7 +379,7 @@ module tb;
379379
.depth ($size(`RAM_MAIN_MEM_HIER)),
380380
.n_bits($bits(`RAM_MAIN_MEM_HIER)),
381381
.err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
382-
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_RAM_MAIN_BASE_ADDR));
382+
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_SRAM_CTRL_MAIN_RAM_BASE_ADDR));
383383
m_mem_bkdr_util[RamMain0] = ram_main0;
384384
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamMain0], `RAM_MAIN_MEM_HIER)
385385

@@ -390,7 +390,7 @@ module tb;
390390
.depth ($size(`RAM_RET_MEM_HIER)),
391391
.n_bits($bits(`RAM_RET_MEM_HIER)),
392392
.err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
393-
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_RAM_RET_AON_BASE_ADDR));
393+
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_SRAM_CTRL_RET_AON_RAM_BASE_ADDR));
394394
m_mem_bkdr_util[RamRet0] = ram_ret0;
395395
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamRet0], `RAM_RET_MEM_HIER)
396396

@@ -401,7 +401,7 @@ module tb;
401401
.depth ($size(`RAM_MBOX_MEM_HIER)),
402402
.n_bits($bits(`RAM_MBOX_MEM_HIER)),
403403
.err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
404-
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_RAM_MBOX_BASE_ADDR));
404+
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_SRAM_CTRL_MBOX_RAM_BASE_ADDR));
405405
m_mem_bkdr_util[RamMbox0] = ram_mbox0;
406406
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamMbox0], `RAM_MBOX_MEM_HIER)
407407

@@ -412,7 +412,7 @@ module tb;
412412
.depth ($size(`RAM_CTN_MEM_HIER)),
413413
.n_bits($bits(`RAM_CTN_MEM_HIER)),
414414
.err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
415-
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_RAM_CTN_BASE_ADDR));
415+
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_SOC_PROXY_RAM_CTN_BASE_ADDR));
416416
m_mem_bkdr_util[RamCtn0] = ram_ctn0;
417417
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamCtn0], `RAM_CTN_MEM_HIER)
418418

@@ -429,7 +429,7 @@ module tb;
429429
`endif
430430
.key (top_darjeeling_rnd_cnst_pkg::RndCnstRomCtrl0ScrKey),
431431
.nonce (top_darjeeling_rnd_cnst_pkg::RndCnstRomCtrl0ScrNonce),
432-
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_ROM0_BASE_ADDR));
432+
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR));
433433
m_mem_bkdr_util[Rom0] = rom0;
434434
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[Rom0], `ROM0_MEM_HIER)
435435

@@ -446,7 +446,7 @@ module tb;
446446
`endif
447447
.key (top_darjeeling_rnd_cnst_pkg::RndCnstRomCtrl1ScrKey),
448448
.nonce (top_darjeeling_rnd_cnst_pkg::RndCnstRomCtrl1ScrNonce),
449-
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_ROM0_BASE_ADDR));
449+
.system_base_addr (top_darjeeling_pkg::TOP_DARJEELING_ROM_CTRL0_ROM_BASE_ADDR));
450450
m_mem_bkdr_util[Rom1] = rom1;
451451
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[Rom1], `ROM1_MEM_HIER)
452452

‎hw/top_darjeeling/rtl/autogen/chip_darjeeling_asic.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1516,8 +1516,8 @@ module chip_darjeeling_asic #(
15161516
// Default steering to generate error response if address is not within the range
15171517
ctn_dev_sel_s1n = 1'b1;
15181518
// Steering to CTN SRAM.
1519-
if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) ==
1520-
(TOP_DARJEELING_RAM_CTN_BASE_ADDR - TOP_DARJEELING_CTN_BASE_ADDR)) begin
1519+
if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_SOC_PROXY_RAM_CTN_SIZE_BYTES-1)) ==
1520+
(TOP_DARJEELING_SOC_PROXY_RAM_CTN_BASE_ADDR - TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR)) begin
15211521
ctn_dev_sel_s1n = 1'd0;
15221522
end
15231523
end

‎hw/top_darjeeling/rtl/autogen/chip_darjeeling_cw310.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1375,8 +1375,8 @@ module chip_darjeeling_cw310 #(
13751375
// Default steering to generate error response if address is not within the range
13761376
ctn_dev_sel_s1n = 1'b1;
13771377
// Steering to CTN SRAM.
1378-
if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) ==
1379-
(TOP_DARJEELING_RAM_CTN_BASE_ADDR - TOP_DARJEELING_CTN_BASE_ADDR)) begin
1378+
if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_SOC_PROXY_RAM_CTN_SIZE_BYTES-1)) ==
1379+
(TOP_DARJEELING_SOC_PROXY_RAM_CTN_BASE_ADDR - TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR)) begin
13801380
ctn_dev_sel_s1n = 1'd0;
13811381
end
13821382
end

‎hw/top_darjeeling/templates/chiplevel.sv.tpl‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -891,8 +891,8 @@ module chip_${top["name"]}_${target["name"]} #(
891891
// Default steering to generate error response if address is not within the range
892892
ctn_dev_sel_s1n = 1'b1;
893893
// Steering to CTN SRAM.
894-
if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_RAM_CTN_SIZE_BYTES-1)) ==
895-
(TOP_DARJEELING_RAM_CTN_BASE_ADDR - TOP_DARJEELING_CTN_BASE_ADDR)) begin
894+
if ((ctn_sm1_to_s1n_tl_h2d.a_address & ~(TOP_DARJEELING_SOC_PROXY_RAM_CTN_SIZE_BYTES-1)) ==
895+
(TOP_DARJEELING_SOC_PROXY_RAM_CTN_BASE_ADDR - TOP_DARJEELING_SOC_PROXY_CTN_BASE_ADDR)) begin
896896
ctn_dev_sel_s1n = 1'd0;
897897
end
898898
end

‎hw/top_earlgrey/dv/env/chip_env_pkg.sv‎

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -68,7 +68,7 @@ package chip_env_pkg;
6868

6969
// ROM digest parameters
7070
localparam uint RomDigestDw = 256;
71-
localparam uint RomMaxCheckAddr = top_earlgrey_pkg::TOP_EARLGREY_ROM_SIZE_BYTES -
71+
localparam uint RomMaxCheckAddr = top_earlgrey_pkg::TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES -
7272
(RomDigestDw / 8);
7373

7474
typedef virtual sw_logger_if sw_logger_vif;

‎hw/top_earlgrey/dv/env/seq_lib/chip_sw_rom_e2e_asm_init_vseq.sv‎

Lines changed: 7 additions & 7 deletions
Original file line numberDiff line numberDiff line change
@@ -132,13 +132,13 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq;
132132

133133
// ePMP address entries
134134
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[0],
135-
epmp_addr_tor(top_earlgrey_pkg::TOP_EARLGREY_ROM_BASE_ADDR))
135+
epmp_addr_tor(top_earlgrey_pkg::TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR))
136136
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[2],
137-
epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_ROM_BASE_ADDR,
138-
top_earlgrey_pkg::TOP_EARLGREY_ROM_SIZE_BYTES))
137+
epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR,
138+
top_earlgrey_pkg::TOP_EARLGREY_ROM_CTRL_ROM_SIZE_BYTES))
139139
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[5],
140-
epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_EFLASH_BASE_ADDR,
141-
top_earlgrey_pkg::TOP_EARLGREY_EFLASH_SIZE_BYTES))
140+
epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR,
141+
top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES))
142142
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[10], epmp_addr_tor(MMIO_START_ADDRESS))
143143
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[11], epmp_addr_tor(MMIO_END_ADDRESS))
144144
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[13],
@@ -147,8 +147,8 @@ class chip_sw_rom_e2e_asm_init_vseq extends chip_sw_base_vseq;
147147
// PMP NA4 address calculation is the same as the TOR calculation.
148148
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[14], epmp_addr_tor(RAM_STACK_GUARD_ADDRESS))
149149
`DV_CHECK_EQ(cfg.chip_vif.pmp_addr[15],
150-
epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_RAM_MAIN_BASE_ADDR,
151-
top_earlgrey_pkg::TOP_EARLGREY_RAM_MAIN_SIZE_BYTES))
150+
epmp_addr_napot(top_earlgrey_pkg::TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR,
151+
top_earlgrey_pkg::TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_SIZE_BYTES))
152152

153153
// Check interrupts.
154154
`DV_CHECK_EQ(cfg.chip_vif.mstatus_mie, 0)

‎hw/top_earlgrey/dv/tb/tb.sv‎

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -474,7 +474,7 @@ module tb;
474474
.depth ($size(`FLASH0_DATA_MEM_HIER)),
475475
.n_bits($bits(`FLASH0_DATA_MEM_HIER)),
476476
.err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68),
477-
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_EFLASH_BASE_ADDR));
477+
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR));
478478
m_mem_bkdr_util[FlashBank0Data] = data0;
479479
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank0Data], `FLASH0_DATA_MEM_HIER)
480480

@@ -485,7 +485,7 @@ module tb;
485485
.depth ($size(`FLASH0_INFO_MEM_HIER)),
486486
.n_bits($bits(`FLASH0_INFO_MEM_HIER)),
487487
.err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68),
488-
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_EFLASH_BASE_ADDR));
488+
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR));
489489
m_mem_bkdr_util[FlashBank0Info] = info0;
490490
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank0Info], `FLASH0_INFO_MEM_HIER)
491491

@@ -496,8 +496,8 @@ module tb;
496496
.depth ($size(`FLASH1_DATA_MEM_HIER)),
497497
.n_bits($bits(`FLASH1_DATA_MEM_HIER)),
498498
.err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68),
499-
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_EFLASH_BASE_ADDR +
500-
top_earlgrey_pkg::TOP_EARLGREY_EFLASH_SIZE_BYTES /
499+
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR +
500+
top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES /
501501
flash_ctrl_top_specific_pkg::NumBanks));
502502
m_mem_bkdr_util[FlashBank1Data] = data1;
503503
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank1Data], `FLASH1_DATA_MEM_HIER)
@@ -509,8 +509,8 @@ module tb;
509509
.depth ($size(`FLASH1_INFO_MEM_HIER)),
510510
.n_bits($bits(`FLASH1_INFO_MEM_HIER)),
511511
.err_detection_scheme(mem_bkdr_util_pkg::EccHamming_76_68),
512-
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_EFLASH_BASE_ADDR +
513-
top_earlgrey_pkg::TOP_EARLGREY_EFLASH_SIZE_BYTES /
512+
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_BASE_ADDR +
513+
top_earlgrey_pkg::TOP_EARLGREY_FLASH_CTRL_MEM_SIZE_BYTES /
514514
flash_ctrl_top_specific_pkg::NumBanks));
515515
m_mem_bkdr_util[FlashBank1Info] = info1;
516516
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[FlashBank1Info], `FLASH1_INFO_MEM_HIER)
@@ -570,7 +570,7 @@ module tb;
570570
.n_bits($bits(`RAM_MAIN_MEM_HIER)),
571571
.err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
572572
.num_prince_rounds_half(2),
573-
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_RAM_MAIN_BASE_ADDR));
573+
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_SRAM_CTRL_MAIN_RAM_BASE_ADDR));
574574
m_mem_bkdr_util[RamMain0] = ram_main0;
575575
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamMain0], `RAM_MAIN_MEM_HIER)
576576

@@ -581,7 +581,7 @@ module tb;
581581
.depth ($size(`RAM_RET_MEM_HIER)),
582582
.n_bits($bits(`RAM_RET_MEM_HIER)),
583583
.err_detection_scheme(mem_bkdr_util_pkg::EccInv_39_32),
584-
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_RAM_RET_AON_BASE_ADDR));
584+
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_SRAM_CTRL_RET_AON_RAM_BASE_ADDR));
585585
m_mem_bkdr_util[RamRet0] = ram_ret0;
586586
`MEM_BKDR_UTIL_FILE_OP(m_mem_bkdr_util[RamRet0], `RAM_RET_MEM_HIER)
587587

@@ -598,7 +598,7 @@ module tb;
598598
`endif
599599
.key (top_earlgrey_rnd_cnst_pkg::RndCnstRomCtrlScrKey),
600600
.nonce (top_earlgrey_rnd_cnst_pkg::RndCnstRomCtrlScrNonce),
601-
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_ROM_BASE_ADDR));
601+
.system_base_addr (top_earlgrey_pkg::TOP_EARLGREY_ROM_CTRL_ROM_BASE_ADDR));
602602
m_mem_bkdr_util[Rom] = rom;
603603

604604
// Knob to skip ROM backdoor logging (for sims that use ROM macro).

0 commit comments

Comments
 (0)