|
| 1 | +/* |
| 2 | + * QEMU lowRISC Ibex IRQ wrapper |
| 3 | + * |
| 4 | + * Copyright (c) 2022-2023 Rivos, Inc. |
| 5 | + * |
| 6 | + * SPDX-License-Identifier: MIT |
| 7 | + * |
| 8 | + */ |
| 9 | + |
| 10 | +#ifndef HW_RISCV_IBEX_IRQ_H |
| 11 | +#define HW_RISCV_IBEX_IRQ_H |
| 12 | + |
| 13 | +#include "qemu/osdep.h" |
| 14 | +#include "qom/object.h" |
| 15 | +#include "hw/irq.h" |
| 16 | +#include "hw/qdev-core.h" |
| 17 | +#include "hw/sysbus.h" |
| 18 | + |
| 19 | + |
| 20 | +/** Simple IRQ wrapper to limit propagation of no-change calls */ |
| 21 | +typedef struct { |
| 22 | + qemu_irq irq; |
| 23 | + int level; |
| 24 | +} IbexIRQ; |
| 25 | + |
| 26 | +static inline bool ibex_irq_set(IbexIRQ *ibex_irq, int level) |
| 27 | +{ |
| 28 | + if (level != ibex_irq->level) { |
| 29 | + ibex_irq->level = level; |
| 30 | + qemu_set_irq(ibex_irq->irq, level); |
| 31 | + return true; |
| 32 | + } |
| 33 | + |
| 34 | + return false; |
| 35 | +} |
| 36 | + |
| 37 | +static inline bool ibex_irq_raise(IbexIRQ *irq) |
| 38 | +{ |
| 39 | + return ibex_irq_set(irq, 1); |
| 40 | +} |
| 41 | + |
| 42 | +static inline bool ibex_irq_lower(IbexIRQ *irq) |
| 43 | +{ |
| 44 | + return ibex_irq_set(irq, 0); |
| 45 | +} |
| 46 | + |
| 47 | +static inline void ibex_qdev_init_irq(Object *obj, IbexIRQ *irq, |
| 48 | + const char *name) |
| 49 | +{ |
| 50 | + irq->level = 0; |
| 51 | + qdev_init_gpio_out_named(DEVICE(obj), &irq->irq, name, 1); |
| 52 | +} |
| 53 | + |
| 54 | +static inline void ibex_qdev_init_irqs(Object *obj, IbexIRQ *irqs, |
| 55 | + const char *name, unsigned count) |
| 56 | +{ |
| 57 | + for (unsigned ix = 0; ix < count; ix++) { |
| 58 | + irqs[ix].level = 0; |
| 59 | + qdev_init_gpio_out_named(DEVICE(obj), &irqs[ix].irq, name, 1); |
| 60 | + } |
| 61 | +} |
| 62 | + |
| 63 | +static inline void ibex_sysbus_init_irq(Object *obj, IbexIRQ *irq) |
| 64 | +{ |
| 65 | + irq->level = 0; |
| 66 | + sysbus_init_irq(SYS_BUS_DEVICE(obj), &irq->irq); |
| 67 | +} |
| 68 | + |
| 69 | +#endif /* HW_RISCV_IBEX_IRQ_H */ |
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