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[ot] hw/opentitan: ot_spi_device: Update the SRAM definition
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‎hw/opentitan/ot_spi_device.c‎

Lines changed: 74 additions & 53 deletions
Original file line numberDiff line numberDiff line change
@@ -43,10 +43,10 @@
4343
#include "hw/riscv/ibex_irq.h"
4444
#include "trace.h"
4545

46-
#define PARAM_SRAM_DEPTH 1024u
47-
#define PARAM_SRAM_OFFSET 4096u
48-
#define PARAM_SRAM_EGRESS_DEPTH 832u
49-
#define PARAM_SRAM_INGRESS_DEPTH 104u
46+
#define PARAM_SRAM_OFFSET 0x1000u
47+
#define PARAM_SRAM_DEPTH (0x1000u / sizeof(uint32_t))
48+
#define PARAM_SRAM_EGRESS_DEPTH (0xe00u / sizeof(uint32_t))
49+
#define PARAM_SRAM_INGRESS_DEPTH (0x200u / sizeof(uint32_t))
5050
#define PARAM_NUM_CMD_INFO 24u
5151
#define PARAM_NUM_LOCALITY 5u
5252
#define PARAM_TPM_WR_FIFO_PTR_W 7u
@@ -233,8 +233,9 @@ REG32(TPM_WRITE_FIFO, 0x38u)
233233
FIELD(TPM_WRITE_FIFO, VALUE, 0u, 8u)
234234
/* clang-format on */
235235

236-
#define SPI_BUS_PROTO_VER 0
237-
#define SPI_BUS_HEADER_SIZE (2u * sizeof(uint32_t))
236+
#define SPI_BUS_PROTO_VER 0
237+
#define SPI_BUS_HEADER_SIZE (2u * sizeof(uint32_t))
238+
#define SPI_TPM_READ_FIFO_SIZE_BYTES (PARAM_TPM_RD_FIFO_WIDTH * sizeof(uint32_t))
238239
/**
239240
* Delay for handling non-aligned generic data transfer and flush the FIFO.
240241
* Generic mode is deprecated anyway. Arbitrarily set to 1 ms.
@@ -253,59 +254,75 @@ REG32(TPM_WRITE_FIFO, 0x38u)
253254

254255
/*
255256
* New scheme (Egress + Ingress) Old Scheme (DPSRAM)
256-
* +-----------------------------+ +-----------------------+
257-
* | Flash / Passthru modes | | Flash / Passthru modes|
258-
* 0x000 -+----------------+------+-----+ -+----------------+------+
259-
* | Read Command 0 | 1KiB | Out | | Read Command 0 | 1KiB |
260-
* 0x400 -+----------------+------+-----+ -+----------------+------+
261-
* | Read Command 1 | 1KiB | Out | | Read Command 1 | 1KiB |
262-
* 0x800 -+----------------+------+-----+ -+----------------+------+
263-
* | Mailbox | 1KiB | Out | | Mailbox | 1KiB |
264-
* 0xc00 -+----------------+------+-----+ -+----------------+------+
265-
* | SFDP | 256B | Out | | SFDP | 256B |
266-
* 0xd00 -+----------------+------+-----+ -+----------------+------+
267-
* | | | Payload FIFO | 256B |
268-
* 0xe00 -+----------------+------+-----+ -+----------------+------+
269-
* | Payload FIFO | 256B | In | | Command FIFO | 64B |
270-
* 0xe40 -+----------------+------+-----+ -+----------------+------+
271-
* | Command FIFO | 64B | In | | Address FIFO | 64B |
272-
* 0xe80 -+----------------+------+-----+ -+----------------+------+
273-
* | Address FIFO | 64B | In |
274-
* 0xe80 -+----------------+------+-----+
275-
*
257+
* +--------------------------------+ +-----------------------+
258+
* | Flash / Passthru modes | | Flash / Passthru modes|
259+
* 0x000 -+-------------------+------+-----+ -+----------------+------+
260+
* | Read Command 0 | 1KiB | Out | | Read Command 0 | 1KiB |
261+
* 0x400 -+-------------------+------+-----+ -+----------------+------+
262+
* | Read Command 1 | 1KiB | Out | | Read Command 1 | 1KiB |
263+
* 0x800 -+-------------------+------+-----+ -+----------------+------+
264+
* | Mailbox | 1KiB | Out | | Mailbox | 1KiB |
265+
* 0xc00 -+-------------------+------+-----+ -+----------------+------+
266+
* | SFDP | 256B | Out | | SFDP | 256B |
267+
* 0xd00 -+-------------------+------+-----+ -+----------------+------+
268+
* | TPM Read Buffer + 64B + Out | | Payload FIFO | 256B |
269+
* 0xd40 -+-------------------+------+-----+ -+----------------+------+
270+
* | | | | | Command FIFO | 64B |
271+
* 0xe00 -+-------------------+------+-----+ -+----------------+------+
272+
* | Payload FIFO | 256B | In | | Address FIFO | 64B |
273+
* 0xf00 -+-------------------+------+-----+ -+----------------+------+
274+
* | Command FIFO | 64B | In |
275+
* 0xf40 -+-------------------+------+-----+
276+
* | Address FIFO | 64B | In |
277+
* 0xf80 -+-------------------+------+-----+
278+
* | TPM Write buffer | 64B | In |
279+
* 0xfc0 -+-------------------+------+-----+
276280
*
277281
*/
278282
#define SPI_SRAM_READ0_OFFSET 0x0
279283
#define SPI_SRAM_READ_SIZE 0x400u
284+
280285
#define SPI_SRAM_READ1_OFFSET (SPI_SRAM_READ0_OFFSET + SPI_SRAM_READ_SIZE)
281286
#define SPI_SRAM_READ1_SIZE 0x400u
282-
#define SPI_SRAM_MBX_OFFSET (SPI_SRAM_READ1_OFFSET + SPI_SRAM_READ_SIZE)
283-
#define SPI_SRAM_MBX_SIZE 0x400u
284-
#define SPI_SRAM_SFDP_OFFSET (SPI_SRAM_MBX_OFFSET + SPI_SRAM_MBX_SIZE)
285-
#define SPI_SRAM_SFDP_SIZE 0x100u
287+
288+
#define SPI_SRAM_MBX_OFFSET (SPI_SRAM_READ1_OFFSET + SPI_SRAM_READ_SIZE)
289+
#define SPI_SRAM_MBX_SIZE 0x400u
290+
291+
#define SPI_SRAM_SFDP_OFFSET (SPI_SRAM_MBX_OFFSET + SPI_SRAM_MBX_SIZE)
292+
#define SPI_SRAM_SFDP_SIZE 0x100u
293+
294+
#define SPI_SRAM_TPM_READ_OFFSET (SPI_SRAM_SFDP_OFFSET + SPI_SRAM_SFDP_SIZE)
295+
#define SPI_SRAM_TPM_READ_SIZE 0x40u
286296
/* with new scheme (no dual part SRAM, the following offsets are shifted...) */
287-
#define SPI_SRAM_INGRESS_OFFSET 0x100u
288-
#define SPI_SRAM_PAYLOAD_OFFSET (SPI_SRAM_SFDP_OFFSET + SPI_SRAM_SFDP_SIZE)
297+
#define SPI_SRAM_INGRESS_OFFSET 0xE00u
298+
299+
#define SPI_SRAM_PAYLOAD_OFFSET SPI_SRAM_INGRESS_OFFSET
289300
#define SPI_SRAM_PAYLOAD_SIZE 0x100u
290-
#define SPI_SRAM_CMD_OFFSET (SPI_SRAM_PAYLOAD_OFFSET + SPI_SRAM_PAYLOAD_SIZE)
291-
#define SPI_SRAM_CMD_SIZE 0x40u
292-
#define SPI_SRAM_ADDR_OFFSET (SPI_SRAM_CMD_OFFSET + SPI_SRAM_CMD_SIZE)
293-
#define SPI_SRAM_ADDR_SIZE 0x40u
294-
#define SPI_SRAM_ADDR_END (SPI_SRAM_ADDR_OFFSET + SPI_SRAM_ADDR_SIZE)
295-
#define SPI_SRAM_END_OFFSET (SPI_SRAM_ADDR_END)
296-
static_assert(SPI_SRAM_END_OFFSET == 0xe80u, "Invalid SRAM definition");
301+
302+
#define SPI_SRAM_CMD_OFFSET (SPI_SRAM_PAYLOAD_OFFSET + SPI_SRAM_PAYLOAD_SIZE)
303+
#define SPI_SRAM_CMD_SIZE 0x40u
304+
305+
#define SPI_SRAM_ADDR_OFFSET (SPI_SRAM_CMD_OFFSET + SPI_SRAM_CMD_SIZE)
306+
#define SPI_SRAM_ADDR_SIZE 0x40u
307+
308+
#define SPI_SRAM_TPM_WRITE_OFFSET (SPI_SRAM_ADDR_OFFSET + SPI_SRAM_ADDR_SIZE)
309+
#define SPI_SRAM_TPM_WRITE_SIZE 0x40u
310+
311+
#define SPI_SRAM_ADDR_END (SPI_SRAM_TPM_WRITE_OFFSET + SPI_SRAM_TPM_WRITE_SIZE)
312+
#define SPI_SRAM_END_OFFSET (SPI_SRAM_ADDR_END)
313+
static_assert(SPI_SRAM_END_OFFSET == 0xfc0u, "Invalid SRAM definition");
297314

298315
#define SPI_DEVICE_SIZE 0x2000u
299316
#define SPI_DEVICE_SPI_REGS_OFFSET 0u
300317
#define SPI_DEVICE_TPM_REGS_OFFSET 0x800u
301-
#define SPI_DEVICE_SRAM_OFFSET 0x1000u
318+
#define SPI_DEVICE_SRAM_OFFSET PARAM_SRAM_OFFSET
302319

303-
#define SRAM_SIZE PARAM_SRAM_OFFSET
320+
#define SRAM_SIZE 0x1000
304321
#define EGRESS_BUFFER_SIZE_BYTES \
305-
(SPI_SRAM_PAYLOAD_OFFSET - SPI_SRAM_READ0_OFFSET)
322+
(SPI_SRAM_INGRESS_OFFSET - SPI_SRAM_READ0_OFFSET)
306323
#define EGRESS_BUFFER_SIZE_WORDS (EGRESS_BUFFER_SIZE_BYTES / sizeof(uint32_t))
307324
#define INGRESS_BUFFER_SIZE_BYTES \
308-
(SPI_SRAM_END_OFFSET - SPI_SRAM_PAYLOAD_OFFSET)
325+
(SPI_SRAM_END_OFFSET - SPI_SRAM_INGRESS_OFFSET)
309326
#define INGRESS_BUFFER_SIZE_WORDS (INGRESS_BUFFER_SIZE_BYTES / sizeof(uint32_t))
310327

311328
#define FLASH_READ_BUFFER_SIZE (2u * SPI_SRAM_READ_SIZE)
@@ -1814,26 +1831,30 @@ static MemTxResult ot_spi_device_buf_read_with_attrs(
18141831
(void)attrs;
18151832
uint32_t val32;
18161833

1817-
hwaddr last = addr + size - 1u;
1834+
hwaddr last = (hwaddr)((uint32_t)addr + size - 1u);
18181835

1819-
if (last < SPI_SRAM_PAYLOAD_OFFSET + SPI_SRAM_INGRESS_OFFSET) {
1836+
if (addr < SPI_SRAM_INGRESS_OFFSET) {
18201837
qemu_log_mask(LOG_GUEST_ERROR,
18211838
"%s: cannot read egress buffer 0x%" HWADDR_PRIx "\n",
18221839
__func__, addr);
18231840
return MEMTX_DECODE_ERROR;
18241841
}
1825-
if (last < SPI_SRAM_CMD_OFFSET + SPI_SRAM_INGRESS_OFFSET) {
1826-
/* payload buffer */
1842+
1843+
if ((addr >= SPI_SRAM_PAYLOAD_OFFSET &&
1844+
last < (SPI_SRAM_PAYLOAD_OFFSET + SPI_SRAM_PAYLOAD_SIZE)) ||
1845+
(addr >= SPI_SRAM_TPM_WRITE_OFFSET &&
1846+
last < (SPI_SRAM_TPM_WRITE_OFFSET + SPI_SRAM_TPM_WRITE_SIZE))) {
18271847
val32 = s->sram[addr >> 2u];
1828-
} else if (last < SPI_SRAM_ADDR_OFFSET + SPI_SRAM_INGRESS_OFFSET) {
1848+
} else if (addr >= SPI_SRAM_CMD_OFFSET &&
1849+
last < (SPI_SRAM_CMD_OFFSET + SPI_SRAM_CMD_SIZE)) {
18291850
/* command FIFO */
18301851
val32 = ((const uint32_t *)s->flash.cmd_fifo.data)[addr >> 2u];
1831-
} else if (last < SPI_SRAM_ADDR_END + SPI_SRAM_INGRESS_OFFSET) {
1852+
} else if (addr >= SPI_SRAM_ADDR_OFFSET &&
1853+
last < (SPI_SRAM_ADDR_OFFSET + SPI_SRAM_ADDR_SIZE)) {
18321854
/* address FIFO */
18331855
val32 = s->flash.address_fifo.data[addr >> 2u];
18341856
} else {
1835-
/* TPM or not used area */
1836-
qemu_log_mask(LOG_UNIMP, "%s: TPM not supported 0x%" HWADDR_PRIx "\n",
1857+
qemu_log_mask(LOG_UNIMP, "%s: Area out of bounds 0x%" HWADDR_PRIx "\n",
18371858
__func__, addr);
18381859
val32 = 0;
18391860
}
@@ -1862,9 +1883,9 @@ static MemTxResult ot_spi_device_buf_write_with_attrs(
18621883
uint32_t pc = ibex_get_current_pc();
18631884
trace_ot_spi_device_buf_write_in(s->ot_id, (uint32_t)addr, size, val32, pc);
18641885

1865-
hwaddr last = addr + size - 1u;
1886+
hwaddr last = (hwaddr)((uint32_t)addr + size - 1u);
18661887

1867-
if (last >= SPI_SRAM_PAYLOAD_OFFSET) {
1888+
if (last >= SPI_SRAM_INGRESS_OFFSET) {
18681889
qemu_log_mask(LOG_GUEST_ERROR,
18691890
"%s: cannot write ingress buffer 0x%" HWADDR_PRIx "\n",
18701891
__func__, addr);

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