Enable CHERIoT Ibex ICache

Author: GregAC

rtl/system/sonata_system.sv

@@ -1174,7 +1174,8 @@ module sonata_system #(
     .HeapBase        ( tl_main_pkg::ADDR_SPACE_SRAM            ),
     .TSMapBase       ( tl_main_pkg::ADDR_SPACE_REV_TAG         ),
     .TSMapSize       ( RevTagDepth                             ),
-    .RV32B           ( ibex_pkg::RV32BFull                     )
+    .RV32B           ( ibex_pkg::RV32BFull                     ),
+    .ICache          ( 1'b1                                    )
   ) u_top_tracing (
     .clk_i                  (clk_sys_i),
     .rst_ni                 (rst_core_n),

sw/cheri/boot/boot.S

@@ -7,6 +7,8 @@
 	.p2align 2
     .type start,@function
 start:
+	// Enable the ICache
+	csrsi            0x7c0, 1
 	// Upon reset mtdc contains the read-write root and pcc contains the execution root.
 	cspecialr        cs0, mtdc
 	auipcc           cs1, 0
@@ -32,6 +34,9 @@ start:
 	cmove            ca0, cs0
 	ccall            rom_loader_entry
 
+	// Flush ICache now we've loaded new code
+	fence.i
+
 	// Jump to the newly loaded binary.
 	csetaddr         ct0, cs1, a0
 	cjr              ct0

sw/cheri/common/boot.S

@@ -7,6 +7,8 @@
 	.p2align 2
     .type start,@function
 start:
+	// Enable the ICache
+	csrsi            0x7c0, 1
 	// ca0 (first argument) contains the read-write root
 	cspecialr        ca0, mtdc
 

sw/cheri/sim_boot_stub/boot.S

@@ -5,6 +5,8 @@
 	.p2align 2
     .type start,@function
 start:
+  // Enable the ICache
+  csrsi            0x7c0, 1
   auipcc           ct1, 0
   li               t0, 0x40000000
   csetaddr         ct1, ct1, t0

sw/cheri/tests/hyperram_tests.hh

@@ -217,6 +217,8 @@ void write_prog(Capability<volatile uint32_t> hyperram_area, uint32_t addr) {
   hyperram_area[addr + 2] = 0x00552023;
   hyperram_area[addr + 3] = 0x00000517;
   hyperram_area[addr + 4] = 0x8082;
+
+  asm volatile ("fence.i" : : : "memory");
 }
 
 /*