Skip to content

Commit 0d201f4

Browse files
mariusmmmariusmm
committed
Fixed Debug module for RV32 & RV64
1 parent 6e9f3eb commit 0d201f4

File tree

6 files changed

+135
-55
lines changed

6 files changed

+135
-55
lines changed

‎inc/CPU.h

Lines changed: 9 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,9 @@
2626

2727
namespace riscv_tlm {
2828

29+
typedef enum {RV32, RV64} cpu_types_t;
30+
31+
2932
class CPU : sc_core::sc_module {
3033
public:
3134

@@ -111,7 +114,7 @@ namespace riscv_tlm {
111114
* @brief RISC_V CPU 32 bits model
112115
* @param name name of the module
113116
*/
114-
class RV32 : public CPU {
117+
class CPURV32 : public CPU {
115118
public:
116119
using BaseType = std::uint32_t;
117120

@@ -121,12 +124,12 @@ namespace riscv_tlm {
121124
* @param PC Program Counter initialize value
122125
* @param debug To start debugging
123126
*/
124-
RV32(sc_core::sc_module_name const &name, BaseType PC, bool debug);
127+
CPURV32(sc_core::sc_module_name const &name, BaseType PC, bool debug);
125128

126129
/**
127130
* @brief Destructor
128131
*/
129-
~RV32() override;
132+
~CPURV32() override;
130133

131134
bool CPU_step() override;
132135
Registers<BaseType> *getRegisterBank() { return register_bank; }
@@ -165,7 +168,7 @@ namespace riscv_tlm {
165168
* @brief RISC_V CPU 64 bits model
166169
* @param name name of the module
167170
*/
168-
class RV64 : public CPU {
171+
class CPURV64 : public CPU {
169172
public:
170173
using BaseType = std::uint64_t;
171174

@@ -175,12 +178,12 @@ namespace riscv_tlm {
175178
* @param PC Program Counter initialize value
176179
* @param debug To start debugging
177180
*/
178-
RV64(sc_core::sc_module_name const &name, BaseType PC, bool debug);
181+
CPURV64(sc_core::sc_module_name const &name, BaseType PC, bool debug);
179182

180183
/**
181184
* @brief Destructor
182185
*/
183-
~RV64() override;
186+
~CPURV64() override;
184187

185188
bool CPU_step() override;
186189
Registers<BaseType> *getRegisterBank() { return register_bank; }

‎inc/Debug.h

Lines changed: 7 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -25,7 +25,8 @@ namespace riscv_tlm {
2525
class Debug : sc_core::sc_module {
2626
public:
2727

28-
Debug(riscv_tlm::RV32 *cpu, Memory *mem);
28+
Debug(riscv_tlm::CPURV32 *cpu, Memory *mem);
29+
Debug(riscv_tlm::CPURV64 *cpu, Memory *mem);
2930

3031
~Debug() override;
3132

@@ -41,11 +42,15 @@ namespace riscv_tlm {
4142
static constexpr size_t bufsize = 1024 * 8;
4243
char iobuf[bufsize]{};
4344
int conn;
44-
riscv_tlm::RV32 *dbg_cpu;
45+
riscv_tlm::CPURV32 *dbg_cpu32;
46+
riscv_tlm::CPURV64 *dbg_cpu64;
47+
Registers<std::uint32_t> *register_bank32;
48+
Registers<std::uint64_t> *register_bank64;
4549
Memory *dbg_mem;
4650
tlm::tlm_generic_payload dbg_trans;
4751
unsigned char pyld_array[128]{};
4852
std::unordered_set<uint32_t> breakpoints;
53+
riscv_tlm::cpu_types_t cpu_type;
4954
};
5055
}
5156

‎src/Debug.cpp

Lines changed: 84 additions & 15 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,35 @@ namespace riscv_tlm {
2323
constexpr char nibble_to_hex[16] = {'0', '1', '2', '3', '4', '5', '6', '7',
2424
'8', '9', 'a', 'b', 'c', 'd', 'e', 'f'};
2525

26-
Debug::Debug(riscv_tlm::RV32 *cpu, Memory *mem) : sc_module(sc_core::sc_module_name("Debug")) {
27-
dbg_cpu = cpu;
26+
Debug::Debug(riscv_tlm::CPURV32 *cpu, Memory *mem) : sc_module(sc_core::sc_module_name("Debug")) {
27+
dbg_cpu32 = cpu;
2828
dbg_mem = mem;
29+
cpu_type = riscv_tlm::RV32;
30+
31+
int sock = socket(AF_INET, SOCK_STREAM, 0);
32+
33+
int optval = 1;
34+
setsockopt(sock, SOL_SOCKET, SO_REUSEADDR, &optval,
35+
sizeof(optval));
36+
37+
sockaddr_in addr;
38+
addr.sin_family = AF_INET;
39+
addr.sin_addr.s_addr = INADDR_ANY;
40+
addr.sin_port = htons(1234);
41+
42+
bind(sock, (struct sockaddr *) &addr, sizeof(addr));
43+
listen(sock, 1);
44+
45+
socklen_t len = sizeof(addr);
46+
conn = accept(sock, (struct sockaddr *) &addr, &len);
47+
48+
handle_gdb_loop();
49+
}
50+
51+
Debug::Debug(riscv_tlm::CPURV64 *cpu, Memory *mem) : sc_module(sc_core::sc_module_name("Debug")) {
52+
dbg_cpu64 = cpu;
53+
dbg_mem = mem;
54+
cpu_type = riscv_tlm::RV64;
2955

3056
int sock = socket(AF_INET, SOCK_STREAM, 0);
3157

@@ -77,7 +103,11 @@ namespace riscv_tlm {
77103
void Debug::handle_gdb_loop() {
78104
std::cout << "Handle_GDB_Loop\n";
79105

80-
Registers<std::uint32_t> *register_bank = dbg_cpu->getRegisterBank();
106+
if (dbg_cpu32 != nullptr) {
107+
register_bank32 = dbg_cpu32->getRegisterBank();
108+
} else {
109+
register_bank64 = dbg_cpu64->getRegisterBank();
110+
}
81111

82112
while (true) {
83113
std::string msg = receive_packet();
@@ -115,30 +145,52 @@ namespace riscv_tlm {
115145
std::stringstream stream;
116146
stream << std::setfill('0') << std::hex;
117147
for (int i = 1; i < 32; i++) {
118-
stream << std::setw(8) << register_bank->getValue(i);
148+
if (cpu_type == riscv_tlm::RV32) {
149+
stream << std::setw(8) << register_bank32->getValue(i);
150+
}
119151
}
120152
send_packet(conn, stream.str());
121153
} else if (boost::starts_with(msg, "p")) {
122154
long n = strtol(msg.c_str() + 1, 0, 16);
123-
std::uint64_t reg_value;
155+
std::uint64_t reg_value = 0;
124156
if (n < 32) {
125-
reg_value = register_bank->getValue(n);
157+
if (cpu_type == riscv_tlm::RV32) {
158+
reg_value = register_bank32->getValue(n);
159+
} else {
160+
reg_value = register_bank64->getValue(n);
161+
}
126162
} else if (n == 32) {
127-
reg_value = register_bank->getPC();
163+
if (cpu_type == riscv_tlm::RV32) {
164+
reg_value = register_bank32->getPC();
165+
} else {
166+
reg_value = register_bank64->getPC();
167+
}
128168
} else {
129169
// see: https://github.com/riscv/riscv-gnu-toolchain/issues/217
130170
// risc-v register 834
131-
reg_value = register_bank->getCSR(n - 65);
171+
if (cpu_type == riscv_tlm::RV32) {
172+
reg_value = register_bank32->getCSR(n - 65);
173+
} else {
174+
reg_value = register_bank64->getCSR(n - 65);
175+
}
132176
}
133177
std::stringstream stream;
134178
stream << std::setfill('0') << std::hex;
135-
stream << std::setw(8) << htonl(reg_value);
179+
if (cpu_type == riscv_tlm::RV32) {
180+
stream << std::setw(8) << htonl(reg_value);
181+
} else {
182+
stream << std::setw(16) << htonl(reg_value);
183+
}
136184
send_packet(conn, stream.str());
137185
} else if (boost::starts_with(msg, "P")) {
138186
char *pEnd;
139187
long reg = strtol(msg.c_str() + 1, &pEnd, 16);
140188
int val = strtol(pEnd + 1, 0, 16);
141-
register_bank->setValue(reg + 1, val);
189+
if (cpu_type == riscv_tlm::RV32) {
190+
register_bank32->setValue(reg + 1, val);
191+
} else {
192+
register_bank64->setValue(reg + 1, val);
193+
}
142194
send_packet(conn, "OK");
143195
} else if (boost::starts_with(msg, "m")) {
144196
char *pEnd;
@@ -174,23 +226,40 @@ namespace riscv_tlm {
174226
bool breakpoint_hit = false;
175227
bool bkpt = false;
176228
do {
177-
bkpt = dbg_cpu->CPU_step();
178-
uint32_t currentPC = register_bank->getPC();
229+
std::uint64_t currentPC;
230+
//bkpt = dbg_cpu->CPU_step();
231+
if (cpu_type == riscv_tlm::RV32) {
232+
bkpt = dbg_cpu32->CPU_step();
233+
currentPC = register_bank32->getPC();
234+
} else {
235+
bkpt = dbg_cpu64->CPU_step();
236+
currentPC = register_bank64->getPC();
237+
}
179238

180239
auto search = breakpoints.find(currentPC);
181240
if (search != breakpoints.end()) {
182241
breakpoint_hit = true;
183242
}
184243
} while ((breakpoint_hit == false) && (bkpt == false));
185244

186-
std::cout << "Breakpoint hit at 0x" << std::hex << register_bank->getPC() << std::endl;
245+
// std::cout << "Breakpoint hit at 0x" << std::hex << register_bank->getPC() << std::endl;
187246
send_packet(conn, "S05");
188247
} else if (msg == "s") {
189248

190249
bool breakpoint;
191-
dbg_cpu->CPU_step();
250+
if (cpu_type == riscv_tlm::RV32) {
251+
dbg_cpu32->CPU_step();
252+
} else {
253+
dbg_cpu64->CPU_step();
254+
}
255+
256+
std::uint64_t currentPC;
257+
if (cpu_type == riscv_tlm::RV32) {
258+
currentPC = register_bank32->getPC();
259+
} else {
260+
currentPC = register_bank64->getPC();
261+
}
192262

193-
uint32_t currentPC = register_bank->getPC();
194263
auto search = breakpoints.find(currentPC);
195264
if (search != breakpoints.end()) {
196265
breakpoint = true;

‎src/RV32.cpp

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -9,9 +9,9 @@
99

1010
namespace riscv_tlm {
1111

12-
SC_HAS_PROCESS(RV32);
12+
SC_HAS_PROCESS(CPURV32);
1313

14-
RV32::RV32(sc_core::sc_module_name const &name, BaseType PC, bool debug) :
14+
CPURV32::CPURV32(sc_core::sc_module_name const &name, BaseType PC, bool debug) :
1515
CPU(name, debug), INSTR(0) {
1616

1717
register_bank = new Registers<BaseType>();
@@ -22,7 +22,7 @@ namespace riscv_tlm {
2222
int_cause = 0;
2323

2424
instr_bus.register_invalidate_direct_mem_ptr(this,
25-
&RV32::invalidate_direct_mem_ptr);
25+
&CPURV32::invalidate_direct_mem_ptr);
2626

2727
exec = new BASE_ISA<BaseType>(0, register_bank, mem_intf);
2828
c_inst = new C_extension<BaseType>(0, register_bank, mem_intf);
@@ -31,11 +31,11 @@ namespace riscv_tlm {
3131

3232
trans.set_data_ptr(reinterpret_cast<unsigned char *>(&INSTR));
3333

34-
logger->info("Created RV32 CPU");
35-
std::cout << "Created RV32 CPU" << std::endl;
34+
logger->info("Created CPURV32 CPU");
35+
std::cout << "Created CPURV32 CPU" << std::endl;
3636
}
3737

38-
RV32::~RV32() {
38+
CPURV32::~CPURV32() {
3939
delete register_bank;
4040
delete mem_intf;
4141
delete exec;
@@ -45,7 +45,7 @@ namespace riscv_tlm {
4545
delete m_qk;
4646
}
4747

48-
bool RV32::cpu_process_IRQ() {
48+
bool CPURV32::cpu_process_IRQ() {
4949
BaseType csr_temp;
5050
bool ret_value = false;
5151

@@ -102,7 +102,7 @@ namespace riscv_tlm {
102102
return ret_value;
103103
}
104104

105-
bool RV32::CPU_step() {
105+
bool CPURV32::CPU_step() {
106106
bool PC_not_affected = false;
107107

108108
/* Get new PC value */
@@ -175,19 +175,19 @@ namespace riscv_tlm {
175175

176176

177177

178-
void RV32::call_interrupt(tlm::tlm_generic_payload &m_trans,
178+
void CPURV32::call_interrupt(tlm::tlm_generic_payload &m_trans,
179179
sc_core::sc_time &delay) {
180180
interrupt = true;
181181
/* Socket caller send a cause (its id) */
182182
memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(BaseType));
183183
delay = sc_core::SC_ZERO_TIME;
184184
}
185185

186-
std::uint64_t RV32::getStartDumpAddress() {
186+
std::uint64_t CPURV32::getStartDumpAddress() {
187187
return register_bank->getValue(Registers<std::uint32_t>::t0);
188188
}
189189

190-
std::uint64_t RV32::getEndDumpAddress() {
190+
std::uint64_t CPURV32::getEndDumpAddress() {
191191
return register_bank->getValue(Registers<std::uint32_t>::t1);
192192
}
193193
}

‎src/RV64.cpp

Lines changed: 10 additions & 10 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99

1010
namespace riscv_tlm {
1111

12-
RV64::RV64(sc_core::sc_module_name const &name, BaseType PC, bool debug) :
12+
CPURV64::CPURV64(sc_core::sc_module_name const &name, BaseType PC, bool debug) :
1313
CPU(name, debug), INSTR(0) {
1414

1515
register_bank = new Registers<BaseType>();
@@ -20,7 +20,7 @@ namespace riscv_tlm {
2020
int_cause = 0;
2121

2222
instr_bus.register_invalidate_direct_mem_ptr(this,
23-
&RV64::invalidate_direct_mem_ptr);
23+
&CPURV64::invalidate_direct_mem_ptr);
2424

2525
exec = new BASE_ISA<BaseType>(0, register_bank, mem_intf);
2626
c_inst = new C_extension<BaseType>(0, register_bank, mem_intf);
@@ -29,11 +29,11 @@ namespace riscv_tlm {
2929

3030
trans.set_data_ptr(reinterpret_cast<unsigned char *>(&INSTR));
3131

32-
logger->info("Created RV64 CPU");
33-
std::cout << "Created RV64 CPU" << std::endl;
32+
logger->info("Created CPURV64 CPU");
33+
std::cout << "Created CPURV64 CPU" << std::endl;
3434
}
3535

36-
RV64::~RV64() {
36+
CPURV64::~CPURV64() {
3737
delete register_bank;
3838
delete mem_intf;
3939
delete exec;
@@ -43,7 +43,7 @@ namespace riscv_tlm {
4343
delete m_qk;
4444
}
4545

46-
bool RV64::cpu_process_IRQ() {
46+
bool CPURV64::cpu_process_IRQ() {
4747
BaseType csr_temp;
4848
bool ret_value = false;
4949

@@ -100,7 +100,7 @@ namespace riscv_tlm {
100100
return ret_value;
101101
}
102102

103-
bool RV64::CPU_step() {
103+
bool CPURV64::CPU_step() {
104104
bool PC_not_affected = false;
105105

106106
/* Get new PC value */
@@ -171,19 +171,19 @@ namespace riscv_tlm {
171171
return breakpoint;
172172
}
173173

174-
void RV64::call_interrupt(tlm::tlm_generic_payload &m_trans,
174+
void CPURV64::call_interrupt(tlm::tlm_generic_payload &m_trans,
175175
sc_core::sc_time &delay) {
176176
interrupt = true;
177177
/* Socket caller send a cause (its id) */
178178
memcpy(&int_cause, m_trans.get_data_ptr(), sizeof(BaseType));
179179
delay = sc_core::SC_ZERO_TIME;
180180
}
181181

182-
std::uint64_t RV64::getStartDumpAddress() {
182+
std::uint64_t CPURV64::getStartDumpAddress() {
183183
return register_bank->getValue(Registers<std::uint32_t>::t0);
184184
}
185185

186-
std::uint64_t RV64::getEndDumpAddress() {
186+
std::uint64_t CPURV64::getEndDumpAddress() {
187187
return register_bank->getValue(Registers<std::uint32_t>::t1);
188188
}
189189
}

0 commit comments

Comments
 (0)