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Marc Zyngierpm215
Marc Zyngier
authored and
pm215
committedNov 26, 2019
target/arm: Honor HCR_EL2.TID3 trapping requirements
HCR_EL2.TID3 mandates that access from EL1 to a long list of id registers traps to EL2, and QEMU has so far ignored this requirement. This breaks (among other things) KVM guests that have PtrAuth enabled, while the hypervisor doesn't want to expose the feature to its guest. To achieve this, KVM traps the ID registers (ID_AA64ISAR1_EL1 in this case), and masks out the unsupported feature. QEMU not honoring the trap request means that the guest observes that the feature is present in the HW, starts using it, and dies a horrible death when KVM injects an UNDEF, because the feature *really* isn't supported. Do the right thing by trapping to EL2 if HCR_EL2.TID3 is set. Note that this change does not include trapping of the MVFR registers from AArch32 (they are accessed via the VMRS instruction and need to be handled in a different way). Reported-by: Will Deacon <will@kernel.org> Signed-off-by: Marc Zyngier <maz@kernel.org> Tested-by: Will Deacon <will@kernel.org> Message-id: 20191123115618.29230-1-maz@kernel.org [PMM: added missing accessfn line for ID_AA4PFR2_EL1_RESERVED; changed names of access functions to include _tid3] Reviewed-by: Peter Maydell <peter.maydell@linaro.org> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
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v4.2.0-rc3
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‎target/arm/helper.c

+76
Original file line numberDiff line numberDiff line change
@@ -5978,6 +5978,26 @@ static const ARMCPRegInfo predinv_reginfo[] = {
59785978
REGINFO_SENTINEL
59795979
};
59805980

5981+
static CPAccessResult access_aa64_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
5982+
bool isread)
5983+
{
5984+
if ((arm_current_el(env) < 2) && (arm_hcr_el2_eff(env) & HCR_TID3)) {
5985+
return CP_ACCESS_TRAP_EL2;
5986+
}
5987+
5988+
return CP_ACCESS_OK;
5989+
}
5990+
5991+
static CPAccessResult access_aa32_tid3(CPUARMState *env, const ARMCPRegInfo *ri,
5992+
bool isread)
5993+
{
5994+
if (arm_feature(env, ARM_FEATURE_V8)) {
5995+
return access_aa64_tid3(env, ri, isread);
5996+
}
5997+
5998+
return CP_ACCESS_OK;
5999+
}
6000+
59816001
void register_cp_regs_for_features(ARMCPU *cpu)
59826002
{
59836003
/* Register all the coprocessor registers based on feature bits */
@@ -6001,70 +6021,86 @@ void register_cp_regs_for_features(ARMCPU *cpu)
60016021
{ .name = "ID_PFR0", .state = ARM_CP_STATE_BOTH,
60026022
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 0,
60036023
.access = PL1_R, .type = ARM_CP_CONST,
6024+
.accessfn = access_aa32_tid3,
60046025
.resetvalue = cpu->id_pfr0 },
60056026
/* ID_PFR1 is not a plain ARM_CP_CONST because we don't know
60066027
* the value of the GIC field until after we define these regs.
60076028
*/
60086029
{ .name = "ID_PFR1", .state = ARM_CP_STATE_BOTH,
60096030
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 1,
60106031
.access = PL1_R, .type = ARM_CP_NO_RAW,
6032+
.accessfn = access_aa32_tid3,
60116033
.readfn = id_pfr1_read,
60126034
.writefn = arm_cp_write_ignore },
60136035
{ .name = "ID_DFR0", .state = ARM_CP_STATE_BOTH,
60146036
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 2,
60156037
.access = PL1_R, .type = ARM_CP_CONST,
6038+
.accessfn = access_aa32_tid3,
60166039
.resetvalue = cpu->id_dfr0 },
60176040
{ .name = "ID_AFR0", .state = ARM_CP_STATE_BOTH,
60186041
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 3,
60196042
.access = PL1_R, .type = ARM_CP_CONST,
6043+
.accessfn = access_aa32_tid3,
60206044
.resetvalue = cpu->id_afr0 },
60216045
{ .name = "ID_MMFR0", .state = ARM_CP_STATE_BOTH,
60226046
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 4,
60236047
.access = PL1_R, .type = ARM_CP_CONST,
6048+
.accessfn = access_aa32_tid3,
60246049
.resetvalue = cpu->id_mmfr0 },
60256050
{ .name = "ID_MMFR1", .state = ARM_CP_STATE_BOTH,
60266051
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 5,
60276052
.access = PL1_R, .type = ARM_CP_CONST,
6053+
.accessfn = access_aa32_tid3,
60286054
.resetvalue = cpu->id_mmfr1 },
60296055
{ .name = "ID_MMFR2", .state = ARM_CP_STATE_BOTH,
60306056
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 6,
60316057
.access = PL1_R, .type = ARM_CP_CONST,
6058+
.accessfn = access_aa32_tid3,
60326059
.resetvalue = cpu->id_mmfr2 },
60336060
{ .name = "ID_MMFR3", .state = ARM_CP_STATE_BOTH,
60346061
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 1, .opc2 = 7,
60356062
.access = PL1_R, .type = ARM_CP_CONST,
6063+
.accessfn = access_aa32_tid3,
60366064
.resetvalue = cpu->id_mmfr3 },
60376065
{ .name = "ID_ISAR0", .state = ARM_CP_STATE_BOTH,
60386066
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 0,
60396067
.access = PL1_R, .type = ARM_CP_CONST,
6068+
.accessfn = access_aa32_tid3,
60406069
.resetvalue = cpu->isar.id_isar0 },
60416070
{ .name = "ID_ISAR1", .state = ARM_CP_STATE_BOTH,
60426071
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 1,
60436072
.access = PL1_R, .type = ARM_CP_CONST,
6073+
.accessfn = access_aa32_tid3,
60446074
.resetvalue = cpu->isar.id_isar1 },
60456075
{ .name = "ID_ISAR2", .state = ARM_CP_STATE_BOTH,
60466076
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 2,
60476077
.access = PL1_R, .type = ARM_CP_CONST,
6078+
.accessfn = access_aa32_tid3,
60486079
.resetvalue = cpu->isar.id_isar2 },
60496080
{ .name = "ID_ISAR3", .state = ARM_CP_STATE_BOTH,
60506081
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 3,
60516082
.access = PL1_R, .type = ARM_CP_CONST,
6083+
.accessfn = access_aa32_tid3,
60526084
.resetvalue = cpu->isar.id_isar3 },
60536085
{ .name = "ID_ISAR4", .state = ARM_CP_STATE_BOTH,
60546086
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 4,
60556087
.access = PL1_R, .type = ARM_CP_CONST,
6088+
.accessfn = access_aa32_tid3,
60566089
.resetvalue = cpu->isar.id_isar4 },
60576090
{ .name = "ID_ISAR5", .state = ARM_CP_STATE_BOTH,
60586091
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 5,
60596092
.access = PL1_R, .type = ARM_CP_CONST,
6093+
.accessfn = access_aa32_tid3,
60606094
.resetvalue = cpu->isar.id_isar5 },
60616095
{ .name = "ID_MMFR4", .state = ARM_CP_STATE_BOTH,
60626096
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 6,
60636097
.access = PL1_R, .type = ARM_CP_CONST,
6098+
.accessfn = access_aa32_tid3,
60646099
.resetvalue = cpu->id_mmfr4 },
60656100
{ .name = "ID_ISAR6", .state = ARM_CP_STATE_BOTH,
60666101
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 2, .opc2 = 7,
60676102
.access = PL1_R, .type = ARM_CP_CONST,
6103+
.accessfn = access_aa32_tid3,
60686104
.resetvalue = cpu->isar.id_isar6 },
60696105
REGINFO_SENTINEL
60706106
};
@@ -6185,164 +6221,204 @@ void register_cp_regs_for_features(ARMCPU *cpu)
61856221
{ .name = "ID_AA64PFR0_EL1", .state = ARM_CP_STATE_AA64,
61866222
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 0,
61876223
.access = PL1_R, .type = ARM_CP_NO_RAW,
6224+
.accessfn = access_aa64_tid3,
61886225
.readfn = id_aa64pfr0_read,
61896226
.writefn = arm_cp_write_ignore },
61906227
{ .name = "ID_AA64PFR1_EL1", .state = ARM_CP_STATE_AA64,
61916228
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 1,
61926229
.access = PL1_R, .type = ARM_CP_CONST,
6230+
.accessfn = access_aa64_tid3,
61936231
.resetvalue = cpu->isar.id_aa64pfr1},
61946232
{ .name = "ID_AA64PFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
61956233
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 2,
61966234
.access = PL1_R, .type = ARM_CP_CONST,
6235+
.accessfn = access_aa64_tid3,
61976236
.resetvalue = 0 },
61986237
{ .name = "ID_AA64PFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
61996238
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 3,
62006239
.access = PL1_R, .type = ARM_CP_CONST,
6240+
.accessfn = access_aa64_tid3,
62016241
.resetvalue = 0 },
62026242
{ .name = "ID_AA64ZFR0_EL1", .state = ARM_CP_STATE_AA64,
62036243
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 4,
62046244
.access = PL1_R, .type = ARM_CP_CONST,
6245+
.accessfn = access_aa64_tid3,
62056246
/* At present, only SVEver == 0 is defined anyway. */
62066247
.resetvalue = 0 },
62076248
{ .name = "ID_AA64PFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62086249
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 5,
62096250
.access = PL1_R, .type = ARM_CP_CONST,
6251+
.accessfn = access_aa64_tid3,
62106252
.resetvalue = 0 },
62116253
{ .name = "ID_AA64PFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62126254
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 6,
62136255
.access = PL1_R, .type = ARM_CP_CONST,
6256+
.accessfn = access_aa64_tid3,
62146257
.resetvalue = 0 },
62156258
{ .name = "ID_AA64PFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62166259
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 4, .opc2 = 7,
62176260
.access = PL1_R, .type = ARM_CP_CONST,
6261+
.accessfn = access_aa64_tid3,
62186262
.resetvalue = 0 },
62196263
{ .name = "ID_AA64DFR0_EL1", .state = ARM_CP_STATE_AA64,
62206264
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 0,
62216265
.access = PL1_R, .type = ARM_CP_CONST,
6266+
.accessfn = access_aa64_tid3,
62226267
.resetvalue = cpu->id_aa64dfr0 },
62236268
{ .name = "ID_AA64DFR1_EL1", .state = ARM_CP_STATE_AA64,
62246269
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 1,
62256270
.access = PL1_R, .type = ARM_CP_CONST,
6271+
.accessfn = access_aa64_tid3,
62266272
.resetvalue = cpu->id_aa64dfr1 },
62276273
{ .name = "ID_AA64DFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62286274
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 2,
62296275
.access = PL1_R, .type = ARM_CP_CONST,
6276+
.accessfn = access_aa64_tid3,
62306277
.resetvalue = 0 },
62316278
{ .name = "ID_AA64DFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62326279
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 3,
62336280
.access = PL1_R, .type = ARM_CP_CONST,
6281+
.accessfn = access_aa64_tid3,
62346282
.resetvalue = 0 },
62356283
{ .name = "ID_AA64AFR0_EL1", .state = ARM_CP_STATE_AA64,
62366284
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 4,
62376285
.access = PL1_R, .type = ARM_CP_CONST,
6286+
.accessfn = access_aa64_tid3,
62386287
.resetvalue = cpu->id_aa64afr0 },
62396288
{ .name = "ID_AA64AFR1_EL1", .state = ARM_CP_STATE_AA64,
62406289
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 5,
62416290
.access = PL1_R, .type = ARM_CP_CONST,
6291+
.accessfn = access_aa64_tid3,
62426292
.resetvalue = cpu->id_aa64afr1 },
62436293
{ .name = "ID_AA64AFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62446294
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 6,
62456295
.access = PL1_R, .type = ARM_CP_CONST,
6296+
.accessfn = access_aa64_tid3,
62466297
.resetvalue = 0 },
62476298
{ .name = "ID_AA64AFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62486299
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 5, .opc2 = 7,
62496300
.access = PL1_R, .type = ARM_CP_CONST,
6301+
.accessfn = access_aa64_tid3,
62506302
.resetvalue = 0 },
62516303
{ .name = "ID_AA64ISAR0_EL1", .state = ARM_CP_STATE_AA64,
62526304
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 0,
62536305
.access = PL1_R, .type = ARM_CP_CONST,
6306+
.accessfn = access_aa64_tid3,
62546307
.resetvalue = cpu->isar.id_aa64isar0 },
62556308
{ .name = "ID_AA64ISAR1_EL1", .state = ARM_CP_STATE_AA64,
62566309
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 1,
62576310
.access = PL1_R, .type = ARM_CP_CONST,
6311+
.accessfn = access_aa64_tid3,
62586312
.resetvalue = cpu->isar.id_aa64isar1 },
62596313
{ .name = "ID_AA64ISAR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62606314
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 2,
62616315
.access = PL1_R, .type = ARM_CP_CONST,
6316+
.accessfn = access_aa64_tid3,
62626317
.resetvalue = 0 },
62636318
{ .name = "ID_AA64ISAR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62646319
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 3,
62656320
.access = PL1_R, .type = ARM_CP_CONST,
6321+
.accessfn = access_aa64_tid3,
62666322
.resetvalue = 0 },
62676323
{ .name = "ID_AA64ISAR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62686324
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 4,
62696325
.access = PL1_R, .type = ARM_CP_CONST,
6326+
.accessfn = access_aa64_tid3,
62706327
.resetvalue = 0 },
62716328
{ .name = "ID_AA64ISAR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62726329
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 5,
62736330
.access = PL1_R, .type = ARM_CP_CONST,
6331+
.accessfn = access_aa64_tid3,
62746332
.resetvalue = 0 },
62756333
{ .name = "ID_AA64ISAR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62766334
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 6,
62776335
.access = PL1_R, .type = ARM_CP_CONST,
6336+
.accessfn = access_aa64_tid3,
62786337
.resetvalue = 0 },
62796338
{ .name = "ID_AA64ISAR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62806339
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 6, .opc2 = 7,
62816340
.access = PL1_R, .type = ARM_CP_CONST,
6341+
.accessfn = access_aa64_tid3,
62826342
.resetvalue = 0 },
62836343
{ .name = "ID_AA64MMFR0_EL1", .state = ARM_CP_STATE_AA64,
62846344
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 0,
62856345
.access = PL1_R, .type = ARM_CP_CONST,
6346+
.accessfn = access_aa64_tid3,
62866347
.resetvalue = cpu->isar.id_aa64mmfr0 },
62876348
{ .name = "ID_AA64MMFR1_EL1", .state = ARM_CP_STATE_AA64,
62886349
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 1,
62896350
.access = PL1_R, .type = ARM_CP_CONST,
6351+
.accessfn = access_aa64_tid3,
62906352
.resetvalue = cpu->isar.id_aa64mmfr1 },
62916353
{ .name = "ID_AA64MMFR2_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62926354
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 2,
62936355
.access = PL1_R, .type = ARM_CP_CONST,
6356+
.accessfn = access_aa64_tid3,
62946357
.resetvalue = 0 },
62956358
{ .name = "ID_AA64MMFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
62966359
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 3,
62976360
.access = PL1_R, .type = ARM_CP_CONST,
6361+
.accessfn = access_aa64_tid3,
62986362
.resetvalue = 0 },
62996363
{ .name = "ID_AA64MMFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63006364
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 4,
63016365
.access = PL1_R, .type = ARM_CP_CONST,
6366+
.accessfn = access_aa64_tid3,
63026367
.resetvalue = 0 },
63036368
{ .name = "ID_AA64MMFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63046369
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 5,
63056370
.access = PL1_R, .type = ARM_CP_CONST,
6371+
.accessfn = access_aa64_tid3,
63066372
.resetvalue = 0 },
63076373
{ .name = "ID_AA64MMFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63086374
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 6,
63096375
.access = PL1_R, .type = ARM_CP_CONST,
6376+
.accessfn = access_aa64_tid3,
63106377
.resetvalue = 0 },
63116378
{ .name = "ID_AA64MMFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63126379
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 7, .opc2 = 7,
63136380
.access = PL1_R, .type = ARM_CP_CONST,
6381+
.accessfn = access_aa64_tid3,
63146382
.resetvalue = 0 },
63156383
{ .name = "MVFR0_EL1", .state = ARM_CP_STATE_AA64,
63166384
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 0,
63176385
.access = PL1_R, .type = ARM_CP_CONST,
6386+
.accessfn = access_aa64_tid3,
63186387
.resetvalue = cpu->isar.mvfr0 },
63196388
{ .name = "MVFR1_EL1", .state = ARM_CP_STATE_AA64,
63206389
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 1,
63216390
.access = PL1_R, .type = ARM_CP_CONST,
6391+
.accessfn = access_aa64_tid3,
63226392
.resetvalue = cpu->isar.mvfr1 },
63236393
{ .name = "MVFR2_EL1", .state = ARM_CP_STATE_AA64,
63246394
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 2,
63256395
.access = PL1_R, .type = ARM_CP_CONST,
6396+
.accessfn = access_aa64_tid3,
63266397
.resetvalue = cpu->isar.mvfr2 },
63276398
{ .name = "MVFR3_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63286399
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 3,
63296400
.access = PL1_R, .type = ARM_CP_CONST,
6401+
.accessfn = access_aa64_tid3,
63306402
.resetvalue = 0 },
63316403
{ .name = "MVFR4_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63326404
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 4,
63336405
.access = PL1_R, .type = ARM_CP_CONST,
6406+
.accessfn = access_aa64_tid3,
63346407
.resetvalue = 0 },
63356408
{ .name = "MVFR5_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63366409
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 5,
63376410
.access = PL1_R, .type = ARM_CP_CONST,
6411+
.accessfn = access_aa64_tid3,
63386412
.resetvalue = 0 },
63396413
{ .name = "MVFR6_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63406414
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 6,
63416415
.access = PL1_R, .type = ARM_CP_CONST,
6416+
.accessfn = access_aa64_tid3,
63426417
.resetvalue = 0 },
63436418
{ .name = "MVFR7_EL1_RESERVED", .state = ARM_CP_STATE_AA64,
63446419
.opc0 = 3, .opc1 = 0, .crn = 0, .crm = 3, .opc2 = 7,
63456420
.access = PL1_R, .type = ARM_CP_CONST,
6421+
.accessfn = access_aa64_tid3,
63466422
.resetvalue = 0 },
63476423
{ .name = "PMCEID0", .state = ARM_CP_STATE_AA32,
63486424
.cp = 15, .opc1 = 0, .crn = 9, .crm = 12, .opc2 = 6,

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