x86/intel: force tsc to be reliable on Baytrail (v3)

Signed-off-by: youling257 <[email protected]>

(v2)
Changes due to following commit:
34b3fc5 "x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines"

(v3)
Changes due to following commit:
34b3fc5 "x86/cpu/intel: Drop stray FAM6 check with new Intel CPU model defines"

Author: maurossi

arch/x86/kernel/cpu/intel.c

@@ -302,7 +302,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 
 	/* Penwell and Cloverview have the TSC which doesn't sleep on S3 */
 	switch (c->x86_vfm) {
-	case INTEL_FAM6_ATOM_SILVERMONT:
+	case INTEL_ATOM_SILVERMONT:
 		set_cpu_cap(c, X86_FEATURE_TSC_RELIABLE);
 		/* Fall through */
 	case INTEL_ATOM_SALTWELL_MID: