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Icestorm-module.html
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<h1 id="unstable-icestorm-module">Unstable IceStorm module</h1>
<p>This module is available since version 0.45.0.</p>
<p><strong>Note</strong>: this module is unstable. It is only provided as a technology
preview. Its API may change in arbitrary ways between releases or it
might be removed from Meson altogether.</p>
<h2 id="usage">Usage</h2>
<p>This module provides an experimental method to create FPGA bitstreams
using the <a href="http://www.clifford.at/icestorm/">IceStorm</a> suite of tools.</p>
<p>The module exposes only one method called <code>project</code> and it is used
like this:</p>
<pre><code>is.project('projname',
<verilog files>,
constraint_file : <pcf file>,
)
</code></pre>
<p>The input to this function is the set of Verilog files and a
constraint file. This produces output files called <code>projname.asc</code>,
<code>projname.blif</code> and <code>projname.bin</code>. In addition it creates two run
targets called <code>projname-time</code> for running timing analysis and
<code>projname-upload</code> that uploads the generated bitstream to an FPGA
device using the <code>iceprog</code> programming executable.</p>
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