enable

Author: romank-msft

openhcl/hcl/src/ioctl.rs

@@ -2132,6 +2132,8 @@ impl<'a, T: Backing<'a>> ProcessorRunner<'a, T> {
                     | HvX64RegisterName::VsmVpSecureConfigVtl0
                     | HvX64RegisterName::VsmVpSecureConfigVtl1
                     | HvX64RegisterName::CrInterceptControl
+                    | HvX64RegisterName::SevAvicGpa
+                    | HvX64RegisterName::GuestVsmPartitionConfig
             )
         ));
         self.set_vp_registers_hvcall_inner(vtl, &registers)

openhcl/virt_mshv_vtl/src/processor/snp/mod.rs

@@ -463,13 +463,8 @@ impl BackingPrivate for SnpBacked {
             .set_vp_registers_hvcall(Vtl::Vtl0, values)
             .expect("set_vp_registers hypercall for direct overlays should succeed");
 
-        let offload = if this.shared.secure_avic {
-            false // TODO: FLIP THIS
-        } else {
-            false
-        };
-
         // Enable APIC offload if supported for VTL 0.
+        let offload = this.shared.secure_avic;
         this.set_apic_offload(GuestVtl::Vtl0, offload);
         if offload {
             this.backing.cvm.lapics[GuestVtl::Vtl0]
@@ -638,7 +633,7 @@ impl BackingPrivate for SnpBacked {
 impl UhProcessor<'_, SnpBacked> {
     fn set_apic_offload(&mut self, vtl: GuestVtl, offload: bool) {
         assert!(vtl == GuestVtl::Vtl0);
-        tracing::debug!(offload, "Setting APIC offload");
+        tracing::info!(offload, "Setting APIC offload");
         // Share the common architectural parts with TDX.
         if offload {
             // TODO: Load the emulated state into the hardware.
@@ -1110,6 +1105,10 @@ impl UhProcessor<'_, SnpBacked> {
         msr: u32,
         is_write: bool,
     ) {
+        if msr == x86defs::X86X_AMD_MSR_SECURE_AVIC_CONTROL {
+            unimplemented!("secure avic msr access");
+        }
+
         if is_write && self.cvm_try_protect_msr_write(entered_from_vtl, msr) {
             return;
         }
@@ -1394,8 +1393,6 @@ impl UhProcessor<'_, SnpBacked> {
                 } else {
                     &mut self.backing.exit_stats[entered_from_vtl].msr_read
                 }
-
-                // TODO: HAndle Secure AVIC MSR access?
             }
 
             SevExitCode::IOIO => {

vm/x86/x86defs/src/lib.rs

@@ -275,6 +275,7 @@ pub const X86X_AMD_MSR_NB_CFG: u32 = 0xC001001F;
 pub const X86X_AMD_MSR_VM_CR: u32 = 0xC0010114;
 pub const X86X_AMD_MSR_GHCB: u32 = 0xC0010130;
 pub const X86X_AMD_MSR_SEV: u32 = 0xC0010131;
+pub const X86X_AMD_MSR_SECURE_AVIC_CONTROL: u32 = 0xc0010138;
 pub const X86X_AMD_MSR_OSVW_ID_LENGTH: u32 = 0xc0010140;
 pub const X86X_AMD_MSR_OSVW_ID_STATUS: u32 = 0xc0010141;
 pub const X86X_AMD_MSR_DE_CFG: u32 = 0xc0011029;