litedram: Remove remnants of riscv-inits

We still had some wires bringing an extra serial port out of
litedram for the built-in riscv processor. This is all gone now
so take them out.

Signed-off-by: Benjamin Herrenschmidt <[email protected]>

Author: ozbenh

core_dram_tb.vhdl

@@ -91,9 +91,6 @@ begin
             wb_ctrl_is_csr  => wb_dram_is_csr,
             wb_ctrl_is_init => wb_dram_is_init,
 
-            serial_tx	=> open,
-            serial_rx	=> '1',
-
             init_done 	=> open,
             init_error	=> open,
 

dram_tb.vhdl

@@ -61,9 +61,6 @@ begin
             wb_ctrl_is_csr      => '0',
             wb_ctrl_is_init     => '0',
 
-            serial_tx           => open,
-            serial_rx           => '1',
-
             init_done           => open,
             init_error          => open,
 

fpga/top-arty.vhdl

@@ -26,12 +26,6 @@ entity toplevel is
 	uart_main_tx : out std_ulogic;
 	uart_main_rx : in  std_ulogic;
 
-	-- DRAM UART signals (PMOD)
-	uart_pmod_tx    : out std_ulogic;
-	uart_pmod_rx    : in std_ulogic;
-	uart_pmod_cts_n : in std_ulogic;
-	uart_pmod_rts_n : out std_ulogic;
-
 	-- LEDs
 	led0_b	: out std_ulogic;
 	led0_g	: out std_ulogic;
@@ -110,8 +104,6 @@ architecture behaviour of toplevel is
     constant PAYLOAD_SIZE : natural := get_payload_size;
 begin
 
-    uart_pmod_rts_n <= '0';
-
     -- Main SoC
     soc0: entity work.soc
 	generic map(
@@ -232,9 +224,6 @@ begin
 		wb_ctrl_is_csr  => wb_dram_is_csr,
 		wb_ctrl_is_init => wb_dram_is_init,
 
-		serial_tx	=> uart_pmod_tx,
-		serial_rx	=> uart_pmod_rx,
-
 		init_done 	=> dram_init_done,
 		init_error	=> dram_init_error,
 

fpga/top-nexys-video.vhdl

@@ -212,9 +212,6 @@ begin
 		wb_ctrl_is_csr  => wb_dram_is_csr,
 		wb_ctrl_is_init => wb_dram_is_init,
 
-		serial_tx	=> open,
-		serial_rx	=> '0',
-
 		init_done 	=> dram_init_done,
 		init_error	=> dram_init_error,
 

litedram/extras/litedram-wrapper-l2.vhdl

@@ -52,10 +52,6 @@ entity litedram_wrapper is
         wb_ctrl_is_csr  : in std_ulogic;
         wb_ctrl_is_init : in std_ulogic;
 
-        -- Init core serial debug
-        serial_tx     : out std_ulogic;
-        serial_rx     : in std_ulogic;
-
         -- Misc
         init_done     : out std_ulogic;
         init_error    : out std_ulogic;