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| 1 | +From 6a5cf930c34fe2ba29fa3361b07ae42e1e1a66d3 Mon Sep 17 00:00:00 2001 |
| 2 | +From: AKSHAY RAVEENDRAN K < [email protected]> |
| 3 | +Date: Mon, 11 Apr 2022 12:24:33 +0000 |
| 4 | +Subject: [PATCH] Enable WDT2 for causing reset in Kernel/u-boot hang |
| 5 | + |
| 6 | +In the current implementation, WDT1 is enabled as the reset reason |
| 7 | +for u-boot/kernel hang recovery. This fix changes the watchdog timer from |
| 8 | +WDT1 to WDT2 for the u-boot/kernel hang or panic as WDT2 is expected |
| 9 | +here. |
| 10 | + |
| 11 | +Along with this fix, panic time out value is changed from "-1" to "0" in |
| 12 | +kernel configuration file. Which will make the system remain in hang |
| 13 | +instead of rebooting immediately. This will allow WDT2 to complete the |
| 14 | +time out period and trigger the reset. |
| 15 | + |
| 16 | +Tested: |
| 17 | +1. Triggered a kernel panic using "echo c > /proc/sysrq-trigger" command |
| 18 | +and confirmed the reset reason is WDT2 reset. |
| 19 | +2. After 3 kernel panics the BMC is booted to u-boot prompt |
| 20 | +3. The normal BMC resets(ipmitool raw 6 2) are caused by WDT1 only as |
| 21 | +expected. |
| 22 | + |
| 23 | +Signed-off-by: AKSHAY RAVEENDRAN K < [email protected]> |
| 24 | +--- |
| 25 | + arch/arm/dts/ast2600-intel.dts | 2 +- |
| 26 | + arch/arm/mach-aspeed/ast2600/platform.S | 11 +++++++---- |
| 27 | + 2 files changed, 8 insertions(+), 5 deletions(-) |
| 28 | + |
| 29 | +diff --git a/arch/arm/dts/ast2600-intel.dts b/arch/arm/dts/ast2600-intel.dts |
| 30 | +index dba62fd254..b894be2a64 100644 |
| 31 | +--- a/arch/arm/dts/ast2600-intel.dts |
| 32 | ++++ b/arch/arm/dts/ast2600-intel.dts |
| 33 | +@@ -98,7 +98,7 @@ |
| 34 | + |
| 35 | + &wdt1 { |
| 36 | + u-boot,dm-pre-reloc; |
| 37 | +- status = "okay"; |
| 38 | ++ status = "disabled"; |
| 39 | + }; |
| 40 | + |
| 41 | + &wdt2 { |
| 42 | +diff --git a/arch/arm/mach-aspeed/ast2600/platform.S b/arch/arm/mach-aspeed/ast2600/platform.S |
| 43 | +index cc1d6b7a61..967c255cd5 100644 |
| 44 | +--- a/arch/arm/mach-aspeed/ast2600/platform.S |
| 45 | ++++ b/arch/arm/mach-aspeed/ast2600/platform.S |
| 46 | +@@ -78,6 +78,9 @@ |
| 47 | + #define AST_WDT1_RESET_MASK2 (AST_WDT1_BASE + 0x020) |
| 48 | + |
| 49 | + #define AST_WDT2_BASE 0x1E785040 |
| 50 | ++#define AST_WDT2_RELOAD_VAL (AST_WDT2_BASE + 0x004) |
| 51 | ++#define AST_WDT2_RESTART_CTRL (AST_WDT2_BASE + 0x008) |
| 52 | ++#define AST_WDT2_CTRL (AST_WDT2_BASE + 0x00C) |
| 53 | + #define AST_WDT2_RESET_MASK1 (AST_WDT2_BASE + 0x01C) |
| 54 | + #define AST_WDT2_RESET_MASK2 (AST_WDT2_BASE + 0x020) |
| 55 | + |
| 56 | +@@ -388,14 +391,14 @@ wait_lock: |
| 57 | + str r0, [r1] |
| 58 | + |
| 59 | + #ifdef CONFIG_HW_WATCHDOG |
| 60 | +- /* Enable WDT1 to recover u-boot hang */ |
| 61 | +- ldr r0, =AST_WDT1_RELOAD_VAL |
| 62 | ++ /* Enable WDT2 to recover u-boot hang */ |
| 63 | ++ ldr r0, =AST_WDT2_RELOAD_VAL |
| 64 | + ldr r1, =0x00500000 @ ~5 seconds |
| 65 | + str r1, [r0] |
| 66 | +- ldr r0, =AST_WDT1_RESTART_CTRL |
| 67 | ++ ldr r0, =AST_WDT2_RESTART_CTRL |
| 68 | + ldr r1, =0x00004755 |
| 69 | + str r1, [r0] |
| 70 | +- ldr r0, =AST_WDT1_CTRL |
| 71 | ++ ldr r0, =AST_WDT2_CTRL |
| 72 | + ldr r1, =0x00000013 |
| 73 | + str r1, [r0] |
| 74 | + #endif |
| 75 | +-- |
| 76 | +2.17.1 |
| 77 | + |
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