-
Notifications
You must be signed in to change notification settings - Fork 1
/
cpux86-ta.js
executable file
·9719 lines (9580 loc) · 437 KB
/
cpux86-ta.js
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
138
139
140
141
142
143
144
145
146
147
148
149
150
151
152
153
154
155
156
157
158
159
160
161
162
163
164
165
166
167
168
169
170
171
172
173
174
175
176
177
178
179
180
181
182
183
184
185
186
187
188
189
190
191
192
193
194
195
196
197
198
199
200
201
202
203
204
205
206
207
208
209
210
211
212
213
214
215
216
217
218
219
220
221
222
223
224
225
226
227
228
229
230
231
232
233
234
235
236
237
238
239
240
241
242
243
244
245
246
247
248
249
250
251
252
253
254
255
256
257
258
259
260
261
262
263
264
265
266
267
268
269
270
271
272
273
274
275
276
277
278
279
280
281
282
283
284
285
286
287
288
289
290
291
292
293
294
295
296
297
298
299
300
301
302
303
304
305
306
307
308
309
310
311
312
313
314
315
316
317
318
319
320
321
322
323
324
325
326
327
328
329
330
331
332
333
334
335
336
337
338
339
340
341
342
343
344
345
346
347
348
349
350
351
352
353
354
355
356
357
358
359
360
361
362
363
364
365
366
367
368
369
370
371
372
373
374
375
376
377
378
379
380
381
382
383
384
385
386
387
388
389
390
391
392
393
394
395
396
397
398
399
400
401
402
403
404
405
406
407
408
409
410
411
412
413
414
415
416
417
418
419
420
421
422
423
424
425
426
427
428
429
430
431
432
433
434
435
436
437
438
439
440
441
442
443
444
445
446
447
448
449
450
451
452
453
454
455
456
457
458
459
460
461
462
463
464
465
466
467
468
469
470
471
472
473
474
475
476
477
478
479
480
481
482
483
484
485
486
487
488
489
490
491
492
493
494
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
522
523
524
525
526
527
528
529
530
531
532
533
534
535
536
537
538
539
540
541
542
543
544
545
546
547
548
549
550
551
552
553
554
555
556
557
558
559
560
561
562
563
564
565
566
567
568
569
570
571
572
573
574
575
576
577
578
579
580
581
582
583
584
585
586
587
588
589
590
591
592
593
594
595
596
597
598
599
600
601
602
603
604
605
606
607
608
609
610
611
612
613
614
615
616
617
618
619
620
621
622
623
624
625
626
627
628
629
630
631
632
633
634
635
636
637
638
639
640
641
642
643
644
645
646
647
648
649
650
651
652
653
654
655
656
657
658
659
660
661
662
663
664
665
666
667
668
669
670
671
672
673
674
675
676
677
678
679
680
681
682
683
684
685
686
687
688
689
690
691
692
693
694
695
696
697
698
699
700
701
702
703
704
705
706
707
708
709
710
711
712
713
714
715
716
717
718
719
720
721
722
723
724
725
726
727
728
729
730
731
732
733
734
735
736
737
738
739
740
741
742
743
744
745
746
747
748
749
750
751
752
753
754
755
756
757
758
759
760
761
762
763
764
765
766
767
768
769
770
771
772
773
774
775
776
777
778
779
780
781
782
783
784
785
786
787
788
789
790
791
792
793
794
795
796
797
798
799
800
801
802
803
804
805
806
807
808
809
810
811
812
813
814
815
816
817
818
819
820
821
822
823
824
825
826
827
828
829
830
831
832
833
834
835
836
837
838
839
840
841
842
843
844
845
846
847
848
849
850
851
852
853
854
855
856
857
858
859
860
861
862
863
864
865
866
867
868
869
870
871
872
873
874
875
876
877
878
879
880
881
882
883
884
885
886
887
888
889
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910
911
912
913
914
915
916
917
918
919
920
921
922
923
924
925
926
927
928
929
930
931
932
933
934
935
936
937
938
939
940
941
942
943
944
945
946
947
948
949
950
951
952
953
954
955
956
957
958
959
960
961
962
963
964
965
966
967
968
969
970
971
972
973
974
975
976
977
978
979
980
981
982
983
984
985
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
/*
JSLinux-deobfuscated - An annotated version of the original JSLinux.
Original is Copyright (c) 2011-2012 Fabrice Bellard
Redistribution or commercial use is prohibited without the author's permission.
A x86 CPU (circa 486 sans FPU) Emulator
======================================================================
Useful references:
======================================================================
http://pdos.csail.mit.edu/6.828/2005/readings/i386/ <-- super useful
http://ref.x86asm.net/coder32.html#xC4
http://en.wikibooks.org/wiki/X86_Assembly/X86_Architecture
http://en.wikipedia.org/wiki/X86
http://en.wikipedia.org/wiki/Control_register
http://en.wikipedia.org/wiki/X86_assembly_language
http://en.wikipedia.org/wiki/Translation_lookaside_buffer
http://bellard.org/jslinux/tech.html :
The exact restrictions of the emulated CPU are:
- No FPU/MMX/SSE
- No segment limit and right checks when accessing memory
- No single-stepping
Memory Modes
=====================================================================
The x86 transforms logical addresses (i.e., addresses as viewed by
programmers) into physical address (i.e., actual addresses in physical
memory) in two steps:
- Segment translation, in which a logical address (consisting of a
segment selector and segment offset) are converted to a linear
address.
- Page translation, in which a linear address is converted to
a physical address. This step is optional, at the discretion of
systems-software designers.
Paged Memory
--------------
A page table is simply an array of 32-bit page specifiers. A page
table is itself a page, and therefore contains 4 Kilobytes of memory
or at most 1K 32-bit entries. Two levels of tables are used to
address a page of memory. At the higher level is a page directory. The
page directory addresses up to 1K page tables of the second level. A
page table of the second level addresses up to 1K pages. All the
tables addressed by one page directory, therefore, can address 1M
pages (2^(20)). Because each page contains 4K bytes 2^(12) bytes), the
tables of one page directory can span the entire physical address
space of the 80386 (2^(20) times 2^(12) = 2^(32)).
Hints for Bit Twiddling
=========================================================
X & (2^N-1) = mask for lower N bits of X
X & -2^N = mask for upper N bits of X (for two's complement)
X & 3 = mask for lower 2 bits for X
X & 7 = mask for lower 7 bits for X
X & -4096 = mask for upper 20 bits for X
((x << 16) >> 16) = clears top 16bits, enforces word-size data
((x << 24) >> 24) = clears top 24bits, enforces byte-size data
(1<<0 | 1<<4 | 1<<7) = sets bits 0,4,7 to 1, rest to 0
*/
/* Parity Check by LUT:
static const bool ParityTable256[256] = {
# define P2(n) n, n^1, n^1, n
# define P4(n) P2(n), P2(n^1), P2(n^1), P2(n)
# define P6(n) P4(n), P4(n^1), P4(n^1), P4(n)
P6(0), P6(1), P6(1), P6(0) };
unsigned char b; // byte value to compute the parity of
bool parity = ParityTable256[b];
// OR, for 32-bit words: unsigned int v; v ^= v >> 16; v ^= v >> 8; bool parity = ParityTable256[v & 0xff];
// Variation: unsigned char * p = (unsigned char *) &v; parity = ParityTable256[p[0] ^ p[1] ^ p[2] ^ p[3]];
*/
var parity_LUT = [1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1, 1, 0, 0, 1, 0, 1, 1, 0, 1, 0, 0, 1, 0, 1, 1, 0, 0, 1, 1, 0, 1, 0, 0, 1];
var shift16_LUT = [0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14];
var shift8_LUT = [0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 1, 2, 3, 4, 5, 6, 7, 8, 0, 1, 2, 3, 4];
function CPU_X86() {
var i, tlb_size;
/*
AX/EAX/RAX: Accumulator
BX/EBX/RBX: Base index (for use with arrays)
CX/ECX/RCX: Counter
DX/EDX/RDX: Data/general
SI/ESI/RSI: Source index for string operations.
DI/EDI/RDI: Destination index for string operations.
SP/ESP/RSP: Stack pointer for top address of the stack.
BP/EBP/RBP: Stack base pointer for holding the address of the current stack frame.
*/
this.regs = new Array(); // EAX, EBX, ECX, EDX, ESI, EDI, ESP, EBP 32bit registers
for (i = 0; i < 8; i++) {
this.regs[i] = 0;
}
/* IP/EIP/RIP: Instruction pointer. Holds the program counter, the current instruction address. */
this.eip = 0; //instruction pointer
this.cc_op = 0; // current op
this.cc_dst = 0; // current dest
this.cc_src = 0; // current src
this.cc_op2 = 0; // current op, byte2
this.cc_dst2 = 0; // current dest, byte2
this.df = 1; // Direction Flag
/*
0. CF : Carry Flag. Set if the last arithmetic operation carried (addition) or borrowed (subtraction) a
bit beyond the size of the register. This is then checked when the operation is followed with
an add-with-carry or subtract-with-borrow to deal with values too large for just one register to contain.
2. PF : Parity Flag. Set if the number of set bits in the least significant byte is a multiple of 2.
4. AF : Adjust Flag. Carry of Binary Code Decimal (BCD) numbers arithmetic operations.
6. ZF : Zero Flag. Set if the result of an operation is Zero (0).
7. SF : Sign Flag. Set if the result of an operation is negative.
8. TF : Trap Flag. Set if step by step debugging.
9. IF : Interruption Flag. Set if interrupts are enabled.
10. DF : Direction Flag. Stream direction. If set, string operations will decrement their pointer rather
than incrementing it, reading memory backwards.
11. OF : Overflow Flag. Set if signed arithmetic operations result in a value too large for the register to contain.
12-13. IOPL : I/O Privilege Level field (2 bits). I/O Privilege Level of the current process.
14. NT : Nested Task flag. Controls chaining of interrupts. Set if the current process is linked to the next process.
16. RF : Resume Flag. Response to debug exceptions.
17. VM : Virtual-8086 Mode. Set if in 8086 compatibility mode.
18. AC : Alignment Check. Set if alignment checking of memory references is done.
19. VIF : Virtual Interrupt Flag. Virtual image of IF.
20. VIP : Virtual Interrupt Pending flag. Set if an interrupt is pending.
21. ID : Identification Flag. Support for CPUID instruction if can be set.
*/
this.eflags = 0x2; // EFLAG register
this.cycle_count = 0;
this.hard_irq = 0;
this.hard_intno = -1;
this.cpl = 0; //current privilege level
/*
Control Registers
==========================================================================================
*/
/* CR0
---
31 PG Paging If 1, enable paging and use the CR3 register, else disable paging
30 CD Cache disable Globally enables/disable the memory cache
29 NW Not-write through Globally enables/disable write-back caching
18 AM Alignment mask Alignment check enabled if AM set, AC flag (in EFLAGS register) set, and privilege level is 3
16 WP Write protect Determines whether the CPU can write to pages marked read-only
5 NE Numeric error Enable internal x87 floating point error reporting when set, else enables PC style x87 error detection
4 ET Extension type On the 386, it allowed to specify whether the external math coprocessor was an 80287 or 80387
3 TS Task switched Allows saving x87 task context only after x87 instruction used after task switch
2 EM Emulation If set, no x87 floating point unit present, if clear, x87 FPU present
1 MP Monitor co-processor Controls interaction of WAIT/FWAIT instructions with TS flag in CR0
0 PE Protected Mode Enable If 1, system is in protected mode, else system is in real mode
*/
this.cr0 = (1 << 0); //PE-mode ON
/* CR2
---
Page Fault Linear Address (PFLA) When a page fault occurs,
the address the program attempted to access is stored in the
CR2 register. */
this.cr2 = 0;
/* CR3
---
Used when virtual addressing is enabled, hence when the PG
bit is set in CR0. CR3 enables the processor to translate
virtual addresses into physical addresses by locating the page
directory and page tables for the current task.
Typically, the upper 20 bits of CR3 become the page directory
base register (PDBR), which stores the physical address of the
first page directory entry. */
this.cr3 = 0;
/* CR4
---
Used in protected mode to control operations such as virtual-8086 support, enabling I/O breakpoints,
page size extension and machine check exceptions.
Bit Name Full Name Description
18 OSXSAVE XSAVE and Processor Extended States Enable
17 PCIDE PCID Enable If set, enables process-context identifiers (PCIDs).
14 SMXE SMX Enable
13 VMXE VMX Enable
10 OSXMMEXCPT Operating System Support for Unmasked SIMD Floating-Point Exceptions If set, enables unmasked SSE exceptions.
9 OSFXSR Operating system support for FXSAVE and FXSTOR instructions If set, enables SSE instructions and fast FPU save & restore
8 PCE Performance-Monitoring Counter enable
If set, RDPMC can be executed at any privilege level, else RDPMC can only be used in ring 0.
7 PGE Page Global Enabled If set, address translations (PDE or PTE records) may be shared between address spaces.
6 MCE Machine Check Exception If set, enables machine check interrupts to occur.
5 PAE Physical Address Extension
If set, changes page table layout to translate 32-bit virtual addresses into extended 36-bit physical addresses.
4 PSE Page Size Extensions If unset, page size is 4 KB, else page size is increased to 4 MB (ignored with PAE set).
3 DE Debugging Extensions
2 TSD Time Stamp Disable
If set, RDTSC instruction can only be executed when in ring 0, otherwise RDTSC can be used at any privilege level.
1 PVI Protected-mode Virtual Interrupts If set, enables support for the virtual interrupt flag (VIF) in protected mode.
0 VME Virtual 8086 Mode Extensions If set, enables support for the virtual interrupt flag (VIF) in virtual-8086 mode.
*/
this.cr4 = 0;
/*
Segment registers:
--------------------
ES: Extra
CS: Code
SS: Stack
DS: Data
FS: Extra
GS: Extra
In memory addressing for Intel x86 computer architectures,
segment descriptors are a part of the segmentation unit, used for
translating a logical address to a linear address. Segment descriptors
describe the memory segment referred to in the logical address.
The segment descriptor (8 bytes long in 80286) contains the following
fields:
- A segment base address
- The segment limit which specifies the segment limit
- Access rights byte containing the protection mechanism information
- Control bits
*/
/* NOTE: Only segs 0->5 appear to be used in the code, so only ES->GS */
this.segs = new Array(); // [" ES", " CS", " SS", " DS", " FS", " GS", "LDT", " TR"]
for (i = 0; i < 7; i++) {
this.segs[i] = {selector: 0, base: 0, limit: 0, flags: 0};
}
this.segs[2].flags = (1 << 22); // SS
this.segs[1].flags = (1 << 22); // CS
/* Interrupt Descriptor Table
---------------------------
The interrupt descriptor table (IDT) associates each interrupt
or exception identifier with a descriptor for the instructions
that service the associated event. Like the GDT and LDTs, the
IDT is an array of 8-byte descriptors. Unlike the GDT and LDTs,
the first entry of the IDT may contain a descriptor.
To form an index into the IDT, the processor multiplies the
interrupt or exception identifier by eight. Because there are
only 256 identifiers, the IDT need not contain more than 256
descriptors. It can contain fewer than 256 entries; entries are
required only for interrupt identifiers that are actually used. */
this.idt = {base: 0, limit: 0};
// The Global Descriptor Table
this.gdt = {base: 0, limit: 0};
// The Local Descriptor Table
this.ldt = {selector: 0, base: 0, limit: 0, flags: 0};
/* Task Register
--------------
The task register (TR) identifies the currently executing task
by pointing to the TSS.
The task register has both a "visible" portion (i.e., can be
read and changed by instructions) and an "invisible" portion
(maintained by the processor to correspond to the visible
portion; cannot be read by any instruction). The selector in
the visible portion selects a TSS descriptor in the GDT. The
processor uses the invisible portion to cache the base and
limit values from the TSS descriptor. Holding the base and
limit in a register makes execution of the task more efficient,
because the processor does not need to repeatedly fetch these
values from memory when it references the TSS of the current
task.
The instructions LTR and STR are used to modify and read the
visible portion of the task register. Both instructions take
one operand, a 16-bit selector located in memory or in a
general register.
LTR (Load task register) loads the visible portion of the task
register with the selector operand, which must select a TSS
descriptor in the GDT. LTR also loads the invisible portion
with information from the TSS descriptor selected by the
operand. LTR is a privileged instruction; it may be executed
only when CPL is zero. LTR is generally used during system
initialization to give an initial value to the task register;
thereafter, the contents of TR are changed by task switch
operations.
STR (Store task register) stores the visible portion of the task
register in a general register or memory word. STR is not privileged.
All the information the processor needs in order to manage a
task is stored in a special type of segment, a task state
segment (TSS). The fields of a TSS belong to two classes:
1. A dynamic set that the processor updates with each switch from the
task. This set includes the fields that store:
- The general registers (EAX, ECX, EDX, EBX, ESP, EBP, ESI, EDI).
- The segment registers (ES, CS, SS, DS, FS, GS).
- The flags register (EFLAGS).
- The instruction pointer (EIP).
- The selector of the TSS of the previously executing task (updated only when a return is expected).
2. A static set that the processor reads but does not change. This
set includes the fields that store:
- The selector of the task's LDT.
- The register (PDBR) that contains the base address of the task's
page directory (read only when paging is enabled).
- Pointers to the stacks for privilege levels 0-2.
- The T-bit (debug trap bit) which causes the processor to raise a
debug exception when a task switch occurs.
- The I/O map base
*/
this.tr = {selector: 0, base: 0, limit: 0, flags: 0};
this.halted = 0;
this.phys_mem = null; //pointer to raw memory buffer allocated by browser
/*
A translation lookaside buffer (TLB) is a CPU cache that memory
management hardware uses to improve virtual address translation
speed.
A TLB has a fixed number of slots that contain page table
entries, which map virtual addresses to physical addresses. The
virtual memory is the space seen from a process. This space is
segmented in pages of a prefixed size. The page table
(generally loaded in memory) keeps track of where the virtual
pages are loaded in the physical memory. The TLB is a cache of
the page table; that is, only a subset of its content are
stored.
*/
tlb_size = 0x100000; //2^20=1048576 * 4096 ~= 4GB total memory possible
this.tlb_read_kernel = new Int32Array(tlb_size);
this.tlb_write_kernel = new Int32Array(tlb_size);
this.tlb_read_user = new Int32Array(tlb_size);
this.tlb_write_user = new Int32Array(tlb_size);
for (i = 0; i < tlb_size; i++) {
this.tlb_read_kernel[i] = -1;
this.tlb_write_kernel[i] = -1;
this.tlb_read_user[i] = -1;
this.tlb_write_user[i] = -1;
}
this.tlb_pages = new Int32Array(2048);
this.tlb_pages_count = 0;
}
/* Allocates a memory chunnk new_mem_size bytes long and makes 8,16,32 bit array references into it */
CPU_X86.prototype.phys_mem_resize = function(new_mem_size) {
this.mem_size = new_mem_size;
new_mem_size += ((15 + 3) & ~3);
this.phys_mem = new ArrayBuffer(new_mem_size);
this.phys_mem8 = new Uint8Array(this.phys_mem, 0, new_mem_size);
this.phys_mem16 = new Uint16Array(this.phys_mem, 0, new_mem_size / 2);
this.phys_mem32 = new Int32Array(this.phys_mem, 0, new_mem_size / 4);
};
/* Raw, low level memory access routines to alter the host-stored memory, these are called by the higher-level
memory access emulation routines */
CPU_X86.prototype.ld8_phys = function(mem8_loc) { return this.phys_mem8[mem8_loc]; };
CPU_X86.prototype.st8_phys = function(mem8_loc, x) { this.phys_mem8[mem8_loc] = x; };
CPU_X86.prototype.ld32_phys = function(mem8_loc) { return this.phys_mem32[mem8_loc >> 2]; };
CPU_X86.prototype.st32_phys = function(mem8_loc, x) { this.phys_mem32[mem8_loc >> 2] = x; };
/*
TLB Routines
==========================================================================================
*/
CPU_X86.prototype.tlb_set_page = function(mem8_loc, page_val, set_write_tlb, set_user_tlb) {
var i, x, j;
page_val &= -4096; // only top 20bits matter
mem8_loc &= -4096; // only top 20bits matter
x = mem8_loc ^ page_val; // XOR used to simulate hashing
i = mem8_loc >>> 12; // top 20bits point to TLB
if (this.tlb_read_kernel[i] == -1) {
if (this.tlb_pages_count >= 2048) {
this.tlb_flush_all1((i - 1) & 0xfffff);
}
this.tlb_pages[this.tlb_pages_count++] = i;
}
this.tlb_read_kernel[i] = x;
if (set_write_tlb) {
this.tlb_write_kernel[i] = x;
} else {
this.tlb_write_kernel[i] = -1;
}
if (set_user_tlb) {
this.tlb_read_user[i] = x;
if (set_write_tlb) {
this.tlb_write_user[i] = x;
} else {
this.tlb_write_user[i] = -1;
}
} else {
this.tlb_read_user[i] = -1;
this.tlb_write_user[i] = -1;
}
};
CPU_X86.prototype.tlb_flush_page = function(mem8_loc) {
var i;
i = mem8_loc >>> 12;
this.tlb_read_kernel[i] = -1;
this.tlb_write_kernel[i] = -1;
this.tlb_read_user[i] = -1;
this.tlb_write_user[i] = -1;
};
CPU_X86.prototype.tlb_flush_all = function() {
var i, j, n, tlb_pages;
tlb_pages = this.tlb_pages;
n = this.tlb_pages_count;
for (j = 0; j < n; j++) {
i = tlb_pages[j];
this.tlb_read_kernel[i] = -1;
this.tlb_write_kernel[i] = -1;
this.tlb_read_user[i] = -1;
this.tlb_write_user[i] = -1;
}
this.tlb_pages_count = 0;
};
CPU_X86.prototype.tlb_flush_all1 = function(la) {
var i, j, n, tlb_pages, new_n;
tlb_pages = this.tlb_pages;
n = this.tlb_pages_count;
new_n = 0;
for (j = 0; j < n; j++) {
i = tlb_pages[j];
if (i == la) {
tlb_pages[new_n++] = i;
} else {
this.tlb_read_kernel[i] = -1;
this.tlb_write_kernel[i] = -1;
this.tlb_read_user[i] = -1;
this.tlb_write_user[i] = -1;
}
}
this.tlb_pages_count = new_n;
};
/*
String / Logging Routines
==========================================================================================
*/
/* writes ASCII string in na into memory location mem8_loc */
CPU_X86.prototype.write_string = function(mem8_loc, str) {
var i;
for (i = 0; i < str.length; i++) {
this.st8_phys(mem8_loc++, str.charCodeAt(i) & 0xff);
}
this.st8_phys(mem8_loc, 0);
};
/* Represents numeric value ga as n-digit HEX */
function hex_rep(x, n) {
var i, s;
var h = "0123456789ABCDEF";
s = "";
for (i = n - 1; i >= 0; i--) {
s = s + h[(x >>> (i * 4)) & 15];
}
return s;
}
function _4_bytes_(n) { return hex_rep(n, 8);} // Represents 8-hex bytes of n
function _2_bytes_(n) { return hex_rep(n, 2);} // Represents 4-hex bytes of n
function _1_byte_(n) { return hex_rep(n, 4);} // Represents 2-hex bytes of n
CPU_X86.prototype.dump_short = function() {
console.log(" EIP=" + _4_bytes_(this.eip) + " EAX=" + _4_bytes_(this.regs[0])
+ " ECX=" + _4_bytes_(this.regs[1]) + " EDX=" + _4_bytes_(this.regs[2]) + " EBX=" + _4_bytes_(this.regs[3]));
console.log(" EFL=" + _4_bytes_(this.eflags) + " ESP=" + _4_bytes_(this.regs[4])
+ " EBP=" + _4_bytes_(this.regs[5]) + " ESI=" + _4_bytes_(this.regs[6]) + " EDI=" + _4_bytes_(this.regs[7]));
};
CPU_X86.prototype.dump = function() {
var i, descriptor_table, str;
var ta = [" ES", " CS", " SS", " DS", " FS", " GS", "LDT", " TR"];
this.dump_short();
console.log("TSC=" + _4_bytes_(this.cycle_count) + " OP=" + _2_bytes_(this.cc_op)
+ " SRC=" + _4_bytes_(this.cc_src) + " DST=" + _4_bytes_(this.cc_dst)
+ " OP2=" + _2_bytes_(this.cc_op2) + " DST2=" + _4_bytes_(this.cc_dst2));
console.log("CPL=" + this.cpl + " CR0=" + _4_bytes_(this.cr0)
+ " CR2=" + _4_bytes_(this.cr2) + " CR3=" + _4_bytes_(this.cr3) + " CR4=" + _4_bytes_(this.cr4));
str = "";
for (i = 0; i < 8; i++) {
if (i == 6)
descriptor_table = this.ldt;
else if (i == 7)
descriptor_table = this.tr;
else
descriptor_table = this.segs[i];
str += ta[i] + "=" + _1_byte_(descriptor_table.selector) + " " + _4_bytes_(descriptor_table.base) + " "
+ _4_bytes_(descriptor_table.limit) + " " + _1_byte_((descriptor_table.flags >> 8) & 0xf0ff);
if (i & 1) {
console.log(str);
str = "";
} else {
str += " ";
}
}
descriptor_table = this.gdt;
str = "GDT= " + _4_bytes_(descriptor_table.base) + " " + _4_bytes_(descriptor_table.limit) + " ";
descriptor_table = this.idt;
str += "IDT= " + _4_bytes_(descriptor_table.base) + " " + _4_bytes_(descriptor_table.limit);
console.log(str);
};
/*
The Beast
==========================================================================================
*/
CPU_X86.prototype.exec_internal = function(N_cycles, interrupt) {
/*
x,y,z,v are either just general non-local values or their exact specialization is unclear,
esp. x,y look like they're used for everything
I don't know what 'v' should be called, it's not clear yet
*/
var cpu, mem8_loc, regs;
var _src, _dst, _op, _op2, _dst2;
var CS_flags, mem8, reg_idx0, OPbyte, reg_idx1, x, y, z, conditional_var, cycles_left, exit_code, v;
var CS_base, SS_base, SS_mask, FS_usage_flag, init_CS_flags, iopl;//io privilege level
var phys_mem8, last_tlb_val;
var phys_mem16, phys_mem32;
var tlb_read_kernel, tlb_write_kernel, tlb_read_user, tlb_write_user, _tlb_read_, _tlb_write_;
/*
Paged Memory Mode Access Routines
================================================================================
*/
/* Storing XOR values as small lookup table is software equivalent of a Translation Lookaside Buffer (TLB) */
function __ld_8bits_mem8_read() {
var tlb_lookup;
do_tlb_set_page(mem8_loc, 0, cpu.cpl == 3);
tlb_lookup = _tlb_read_[mem8_loc >>> 12] ^ mem8_loc;
return phys_mem8[tlb_lookup];
}
function ld_8bits_mem8_read() {
var last_tlb_val;
return (((last_tlb_val = _tlb_read_[mem8_loc >>> 12]) == -1) ? __ld_8bits_mem8_read() : phys_mem8[mem8_loc ^ last_tlb_val]);
}
function __ld_16bits_mem8_read() {
var x;
x = ld_8bits_mem8_read();
mem8_loc++;
x |= ld_8bits_mem8_read() << 8;
mem8_loc--;
return x;
}
function ld_16bits_mem8_read() {
var last_tlb_val;
return (((last_tlb_val = _tlb_read_[mem8_loc >>> 12]) | mem8_loc) & 1 ? __ld_16bits_mem8_read() : phys_mem16[(mem8_loc ^ last_tlb_val) >> 1]);
}
function __ld_32bits_mem8_read() {
var x;
x = ld_8bits_mem8_read();
mem8_loc++;
x |= ld_8bits_mem8_read() << 8;
mem8_loc++;
x |= ld_8bits_mem8_read() << 16;
mem8_loc++;
x |= ld_8bits_mem8_read() << 24;
mem8_loc -= 3;
return x;
}
function ld_32bits_mem8_read() {
var last_tlb_val;
return (((last_tlb_val = _tlb_read_[mem8_loc >>> 12]) | mem8_loc) & 3 ? __ld_32bits_mem8_read() : phys_mem32[(mem8_loc ^ last_tlb_val) >> 2]);
}
function __ld_8bits_mem8_write() {
var tlb_lookup;
do_tlb_set_page(mem8_loc, 1, cpu.cpl == 3);
tlb_lookup = _tlb_write_[mem8_loc >>> 12] ^ mem8_loc;
return phys_mem8[tlb_lookup];
}
function ld_8bits_mem8_write() {
var tlb_lookup;
return ((tlb_lookup = _tlb_write_[mem8_loc >>> 12]) == -1) ? __ld_8bits_mem8_write() : phys_mem8[mem8_loc ^ tlb_lookup];
}
function __ld_16bits_mem8_write() {
var x;
x = ld_8bits_mem8_write();
mem8_loc++;
x |= ld_8bits_mem8_write() << 8;
mem8_loc--;
return x;
}
function ld_16bits_mem8_write() {
var tlb_lookup;
return ((tlb_lookup = _tlb_write_[mem8_loc >>> 12]) | mem8_loc) & 1 ? __ld_16bits_mem8_write() : phys_mem16[(mem8_loc ^ tlb_lookup) >> 1];
}
function __ld_32bits_mem8_write() {
var x;
x = ld_8bits_mem8_write();
mem8_loc++;
x |= ld_8bits_mem8_write() << 8;
mem8_loc++;
x |= ld_8bits_mem8_write() << 16;
mem8_loc++;
x |= ld_8bits_mem8_write() << 24;
mem8_loc -= 3;
return x;
}
function ld_32bits_mem8_write() {
var tlb_lookup;
return ((tlb_lookup = _tlb_write_[mem8_loc >>> 12]) | mem8_loc) & 3 ? __ld_32bits_mem8_write() : phys_mem32[(mem8_loc ^ tlb_lookup) >> 2];
}
function __st8_mem8_write(x) {
var tlb_lookup;
do_tlb_set_page(mem8_loc, 1, cpu.cpl == 3);
tlb_lookup = _tlb_write_[mem8_loc >>> 12] ^ mem8_loc;
phys_mem8[tlb_lookup] = x;
}
function st8_mem8_write(x) {
var last_tlb_val;
{
last_tlb_val = _tlb_write_[mem8_loc >>> 12];
if (last_tlb_val == -1) {
__st8_mem8_write(x);
} else {
phys_mem8[mem8_loc ^ last_tlb_val] = x;
}
}
}
function __st16_mem8_write(x) {
st8_mem8_write(x);
mem8_loc++;
st8_mem8_write(x >> 8);
mem8_loc--;
}
function st16_mem8_write(x) {
var last_tlb_val;
{
last_tlb_val = _tlb_write_[mem8_loc >>> 12];
if ((last_tlb_val | mem8_loc) & 1) {
__st16_mem8_write(x);
} else {
phys_mem16[(mem8_loc ^ last_tlb_val) >> 1] = x;
}
}
}
function __st32_mem8_write(x) {
st8_mem8_write(x);
mem8_loc++;
st8_mem8_write(x >> 8);
mem8_loc++;
st8_mem8_write(x >> 16);
mem8_loc++;
st8_mem8_write(x >> 24);
mem8_loc -= 3;
}
function st32_mem8_write(x) {
var last_tlb_val;
{
last_tlb_val = _tlb_write_[mem8_loc >>> 12];
if ((last_tlb_val | mem8_loc) & 3) {
__st32_mem8_write(x);
} else {
phys_mem32[(mem8_loc ^ last_tlb_val) >> 2] = x;
}
}
}
function __ld8_mem8_kernel_read() {
var tlb_lookup;
do_tlb_set_page(mem8_loc, 0, 0);
tlb_lookup = tlb_read_kernel[mem8_loc >>> 12] ^ mem8_loc;
return phys_mem8[tlb_lookup];
}
function ld8_mem8_kernel_read() {
var tlb_lookup;
return ((tlb_lookup = tlb_read_kernel[mem8_loc >>> 12]) == -1) ? __ld8_mem8_kernel_read() : phys_mem8[mem8_loc ^ tlb_lookup];
}
function __ld16_mem8_kernel_read() {
var x;
x = ld8_mem8_kernel_read();
mem8_loc++;
x |= ld8_mem8_kernel_read() << 8;
mem8_loc--;
return x;
}
function ld16_mem8_kernel_read() {
var tlb_lookup;
return ((tlb_lookup = tlb_read_kernel[mem8_loc >>> 12]) | mem8_loc) & 1 ? __ld16_mem8_kernel_read() : phys_mem16[(mem8_loc ^ tlb_lookup) >> 1];
}
function __ld32_mem8_kernel_read() {
var x;
x = ld8_mem8_kernel_read();
mem8_loc++;
x |= ld8_mem8_kernel_read() << 8;
mem8_loc++;
x |= ld8_mem8_kernel_read() << 16;
mem8_loc++;
x |= ld8_mem8_kernel_read() << 24;
mem8_loc -= 3;
return x;
}
function ld32_mem8_kernel_read() {
var tlb_lookup;
return ((tlb_lookup = tlb_read_kernel[mem8_loc >>> 12]) | mem8_loc) & 3 ? __ld32_mem8_kernel_read() : phys_mem32[(mem8_loc ^ tlb_lookup) >> 2];
}
function __st8_mem8_kernel_write(x) {
var tlb_lookup;
do_tlb_set_page(mem8_loc, 1, 0);
tlb_lookup = tlb_write_kernel[mem8_loc >>> 12] ^ mem8_loc;
phys_mem8[tlb_lookup] = x;
}
function st8_mem8_kernel_write(x) {
var tlb_lookup;
tlb_lookup = tlb_write_kernel[mem8_loc >>> 12];
if (tlb_lookup == -1) {
__st8_mem8_kernel_write(x);
} else {
phys_mem8[mem8_loc ^ tlb_lookup] = x;
}
}
function __st16_mem8_kernel_write(x) {
st8_mem8_kernel_write(x);
mem8_loc++;
st8_mem8_kernel_write(x >> 8);
mem8_loc--;
}
function st16_mem8_kernel_write(x) {
var tlb_lookup;
tlb_lookup = tlb_write_kernel[mem8_loc >>> 12];
if ((tlb_lookup | mem8_loc) & 1) {
__st16_mem8_kernel_write(x);
} else {
phys_mem16[(mem8_loc ^ tlb_lookup) >> 1] = x;
}
}
function __st32_mem8_kernel_write(x) {
st8_mem8_kernel_write(x);
mem8_loc++;
st8_mem8_kernel_write(x >> 8);
mem8_loc++;
st8_mem8_kernel_write(x >> 16);
mem8_loc++;
st8_mem8_kernel_write(x >> 24);
mem8_loc -= 3;
}
function st32_mem8_kernel_write(x) {
var tlb_lookup;
tlb_lookup = tlb_write_kernel[mem8_loc >>> 12];
if ((tlb_lookup | mem8_loc) & 3) {
__st32_mem8_kernel_write(x);
} else {
phys_mem32[(mem8_loc ^ tlb_lookup) >> 2] = x;
}
}
var eip, physmem8_ptr, eip_tlb_val, initial_mem_ptr, eip_offset;
function ld16_mem8_direct() {
var x, y;
x = phys_mem8[physmem8_ptr++];
y = phys_mem8[physmem8_ptr++];
return x | (y << 8);
}
/*
Segmented Memory Mode Routines
================================================================================
Segmented Memory
-----------------
x86 memory segmentation refers to the implementation of memory
segmentation on the x86 architecture. Memory is divided into portions
that may be addressed by a single index register without changing a
16-bit segment selector. In real mode or V86 mode, a segment is always
64 kilobytes in size (using 16-bit offsets). In protected mode, a
segment can have variable length. Segments can overlap.
Within the x86 architectures, when operating in the real (compatible)
mode, physical address is computed as:
Address = 16*segment + offset
The 16-bit segment register is shifted
left by 4 bits and added to a 16-bit offset, resulting in a 20-bit
address.
When the 80386 is used to execute software designed for architectures
that don't have segments, it may be expedient to effectively "turn
off" the segmentation features of the 80386. The 80386 does not have a
mode that disables segmentation, but the same effect can be achieved
by initially loading the segment registers with selectors for
descriptors that encompass the entire 32-bit linear address
space. Once loaded, the segment registers don't need to be
changed. The 32-bit offsets used by 80386 instructions are adequate to
address the entire linear-address space.
*/
/*
segment translation routine (I believe):
Translates Logical Memory Address to Linear Memory Address
*/
function segment_translation(mem8) {
var base, mem8_loc, Qb, Rb, Sb, Tb;
if (FS_usage_flag && (CS_flags & (0x000f | 0x0080)) == 0) {
switch ((mem8 & 7) | ((mem8 >> 3) & 0x18)) {
case 0x04:
Qb = phys_mem8[physmem8_ptr++];
base = Qb & 7;
if (base == 5) {
{
mem8_loc = phys_mem8[physmem8_ptr] | (phys_mem8[physmem8_ptr + 1] << 8) | (phys_mem8[physmem8_ptr + 2] << 16) | (phys_mem8[physmem8_ptr + 3] << 24);
physmem8_ptr += 4;
}
} else {
mem8_loc = regs[base];
}
Rb = (Qb >> 3) & 7;
if (Rb != 4) {
mem8_loc = (mem8_loc + (regs[Rb] << (Qb >> 6))) >> 0;
}
break;
case 0x0c:
Qb = phys_mem8[physmem8_ptr++];
mem8_loc = ((phys_mem8[physmem8_ptr++] << 24) >> 24);
base = Qb & 7;
mem8_loc = (mem8_loc + regs[base]) >> 0;
Rb = (Qb >> 3) & 7;
if (Rb != 4) {
mem8_loc = (mem8_loc + (regs[Rb] << (Qb >> 6))) >> 0;
}
break;
case 0x14:
Qb = phys_mem8[physmem8_ptr++];
{
mem8_loc = phys_mem8[physmem8_ptr] | (phys_mem8[physmem8_ptr + 1] << 8) | (phys_mem8[physmem8_ptr + 2] << 16) | (phys_mem8[physmem8_ptr + 3] << 24);
physmem8_ptr += 4;
}
base = Qb & 7;
mem8_loc = (mem8_loc + regs[base]) >> 0;
Rb = (Qb >> 3) & 7;
if (Rb != 4) {
mem8_loc = (mem8_loc + (regs[Rb] << (Qb >> 6))) >> 0;
}
break;
case 0x05:
{
mem8_loc = phys_mem8[physmem8_ptr] | (phys_mem8[physmem8_ptr + 1] << 8) | (phys_mem8[physmem8_ptr + 2] << 16) | (phys_mem8[physmem8_ptr + 3] << 24);
physmem8_ptr += 4;
}
break;
case 0x00:
case 0x01:
case 0x02:
case 0x03:
case 0x06:
case 0x07:
base = mem8 & 7;
mem8_loc = regs[base];
break;
case 0x08:
case 0x09:
case 0x0a:
case 0x0b:
case 0x0d:
case 0x0e:
case 0x0f:
mem8_loc = ((phys_mem8[physmem8_ptr++] << 24) >> 24);
base = mem8 & 7;
mem8_loc = (mem8_loc + regs[base]) >> 0;
break;
case 0x10:
case 0x11:
case 0x12:
case 0x13:
case 0x15:
case 0x16:
case 0x17:
default:
{
mem8_loc = phys_mem8[physmem8_ptr] | (phys_mem8[physmem8_ptr + 1] << 8) | (phys_mem8[physmem8_ptr + 2] << 16) | (phys_mem8[physmem8_ptr + 3] << 24);
physmem8_ptr += 4;
}
base = mem8 & 7;
mem8_loc = (mem8_loc + regs[base]) >> 0;
break;
}
return mem8_loc;
} else if (CS_flags & 0x0080) {
if ((mem8 & 0xc7) == 0x06) {
mem8_loc = ld16_mem8_direct();
Tb = 3;
} else {
switch (mem8 >> 6) {
case 0:
mem8_loc = 0;
break;
case 1:
mem8_loc = ((phys_mem8[physmem8_ptr++] << 24) >> 24);
break;
default:
mem8_loc = ld16_mem8_direct();
break;
}
switch (mem8 & 7) {
case 0:
mem8_loc = (mem8_loc + regs[3] + regs[6]) & 0xffff;
Tb = 3;
break;
case 1:
mem8_loc = (mem8_loc + regs[3] + regs[7]) & 0xffff;
Tb = 3;
break;
case 2:
mem8_loc = (mem8_loc + regs[5] + regs[6]) & 0xffff;
Tb = 2;
break;
case 3:
mem8_loc = (mem8_loc + regs[5] + regs[7]) & 0xffff;
Tb = 2;
break;
case 4:
mem8_loc = (mem8_loc + regs[6]) & 0xffff;
Tb = 3;
break;
case 5:
mem8_loc = (mem8_loc + regs[7]) & 0xffff;
Tb = 3;
break;
case 6:
mem8_loc = (mem8_loc + regs[5]) & 0xffff;
Tb = 2;
break;
case 7:
default:
mem8_loc = (mem8_loc + regs[3]) & 0xffff;
Tb = 3;
break;
}
}
Sb = CS_flags & 0x000f;
if (Sb == 0) {
Sb = Tb;
} else {
Sb--;
}
mem8_loc = (mem8_loc + cpu.segs[Sb].base) >> 0;
return mem8_loc;
} else {
switch ((mem8 & 7) | ((mem8 >> 3) & 0x18)) {
case 0x04:
Qb = phys_mem8[physmem8_ptr++];
base = Qb & 7;
if (base == 5) {
{
mem8_loc = phys_mem8[physmem8_ptr] | (phys_mem8[physmem8_ptr + 1] << 8) | (phys_mem8[physmem8_ptr + 2] << 16) | (phys_mem8[physmem8_ptr + 3] << 24);
physmem8_ptr += 4;
}
base = 0;
} else {
mem8_loc = regs[base];
}
Rb = (Qb >> 3) & 7;
if (Rb != 4) {
mem8_loc = (mem8_loc + (regs[Rb] << (Qb >> 6))) >> 0;
}
break;
case 0x0c:
Qb = phys_mem8[physmem8_ptr++];
mem8_loc = ((phys_mem8[physmem8_ptr++] << 24) >> 24);
base = Qb & 7;
mem8_loc = (mem8_loc + regs[base]) >> 0;
Rb = (Qb >> 3) & 7;
if (Rb != 4) {
mem8_loc = (mem8_loc + (regs[Rb] << (Qb >> 6))) >> 0;
}
break;
case 0x14:
Qb = phys_mem8[physmem8_ptr++];
{
mem8_loc = phys_mem8[physmem8_ptr] | (phys_mem8[physmem8_ptr + 1] << 8) | (phys_mem8[physmem8_ptr + 2] << 16) | (phys_mem8[physmem8_ptr + 3] << 24);
physmem8_ptr += 4;
}
base = Qb & 7;
mem8_loc = (mem8_loc + regs[base]) >> 0;
Rb = (Qb >> 3) & 7;