diff --git a/source/Hardware Guide/Breakout Board/index.rst b/source/Hardware Guide/Breakout Board/index.rst index 8d8d0cb7..606c1355 100644 --- a/source/Hardware Guide/Breakout Board/index.rst +++ b/source/Hardware Guide/Breakout Board/index.rst @@ -14,7 +14,10 @@ data IO. :Design Repository: https://github.com/open-ephys/onix-breakout :Compatibility: :ref:`pcie_host`, :ref:`headstage_64`, - :ref:`headstage_neuropix1`, :ref:`miniscopes` + :ref:`headstage_neuropix1`, :ref:`miniscopes`, + :doc:`../Headstages/headstage-neuropix-1e`, + :doc:`../Headstages/headstage-neuropix-2e`, + :doc:`../Headstages/headstage-rhs2116` .. _breakout_overview: @@ -24,30 +27,30 @@ Overview The **ONIX Breakout Board** allows bench access to the IO provided by the :ref:`pcie_host`. -.. figure:: /_static/images/breakout/breakout_edited_callouts.png +.. figure:: /_static/images/breakout/breakout_1r6_callouts.png :align: center - ONIX Breakout Board v1.5. + ONIX Breakout Board v1.6. Features ------------------------- The Breakout Board provides access to the following IO: -- 2x headstage port feed-throughs, each with a power switch -- 3x, passive, high-speed clock feed-throughs +- 2x headstage port feed-throughs, each with a power switch. +- 3x, passive, high-speed clock feed-throughs. These can be used to connect to the two clock inputs and one clock output on the PCIe controller. - 12x passive, ESD-protected, analog feed-throughs. -- BNC, ribbon, or direct wire access to 12 analog inputs or outputs +- BNC, ribbon, or direct wire access to 12 analog inputs or outputs. These have a ±10V range and are sampled at 100 kHz. - Ribbon cable or direct, wire-access to 8 digital outputs and 8 digital - inputs. These are 5V compliant. -- `HARP bus `__ controller + inputs. These are 5V compliant and are sampled at 5 MHz. +- `HARP `__ synchronization clock input bus Additionally, it has the following features: -- Lots of indication LEDs +- Lots of indication LEDs. - 6 buttons for marking experimental events for or triggering software actions. - Rugged M6 and 1/4-20 mounting holes for both metric and imperial optical - tables -- 19" rack compatibility + tables. +- 19" rack compatibility. - Fully open-source gateware and made using an open-source FPGA toolchain (`yosys `__ & `nextpnr - `__) + `__). diff --git a/source/Hardware Guide/Breakout Board/setup.rst b/source/Hardware Guide/Breakout Board/setup.rst index 5ea646e5..4f7b27e8 100644 --- a/source/Hardware Guide/Breakout Board/setup.rst +++ b/source/Hardware Guide/Breakout Board/setup.rst @@ -15,16 +15,11 @@ PCIe host is connected to a breakout board using the following connections: power to the Breakout Board. #. Headstage links (Required for headstages): A single MMCX coaxial cable is used for each headstage port. -#. High speed clocks (Optional): A single MMCX caoxial cable is used for each +#. High speed clocks (Optional): A single MMCX coaxial cable is used for each clock signal -#. HARP (Optional): A 3.5mm audio jack #. Configuration (Optional): Micro USB used to update the breakout gateware. -.. image:: /_static/images/breakout/breakout_host_connections_callouts.png - :align: center - :width: 60% - -.. image:: /_static/images/breakout/bb_cables.jpg +.. image:: /_static/images/breakout/bb_1r6_cables_callouts.png :align: center :width: 60% @@ -33,8 +28,7 @@ each of these signal lines are acquired. .. note:: There may be more IO present on the breakout board than is available on a particular host board. For instance, :ref:`pcie_host` has two coaxial - links, but the breakout board provides four. This is is by design. The breakout - is designed to be compatible with future host hardware. + links, but the v1.5beta breakout board provides four. Reset Button ________________________ @@ -79,11 +73,13 @@ Plug in MMCX coaxial connections for headstage ports and clock signals. - Use the MMCX to MMCX cable to connect a headstage port on the :ref:`pcie_host` to the breakout board. A single cable is required for each headstage port. -- Make sure that port letter (A, B, C, D) on the breakout matches the port +- Make sure that port letter (A, B) on the breakout matches the port letter on the PCIe host. -- Additional MMCX cables can be used to connect the optional clock IO ports - on the PCIe host board to the clock ports on the breakout board. These - are passive, 50-ohm transmission lines so the order does not matter. +- If you are feeding the clock inputs/outputs from the controller through + the breakout board, make sure that the port number (0, 1, 2) on the breakout + board matches the port number on the PCIe host (0 In, 1 In, 2 Out). Older 3D printed versions of + the PCIe bracket label the clock ports as I\ :sub:`0`\, I\ :sub:`1`\, and O - + these should connect to the breakout board ports 0, 1, 2, respectively. .. warning:: The MMCX connectors can be damaged if they are removed improperly. See :ref:`this link ` for information on how to diff --git a/source/Hardware Guide/PCIe Host/index.rst b/source/Hardware Guide/PCIe Host/index.rst index 2570f2bb..1ab80727 100644 --- a/source/Hardware Guide/PCIe Host/index.rst +++ b/source/Hardware Guide/PCIe Host/index.rst @@ -21,6 +21,9 @@ equipment. :Design Repository: https://github.com/open-ephys/onix-fmc-host :Compatibility: :ref:`headstage_64`, :ref:`headstage_neuropix1`, :ref:`miniscopes` - -.. figure:: /_static/images/pcie-host/pcie-host_nereid_fmc-host-1r4.jpg + :doc:`../Headstages/headstage-neuropix-1e`, + :doc:`../Headstages/headstage-neuropix-2e`, + :doc:`../Headstages/headstage-rhs2116` + +.. figure:: /_static/images/pcie-host/pcie-controller.jpg :align: center diff --git a/source/Hardware Guide/PCIe Host/overview.rst b/source/Hardware Guide/PCIe Host/overview.rst index 6fda6f17..edce07a6 100644 --- a/source/Hardware Guide/PCIe Host/overview.rst +++ b/source/Hardware Guide/PCIe Host/overview.rst @@ -11,7 +11,11 @@ provided by the `Numato Nereid `__ carrier board. -.. figure:: /_static/images/pcie-host/host-board_edited_callouts.jpg +.. figure:: /_static/images/pcie-host/pcie-controller-callouts.png + :align: center + :width: 500px + +.. figure:: /_static/images/pcie-host/pcie-controller_front_callouts.png :align: center :width: 500px @@ -21,6 +25,7 @@ carrier board. - 8x digital inputs - 8x digital outputs - 12x analog outputs or inputs (±10V) + - 2x clock inputs, 1x clock output - Multi-board synchronization and triggering to increase number of headstages and IO diff --git a/source/_static/images/breakout/Artboard 6.jpg b/source/_static/images/breakout/Artboard 6.jpg deleted file mode 100644 index 505c7962..00000000 Binary files a/source/_static/images/breakout/Artboard 6.jpg and /dev/null differ diff --git a/source/_static/images/breakout/breakout_1r5_beta.xcf b/source/_static/images/breakout/bb_1r6_cables.png similarity index 57% rename from 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100644 index 00000000..654fa93f --- /dev/null +++ b/source/_static/images/breakout/breakout_1r6_callouts.svg @@ -0,0 +1,355 @@ + + + +ONIXclock outputHarpclock inputAnalog IO: ±10V, 100kHz / chan., input or output19” (48.3 cm) rack-mount compatibleDigital IO 5 MHz / chan.Headstageports (2x)Breadboard or 80/20 railmount points (metric or imperial) diff --git a/source/_static/images/breakout/breakout_1r6_host_connections.png b/source/_static/images/breakout/breakout_1r6_host_connections.png new file mode 100644 index 00000000..e3315202 Binary files /dev/null and b/source/_static/images/breakout/breakout_1r6_host_connections.png differ diff --git a/source/_static/images/breakout/breakout_edited_callouts.pdf b/source/_static/images/breakout/breakout_edited_callouts.pdf deleted file mode 100644 index b35b59c4..00000000 Binary files a/source/_static/images/breakout/breakout_edited_callouts.pdf and /dev/null differ diff --git a/source/_static/images/breakout/breakout_edited_callouts.png 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a/source/_static/images/pcie-host/pcie-controller-callouts.png b/source/_static/images/pcie-host/pcie-controller-callouts.png new file mode 100644 index 00000000..41c5b3f3 Binary files /dev/null and b/source/_static/images/pcie-host/pcie-controller-callouts.png differ diff --git a/source/_static/images/pcie-host/pcie-controller-callouts.svg b/source/_static/images/pcie-host/pcie-controller-callouts.svg new file mode 100644 index 00000000..b465bc04 --- /dev/null +++ b/source/_static/images/pcie-host/pcie-controller-callouts.svg @@ -0,0 +1,210 @@ + + + +Auxiliary analog& digital IOClocks forexternal syncONIXheadstageportsInter-boardsyncGen 2PCIe busKintex 7FPGA4GB DDR3 SDRAMdata buffer diff --git a/source/_static/images/pcie-host/pcie-controller.jpg b/source/_static/images/pcie-host/pcie-controller.jpg new file mode 100644 index 00000000..22161bd6 Binary files /dev/null and b/source/_static/images/pcie-host/pcie-controller.jpg differ diff --git a/source/_static/images/pcie-host/pcie-controller_front_callouts.png b/source/_static/images/pcie-host/pcie-controller_front_callouts.png new file mode 100644 index 00000000..41819724 Binary files /dev/null and b/source/_static/images/pcie-host/pcie-controller_front_callouts.png differ diff --git a/source/_static/images/pcie-host/pcie-controller_front_callouts.svg b/source/_static/images/pcie-host/pcie-controller_front_callouts.svg new file mode 100644 index 00000000..36bb7703 --- /dev/null +++ b/source/_static/images/pcie-host/pcie-controller_front_callouts.svg @@ -0,0 +1,216 @@ + + + +UnusedClock 0InputAuxiliary analog& digital IOONIXHeadstagePort AONIXHeadstagePort BONIXClock 2OutputHarpClock 1Input diff --git a/source/_static/images/pcie-host/pcie-host_nereid_fmc-host-1r4.jpg b/source/_static/images/pcie-host/pcie-host_nereid_fmc-host-1r4.jpg deleted file mode 100644 index 4f83fd03..00000000 Binary files a/source/_static/images/pcie-host/pcie-host_nereid_fmc-host-1r4.jpg and /dev/null differ diff --git a/source/index.rst b/source/index.rst index 93d63465..518faa12 100644 --- a/source/index.rst +++ b/source/index.rst @@ -21,7 +21,7 @@ **ONIX** is a collection of `Open Neuro Interface `_-compliant hardware and software for performing neuroscience experiments with freely moving animals. It is the successor to the original `Open Ephys `__ -`Acquisition System `_ and +`Acquisition Board `_ and significantly expands on its scope, performance, and compatibility with other tools.