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Fix Kill_S signal #153

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Fix Kill_S signal #153

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a3c744b
fixed Kill_SI signal in div_sqrt_top_mvp
Aug 18, 2025
388d835
move to correct path
Aug 18, 2025
e0b39a5
set space
Aug 18, 2025
c7a210b
make kill_si signal synthesizable
Aug 18, 2025
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8 changes: 7 additions & 1 deletion src/fpnew_divsqrt_multi.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -293,6 +293,12 @@ module fpnew_divsqrt_multi #(
fpnew_pkg::status_t unit_status, held_status_q;
logic hold_en;

`ifndef SYNTHESIS
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I would recommend the industry-standard //synopsys translate_on and //synopsys translate_off pragmas. Virtually all commercial synthesis tools recognise these and it avoids using yet-another Verilog macro.

assign Kill_SI_pulp = (flush_i === 1'b1) || (reg_ena_i[NUM_INP_REGS-1] === 1'b1);
`else
assign Kill_SI_pulp = flush_i || reg_ena_i[NUM_INP_REGS-1];
`endif

div_sqrt_top_mvp i_divsqrt_lei (
.Clk_CI ( clk_i ),
.Rst_RBI ( rst_ni ),
Expand All @@ -303,7 +309,7 @@ module fpnew_divsqrt_multi #(
.RM_SI ( rnd_mode_q ),
.Precision_ctl_SI ( '0 ),
.Format_sel_SI ( divsqrt_fmt ),
.Kill_SI ( flush_i | reg_ena_i[NUM_INP_REGS-1] ),
.Kill_SI ( Kill_SI_pulp ),
.Result_DO ( unit_result ),
.Fflags_SO ( unit_status ),
.Ready_SO ( unit_ready ),
Expand Down