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ACWright256ACWright256
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Merge branch 'openhwgroup:main' into main
2 parents 79031e3 + 0ad5165 commit 667c54c

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‎sim/coverage-exclusions-rv64gc.do‎

Lines changed: 73 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -77,7 +77,7 @@ for {set i 0} {$i < $numcacheways} {incr i} {
7777
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetDirtyWay"] -item e 1
7878
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SelectedWiteWordEn"] -item e 1 -fecexprrow 4 6
7979
# below: flushD can't go high during an icache write b/c of pipeline stall
80-
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: icache SetValidEN"] -item e 1 -fecexprrow 4
80+
coverage exclude -scope /dut/core/ifu/bus/icache/icache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
8181
}
8282

8383
## D$ Exclusions.
@@ -88,7 +88,11 @@ coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [Get
8888
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -linerange [GetLineNum ../src/cache/cachefsm.sv "exclusion-tag: cache AnyMiss"] -item e 1 -fecexprrow 4
8989
set numcacheways 4
9090
for {set i 0} {$i < $numcacheways} {incr i} {
91-
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item be 1 -fecexprrow 4
91+
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: dcache invalidateway"] -item bes 1 -fecexprrow 4
92+
93+
# FlushStage=1 will never happen when SetValidWay=1 since a pipeline stall is asserted by the cache in the fetch stage, which happens before
94+
# going into the WRITE_LINE state (and asserting SetValidWay). No TrapM can fire and since StallW is high, a stallM caused by WFIStallM would not cause a flushW.
95+
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/CacheWays[$i] -linerange [GetLineNum ../src/cache/cacheway.sv "exclusion-tag: cache SetValidEN"] -item e 1 -fecexprrow 4
9296
}
9397
# D$ writeback, flush, write_line, or flush_writeback states can't be cancelled by a flush
9498
coverage exclude -scope /dut/core/lsu/bus/dcache/dcache/cachefsm -ftrans CurrState STATE_WRITEBACK->STATE_READY STATE_FLUSH->STATE_READY STATE_WRITE_LINE->STATE_READY STATE_FLUSH_WRITEBACK->STATE_READY
@@ -115,20 +119,85 @@ coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/clintdec -lin
115119
set line [GetLineNum ../src/mmu/adrdec.sv "& SizeValid"]
116120
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker/adrdecs/uncoreramdec -linerange $line-$line -item e 1 -fecexprrow 5
117121

118-
# Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccess' will never be 1
122+
## Excluding signals in lsu: the lsu never executes instructions so 'ExecuteAccessF' will never be 1
123+
# in pmachecker.sv
119124
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX ="]
120125
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 6
121126
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
122127
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 4
128+
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
129+
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2
130+
131+
# in mmu.sv
132+
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
133+
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2
134+
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
135+
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
136+
set line [GetLineNum ../src/mmu/mmu.sv "PMAInstrAccessFaultF \\|"]
137+
coverage exclude -scope /dut/core/lsu/dmmu/dmmu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
138+
139+
# in pmpchecker.sv
140+
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ExecuteAccessF"]
141+
coverage exclude -scope /dut/core/lsu/dmmu/dmmu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
123142

124-
# Excluding ReadAccess and WriteAccess signal in the ifu that will never be true
143+
144+
## Excluding ReadAccessM_1 and WriteAccessM_1 signals in the ifu pmachecker, mmu, pmpchecker because they will never be high
145+
## and Excluding ExecuteAccessF_0 because it is always true/high in the ifu
146+
# in pmachecker.sv
125147
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| WriteAccessM"]
126148
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2 4
127149
set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM \\| ExecuteAccessF"]
128150
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-5
129151
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM \\| ExecuteAccessF"]
130152
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1-3
131153

154+
set line [GetLineNum ../src/mmu/pmachecker.sv "ExecuteAccessF & PMAAccessFault"]
155+
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 1
156+
set line [GetLineNum ../src/mmu/pmachecker.sv "ReadAccessM & PMAAccessFault"]
157+
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
158+
set line [GetLineNum ../src/mmu/pmachecker.sv "WriteAccessM & PMAAccessFault"]
159+
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 2-4
160+
set line [GetLineNum ../src/mmu/pmachecker.sv "AccessRWX \\| AtomicAccessM"]
161+
coverage exclude -scope /dut/core/ifu/immu/immu/pmachecker -linerange $line-$line -item e 1 -fecexprrow 3
162+
163+
# in mmu.sv
164+
set line [GetLineNum ../src/mmu/mmu.sv "ExecuteAccessF \\| ReadAccessM"]
165+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,3,4
166+
set line [GetLineNum ../src/mmu/mmu.sv "ReadAccessM & ~WriteAccessM"]
167+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2-4
168+
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & WriteAccessM"]
169+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
170+
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ExecuteAccessF"]
171+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 3
172+
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & ReadNoAmoAccessM"]
173+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
174+
set line [GetLineNum ../src/mmu/mmu.sv "TLBPageFault & WriteAccessM"]
175+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
176+
set line [GetLineNum ../src/mmu/mmu.sv "DataMisalignedM & ReadNoAmoAccessM"]
177+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 1,2,4
178+
179+
# in pmpchecker.sv
180+
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & WriteAccessM"]
181+
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
182+
set line [GetLineNum ../src/mmu/pmpchecker.sv "EnforcePMP & ReadAccessM"]
183+
coverage exclude -scope /dut/core/ifu/immu/immu/pmp/pmpchecker -linerange $line-$line -item e 1 -fecexprrow 1,2,4,5,6
184+
185+
## Executing any LoadAccess or StoreAccess signal in the ifu - depend on Read and Write Access that the ifu will never have
186+
# in /mmu/mmu.sv
187+
set line [GetLineNum ../src/mmu/mmu.sv "PMALoadAccessFaultM \\| PMPLoadAccessFaultM"]
188+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
189+
set line [GetLineNum ../src/mmu/mmu.sv "PMAStoreAmoAccessFaultM \\| PMPStoreAmoAccessFaultM"]
190+
coverage exclude -scope /dut/core/ifu/immu/immu -linerange $line-$line -item e 1 -fecexprrow 2,4,5,6
191+
192+
## Excluding ReadAccess_0, WriteAcess_1 in the TLB because the itlb only reads, and does not write
193+
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "ReadAccess \\| WriteAccess"]
194+
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 1,3,4
195+
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "CAMHit & TLBAccess"]
196+
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
197+
set line [GetLineNum ../src/mmu/tlb/tlbcontrol.sv "~CAMHit & TLBAccess"]
198+
coverage exclude -scope /dut/core/ifu/immu/immu/tlb/tlb/tlbcontrol -linerange $line-$line -item e 1 -fecexprrow 3
199+
132200
# Excluding reset and clear for impossible case in the wficountreg in privdec
133201
set line [GetLineNum ../src/generic/flop/floprc.sv "reset \\| clear"]
134202
coverage exclude -scope /dut/core/priv/priv/pmd/wfi/wficountreg -linerange $line-$line -item c 1 -feccondrow 2
203+

‎src/cache/cacheway.sv‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -82,6 +82,8 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
8282
mux2 #(1) seltagmux(VictimWay, FlushWay, SelFlush, SelTag);
8383

8484
// FlushWay is part of a one hot way selection. Must clear it if FlushWay not selected.
85+
// coverage off -item e 1 -fecexprrow 3
86+
// nonzero ways will never see SelFlush=0 while FlushWay=1 since FlushWay only advances on a subset of SelFlush assertion cases.
8587
assign FlushWayEn = FlushWay & SelFlush;
8688
assign SelNonHit = FlushWayEn | SetValid | SelWriteback;
8789
end
@@ -100,7 +102,7 @@ module cacheway #(parameter NUMLINES=512, LINELEN = 256, TAGLEN = 26,
100102
assign SetDirtyWay = SetDirty & SelData; // exclusion-tag: icache SetDirtyWay
101103
assign ClearDirtyWay = ClearDirty & SelData;
102104
assign SelectedWriteWordEn = (SetValidWay | SetDirtyWay) & ~FlushStage; // exclusion-tag: icache SelectedWiteWordEn
103-
assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: icache SetValidEN
105+
assign SetValidEN = SetValidWay & ~FlushStage; // exclusion-tag: cache SetValidEN
104106

105107
// If writing the whole line set all write enables to 1, else only set the correct word.
106108
assign FinalByteMask = SetValidWay ? '1 : LineByteMask; // OR

‎src/fpu/unpackinput.sv‎

Lines changed: 2 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -303,8 +303,8 @@ module unpackinput (
303303
assign Man = {ExpNonZero, Frac}; // add the assumed one (or zero if Subnormal or zero) to create the significand
304304
assign NaN = ((ExpMax & ~FracZero)|BadNaNBox)&En; // is the input a NaN?
305305
assign SNaN = NaN&~Frac[`NF-1]&~BadNaNBox; // is the input a singnaling NaN?
306-
assign Inf = ExpMax & FracZero &En & ~BadNaNBox; // is the input infinity?
307-
assign Zero = ~ExpNonZero & FracZero & ~BadNaNBox; // is the input zero?
306+
assign Inf = ExpMax & FracZero & En; // is the input infinity?
307+
assign Zero = ~ExpNonZero & FracZero; // is the input zero?
308308
assign Subnorm = ~ExpNonZero & ~FracZero & ~BadNaNBox; // is the input subnormal
309309

310310
endmodule

‎tests/coverage/pmpcfg.S‎

Lines changed: 21 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,6 +1,6 @@
11
// pmpcfg part 1
22
// Kevin Wan, [email protected], 4/18/2023
3-
// Liam Chalk, [email protected], 4/21/2023
3+
// Liam Chalk, [email protected], 4/25/2023
44
// locks each pmpXcfg bit field in order, from X = 15 to X = 0, with the A[1:0] field set to TOR.
55
// See the next part in pmpcfg1.S
66

@@ -52,6 +52,26 @@ main:
5252
li t0, 0x00001700
5353
csrw pmpcfg3, t0
5454

55+
li t0, 0x90000000
56+
csrw pmpaddr0, t0
57+
li t0, 0x00170000
58+
csrw pmpcfg0, t0
59+
60+
li t0, 0x90000000
61+
csrw pmpaddr2, t0
62+
li t0, 0x00170000
63+
csrw pmpcfg2, t0
64+
65+
li t0, 0x90000000
66+
csrw pmpaddr0, t0
67+
li t0, 0x17000000
68+
csrw pmpcfg0, t0
69+
70+
li t0, 0x90000000
71+
csrw pmpaddr2, t0
72+
li t0, 0x17000000
73+
csrw pmpcfg2, t0
74+
5575
li t0, 0x8800000000000000
5676
csrw pmpcfg2, t0
5777
li t0, 0x88000000000000

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