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davidharrishmcdavidharrishmc
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Merge pull request #282 from ross144/main
Arty A7 board support, ImperasDV linux boot, CVW_v0.9 tag
2 parents 4f6c493 + e72fa0c commit e43de9c

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+2044
-335
lines changed

‎fpga/constraints/artyddr3.ucf‎

Lines changed: 48 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -0,0 +1,48 @@
1+
NET "ddr3_dq[0]" LOC = "K5" | IOSTANDARD = SSTL15 ;
2+
NET "ddr3_dq[1]" LOC = "L3" | IOSTANDARD = SSTL15 ;
3+
NET "ddr3_dq[2]" LOC = "K3" | IOSTANDARD = SSTL15 ;
4+
NET "ddr3_dq[3]" LOC = "L6" | IOSTANDARD = SSTL15 ;
5+
NET "ddr3_dq[4]" LOC = "M3" | IOSTANDARD = SSTL15 ;
6+
NET "ddr3_dq[5]" LOC = "M1" | IOSTANDARD = SSTL15 ;
7+
NET "ddr3_dq[6]" LOC = "L4" | IOSTANDARD = SSTL15 ;
8+
NET "ddr3_dq[7]" LOC = "M2" | IOSTANDARD = SSTL15 ;
9+
NET "ddr3_dq[8]" LOC = "V4" | IOSTANDARD = SSTL15 ;
10+
NET "ddr3_dq[9]" LOC = "T5" | IOSTANDARD = SSTL15 ;
11+
NET "ddr3_dq[10]" LOC = "U4" | IOSTANDARD = SSTL15 ;
12+
NET "ddr3_dq[11]" LOC = "V5" | IOSTANDARD = SSTL15 ;
13+
NET "ddr3_dq[12]" LOC = "V1" | IOSTANDARD = SSTL15 ;
14+
NET "ddr3_dq[13]" LOC = "T3" | IOSTANDARD = SSTL15 ;
15+
NET "ddr3_dq[14]" LOC = "U3" | IOSTANDARD = SSTL15 ;
16+
NET "ddr3_dq[15]" LOC = "R3" | IOSTANDARD = SSTL15 ;
17+
NET "ddr3_dm[0]" LOC = "L1" | IOSTANDARD = SSTL15 ;
18+
NET "ddr3_dm[1]" LOC = "U1" | IOSTANDARD = SSTL15 ;
19+
NET "ddr3_dqs_p[0]" LOC = "N2" | IOSTANDARD = DIFF_SSTL15 ;
20+
NET "ddr3_dqs_n[0]" LOC = "N1" | IOSTANDARD = DIFF_SSTL15 ;
21+
NET "ddr3_dqs_p[1]" LOC = "U2" | IOSTANDARD = DIFF_SSTL15 ;
22+
NET "ddr3_dqs_n[1]" LOC = "V2" | IOSTANDARD = DIFF_SSTL15 ;
23+
NET "ddr3_addr[13]" LOC = "T8" | IOSTANDARD = SSTL15 ;
24+
NET "ddr3_addr[12]" LOC = "T6" | IOSTANDARD = SSTL15 ;
25+
NET "ddr3_addr[11]" LOC = "U6" | IOSTANDARD = SSTL15 ;
26+
NET "ddr3_addr[10]" LOC = "R6" | IOSTANDARD = SSTL15 ;
27+
NET "ddr3_addr[9]" LOC = "V7" | IOSTANDARD = SSTL15 ;
28+
NET "ddr3_addr[8]" LOC = "R8" | IOSTANDARD = SSTL15 ;
29+
NET "ddr3_addr[7]" LOC = "U7" | IOSTANDARD = SSTL15 ;
30+
NET "ddr3_addr[6]" LOC = "V6" | IOSTANDARD = SSTL15 ;
31+
NET "ddr3_addr[5]" LOC = "R7" | IOSTANDARD = SSTL15 ;
32+
NET "ddr3_addr[4]" LOC = "N6" | IOSTANDARD = SSTL15 ;
33+
NET "ddr3_addr[3]" LOC = "T1" | IOSTANDARD = SSTL15 ;
34+
NET "ddr3_addr[2]" LOC = "N4" | IOSTANDARD = SSTL15 ;
35+
NET "ddr3_addr[1]" LOC = "M6" | IOSTANDARD = SSTL15 ;
36+
NET "ddr3_addr[0]" LOC = "R2" | IOSTANDARD = SSTL15 ;
37+
NET "ddr3_ba[2]" LOC = "P2" | IOSTANDARD = SSTL15 ;
38+
NET "ddr3_ba[1]" LOC = "P4" | IOSTANDARD = SSTL15 ;
39+
NET "ddr3_ba[0]" LOC = "R1" | IOSTANDARD = SSTL15 ;
40+
NET "ddr3_ck_p[0]" LOC = "U9" | IOSTANDARD = DIFF_SSTL15 ;
41+
NET "ddr3_ck_n[0]" LOC = "V9" | IOSTANDARD = DIFF_SSTL15 ;
42+
NET "ddr3_ras_n" LOC = "P3" | IOSTANDARD = SSTL15 ;
43+
NET "ddr3_cas_n" LOC = "M4" | IOSTANDARD = SSTL15 ;
44+
NET "ddr3_we_n" LOC = "P5" | IOSTANDARD = SSTL15 ;
45+
NET "ddr3_reset_n" LOC = "K6" | IOSTANDARD = LVCMOS15 ;
46+
NET "ddr3_cke[0]" LOC = "N5" | IOSTANDARD = SSTL15 ;
47+
NET "ddr3_odt[0]" LOC = "R5" | IOSTANDARD = SSTL15 ;
48+
NET "ddr3_cs_n[0]" LOC = "U8" | IOSTANDARD = SSTL15 ;

‎fpga/constraints/constraints-artyA7.xdc‎ renamed to ‎fpga/constraints/constraints-ArtyA7.xdc‎

Lines changed: 45 additions & 77 deletions
Original file line numberDiff line numberDiff line change
@@ -1,21 +1,25 @@
11
# The main clocks are all autogenerated by the Xilinx IP
2-
# mmcm_clkout1 is the 22Mhz clock from the DDR4 IP used to drive wally and the AHBLite Bus.
3-
# mmcm_clkout0 is the clock output of the DDR4 memory interface / 4.
4-
# This clock is not used by wally or the AHBLite Bus. However it is used by the AXI BUS on the DD4 IP.
2+
# clk_out3_xlnx_mmcm is the 20Mhz clock from the mmcm used to drive wally and the AHB Bus.
3+
# mmcm_clkout0 is the clock output of the DDR3 memory interface / 4.
4+
# This clock is not used by wally or the AHB Bus. However it is used by the AXI BUS on the DD3 IP.
55

6-
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 2 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
6+
create_generated_clock -name CLKDiv64_Gen -source [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/I0] -multiply_by 1 -divide_by 1 [get_pins wallypipelinedsoc/uncore.uncore/sdc.SDC/sd_top/slow_clk_divider/clkMux/O]
7+
8+
##### clock #####
9+
set_property PACKAGE_PIN E3 [get_ports {default_100mhz_clk}]
10+
set_property IOSTANDARD LVCMOS33 [get_ports {default_100mhz_clk}]
711

812
##### GPI ####
9-
set_property PACKAGE_PIN D9 [get_ports {GPI[0]}]
13+
set_property PACKAGE_PIN A8 [get_ports {GPI[0]}]
1014
set_property PACKAGE_PIN C9 [get_ports {GPI[1]}]
1115
set_property PACKAGE_PIN B9 [get_ports {GPI[2]}]
1216
set_property PACKAGE_PIN B8 [get_ports {GPI[3]}]
1317
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[3]}]
1418
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[2]}]
1519
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[1]}]
1620
set_property IOSTANDARD LVCMOS33 [get_ports {GPI[0]}]
17-
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports {GPI[*]}]
18-
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports {GPI[*]}]
21+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPI[*]}]
22+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPI[*]}]
1923
set_max_delay -from [get_ports {GPI[*]}] 10.000
2024

2125
##### GPO ####
@@ -24,77 +28,48 @@ set_property PACKAGE_PIN F6 [get_ports {GPO[1]}]
2428
set_property PACKAGE_PIN E1 [get_ports {GPO[2]}]
2529
set_property PACKAGE_PIN G3 [get_ports {GPO[4]}]
2630
set_property PACKAGE_PIN J4 [get_ports {GPO[3]}]
27-
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[4]}]
28-
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[3]}]
29-
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[2]}]
30-
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[1]}]
31-
set_property IOSTANDARD LVCMOS12 [get_ports {GPO[0]}]
31+
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[4]}]
32+
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[3]}]
33+
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[2]}]
34+
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[1]}]
35+
set_property IOSTANDARD LVCMOS33 [get_ports {GPO[0]}]
3236
set_max_delay -to [get_ports {GPO[*]}] 10.000
33-
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {GPO[*]}]
34-
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {GPO[*]}]
37+
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports {GPO[*]}]
38+
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports {GPO[*]}]
3539

3640

3741
##### UART #####
3842
# *** IOSTANDARD is probably wrong
3943
set_property PACKAGE_PIN A9 [get_ports UARTSin]
40-
set_property PACKAGE_PIN D0 [get_ports UARTSout]
41-
set_max_delay -from [get_ports UARTSin] 10.000
42-
set_max_delay -to [get_ports UARTSout] 10.000
44+
set_property PACKAGE_PIN D10 [get_ports UARTSout]
45+
set_max_delay -from [get_ports UARTSin] 14.000
46+
set_max_delay -to [get_ports UARTSout] 14.000
4347
set_property IOSTANDARD LVCMOS33 [get_ports UARTSin]
44-
set_property IOSTANDARD LVCMOS3 [get_ports UARTSout]
45-
set_property DRIVE 6 [get_ports UARTSout]
46-
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports UARTSin]
47-
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports UARTSin]
48-
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports UARTSout]
49-
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports UARTSout]
48+
set_property IOSTANDARD LVCMOS33 [get_ports UARTSout]
49+
set_property DRIVE 4 [get_ports UARTSout]
50+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSin]
51+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSin]
52+
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 0.000 [get_ports UARTSout]
53+
set_output_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 0.000 [get_ports UARTSout]
5054

5155

5256
##### reset #####
5357
#************** reset is inverted
54-
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -min -add_delay 2.000 [get_ports reset]
55-
set_input_delay -clock [get_clocks default_250mhz_clk1_0_p] -max -add_delay 2.000 [get_ports reset]
56-
set_input_delay -clock [get_clocks mmcm_clkout0] -min -add_delay 0.000 [get_ports reset]
57-
set_input_delay -clock [get_clocks mmcm_clkout0] -max -add_delay 0.000 [get_ports reset]
58-
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports reset]
59-
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports reset]
60-
set_max_delay -from [get_ports reset] 15.000
61-
set_false_path -from [get_ports reset]
62-
set_property PACKAGE_PIN C2 [get_ports {reset}]
63-
set_property IOSTANDARD LVCMOS33 [get_ports {reset}]
64-
65-
66-
67-
##### cpu_reset #####
68-
# ***********
69-
set_property PACKAGE_PIN AV36 [get_ports {cpu_reset}]
70-
set_property IOSTANDARD LVCMOS12 [get_ports {cpu_reset}]
71-
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {cpu_reset}]
72-
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {cpu_reset}]
73-
74-
75-
##### calib #####
76-
# **********
77-
set_property PACKAGE_PIN BA37 [get_ports calib]
78-
set_property IOSTANDARD LVCMOS12 [get_ports calib]
79-
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports calib]
80-
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports calib]
81-
set_max_delay -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_ports calib] 50.000
82-
58+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports resetn]
59+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports resetn]
60+
set_max_delay -from [get_ports resetn] 15.000
61+
set_false_path -from [get_ports resetn]
62+
set_property PACKAGE_PIN C2 [get_ports {resetn}]
63+
set_property IOSTANDARD LVCMOS33 [get_ports {resetn}]
8364

84-
##### ahblite_resetn #####
85-
# ***************
86-
set_property PACKAGE_PIN AU37 [get_ports {ahblite_resetn}]
87-
set_property IOSTANDARD LVCMOS12 [get_ports {ahblite_resetn}]
88-
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports {ahblite_resetn}]
89-
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 0.000 [get_ports {ahblite_resetn}]
9065

66+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -min -add_delay 2.000 [get_ports south_reset]
67+
set_input_delay -clock [get_clocks clk_out3_xlnx_mmcm] -max -add_delay 2.000 [get_ports south_reset]
68+
set_max_delay -from [get_ports south_reset] 15.000
69+
set_false_path -from [get_ports south_reset]
70+
set_property PACKAGE_PIN D9 [get_ports {south_reset}]
71+
set_property IOSTANDARD LVCMOS33 [get_ports {south_reset}]
9172

92-
##### south_rst #####
93-
# ***********************
94-
set_property PACKAGE_PIN BE22 [get_ports south_rst]
95-
set_property IOSTANDARD LVCMOS18 [get_ports south_rst]
96-
set_input_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 2.000 [get_ports south_rst]
97-
set_input_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 2.000 [get_ports south_rst]
9873

9974

10075
##### SD Card I/O #####
@@ -103,7 +78,7 @@ set_property PACKAGE_PIN D4 [get_ports {SDCDat[3]}]
10378
set_property PACKAGE_PIN D2 [get_ports {SDCDat[2]}]
10479
set_property PACKAGE_PIN E2 [get_ports {SDCDat[1]}]
10580
set_property PACKAGE_PIN F4 [get_ports {SDCDat[0]}]
106-
set_property PACKAGE_PIN F2 [get_ports SDCCLK]
81+
set_property PACKAGE_PIN F3 [get_ports SDCCLK]
10782
set_property PACKAGE_PIN D3 [get_ports {SDCCmd}]
10883

10984
set_property IOSTANDARD LVCMOS33 [get_ports {SDCDat[3]}]
@@ -132,8 +107,8 @@ set_output_delay -clock [get_clocks CLKDiv64_Gen] -max -add_delay 6.000 [get_por
132107
set_output_delay -clock [get_clocks CLKDiv64_Gen] 0.000 [get_ports SDCCLK]
133108

134109
# *********************************
135-
set_property DCI_CASCADE {64} [get_iobanks 65]
136-
set_property INTERNAL_VREF 0.9 [get_iobanks 65]
110+
#set_property DCI_CASCADE {64} [get_iobanks 65]
111+
#set_property INTERNAL_VREF 0.9 [get_iobanks 65]
137112

138113
# ddr3
139114

@@ -237,15 +212,8 @@ set_properity PACKAGE_PIN R5 [get_ports ddr3_odt[0]]
237212
set_properity PACKAGE_PIN U8 [get_ports ddr3_cs_n[0]]
238213

239214

240-
241-
set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 10.000
242-
243-
244-
set_output_delay -clock [get_clocks mmcm_clkout1] -min -add_delay 0.000 [get_ports c0_ddr4_reset_n]
245-
set_output_delay -clock [get_clocks mmcm_clkout1] -max -add_delay 20.000 [get_ports c0_ddr4_reset_n]
246-
247-
248-
249-
set_max_delay -from [get_pins {xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/cal_RESET_n_reg[0]/C}] -to [get_ports c0_ddr4_reset_n] 50.000
215+
# **** may have to bring this one back
216+
#set_max_delay -datapath_only -from [get_pins xlnx_ddr4_c0/inst/u_ddr4_mem_intfc/u_ddr_cal_top/calDone_gated_reg/C] -to [get_pins xlnx_proc_sys_reset_0/U0/EXT_LPF/lpf_int_reg/D] 20.000
250217

251218

219+
set_property CLOCK_DEDICATED_ROUTE ANY_CMT_COLUMN [get_nets wallypipelinedsoc/uncore.uncore/sdc.SDC/clockgater/CLK]

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