From d651315bb1c1b162b0850a3bae941451292b43ab Mon Sep 17 00:00:00 2001 From: "Matwey V. Kornilov" Date: Sat, 4 Aug 2018 19:10:36 +0300 Subject: [PATCH 1/3] Fix output build name Makefile expects to see ov3.bin but it is top.bin instead. --- software/fpga/ov3/Makefile | 2 +- software/fpga/ov3/build.py | 10 ++++++---- 2 files changed, 7 insertions(+), 5 deletions(-) diff --git a/software/fpga/ov3/Makefile b/software/fpga/ov3/Makefile index 7282ab1..f2a56f1 100644 --- a/software/fpga/ov3/Makefile +++ b/software/fpga/ov3/Makefile @@ -15,7 +15,7 @@ $(FWPKG): $(BITFILE) $(PYTHON) -m zipfile -c $@ $< $(BUILD)/map.txt $(BITFILE): $(PY_FILES) - $(PYTHON) build.py build_dir $(BUILD) build_name ov3 + $(PYTHON) build.py $(BUILD) ov3 clean: rm -rf $(BUILD)/* diff --git a/software/fpga/ov3/build.py b/software/fpga/ov3/build.py index 9b62665..9e7e9c6 100644 --- a/software/fpga/ov3/build.py +++ b/software/fpga/ov3/build.py @@ -21,11 +21,13 @@ def gen_mapfile(ov3_mod): return r if __name__ == "__main__": + import sys + plat = Platform() top = OV3(plat) - # Build the register map - # FIXME: build dir should come from command line arg - open("build/map.txt", "w").write(gen_mapfile(top)) + _, build_dir, build_name = sys.argv + + open("{}/map.txt".format(build_dir), "w").write(gen_mapfile(top)) - plat.build(top) + plat.build(top, build_dir=build_dir, build_name=build_name) From 0ffe58f453fe70e08786f64027f241f3a6c0c96c Mon Sep 17 00:00:00 2001 From: "Matwey V. Kornilov" Date: Sat, 16 Sep 2017 18:25:30 +0300 Subject: [PATCH 2/3] Reset FIFO in sdram_sink and sdram_host_read (cherry picked from commit eafc790d336e05498c46c03e9743c462c156f20e) --- software/fpga/ov3/ovhw/sdram_host_read.py | 5 ++++- software/fpga/ov3/ovhw/sdram_sink.py | 5 ++++- 2 files changed, 8 insertions(+), 2 deletions(-) diff --git a/software/fpga/ov3/ovhw/sdram_host_read.py b/software/fpga/ov3/ovhw/sdram_host_read.py index 5100fa8..3733faa 100644 --- a/software/fpga/ov3/ovhw/sdram_host_read.py +++ b/software/fpga/ov3/ovhw/sdram_host_read.py @@ -1,4 +1,5 @@ from migen import * +from migen.fhdl.decorators import ResetInserter from migen.genlib.fsm import FSM, NextState from migen.genlib.fifo import SyncFIFO from misoc.interconnect.csr import AutoCSR, CSRStorage, CSRStatus @@ -79,7 +80,7 @@ def __init__(self, hostif, host_burst_length = 16): self.submodules.sdram_read_fsm = FSM() - sdram_fifo = SyncFIFO(width, host_burst_length) + sdram_fifo = ResetInserter()(SyncFIFO(width, host_burst_length)) self.submodules += sdram_fifo # we always read (never write) @@ -137,6 +138,8 @@ def __init__(self, hostif, host_burst_length = 16): rptr_next = Signal(awidth) self.comb += If(wrap, rptr_next.eq(self._ring_base.storage)).Else(rptr_next.eq(self.rptr + 1)) + self.sync += sdram_fifo.reset.eq(go &~ gor) + self.sync += \ If(go &~ gor, rptr.eq(self._ring_base.storage), diff --git a/software/fpga/ov3/ovhw/sdram_sink.py b/software/fpga/ov3/ovhw/sdram_sink.py index d371c7f..458b225 100644 --- a/software/fpga/ov3/ovhw/sdram_sink.py +++ b/software/fpga/ov3/ovhw/sdram_sink.py @@ -1,4 +1,5 @@ from migen import * +from migen.fhdl.decorators import ResetInserter from migen.genlib.fsm import FSM, NextState from migen.genlib.fifo import SyncFIFO from misoc.interconnect.csr import AutoCSR, CSRStatus, CSRStorage @@ -16,7 +17,7 @@ def __init__(self, hostif, max_burst_length = 256): self.sink = Endpoint([('d', 8), ('last', 1)]) - self.submodules.sdram_fifo = SyncFIFO(width, max_burst_length) + self.submodules.sdram_fifo = ResetInserter()(SyncFIFO(width, max_burst_length)) self.submodules.fifo_write_fsm = FSM() @@ -138,6 +139,8 @@ def __init__(self, hostif, max_burst_length = 256): # wrap around counter self.comb += If(wrap & hostif.d_stb &~ hostif.d_term, self._wrap_count.inc()) + self.sync += self.sdram_fifo.reset.eq(go &~ gor) + # update wptr self.sync += If(go &~ gor, self.wptr.eq(self._ring_base.storage), From 9000c41fe730a5882dfa07bdc1ed76e5d6c56573 Mon Sep 17 00:00:00 2001 From: "Matwey V. Kornilov" Date: Mon, 20 Aug 2018 10:22:19 +0300 Subject: [PATCH 3/3] Return fifo_fsm to initial state when disabled --- software/fpga/ov3/ovhw/sdram_sink.py | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-) diff --git a/software/fpga/ov3/ovhw/sdram_sink.py b/software/fpga/ov3/ovhw/sdram_sink.py index 458b225..86e237a 100644 --- a/software/fpga/ov3/ovhw/sdram_sink.py +++ b/software/fpga/ov3/ovhw/sdram_sink.py @@ -150,7 +150,9 @@ def __init__(self, hostif, max_burst_length = 256): # sink into fifo - self.submodules.fifo_fsm = FSM() + self.submodules.fifo_fsm = ResetInserter()(FSM()) + + self.sync += self.fifo_fsm.reset.eq(go &~ gor) capture_low = Signal() din_low = Signal(8)