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I noticed that the Gray code counter gc_FP_ATTR is intentionally not reset:
// 2 bit gray counter, it must NEVER be resetlogic [1:0] gc_FP_ATTR ='0;
This makes sense in the context of CDC synchronization — resetting the counter could cause a spurious strobe in the clk2 domain due to mismatch or metastability.
That said, some users (especially targeting ASICs or formal tools) might be surprised by the absence of a reset or the reliance on simulation-only initial values (gc_FP_ATTR = '0).
Would it make sense to:
Add a comment clarifying that the counter should not be reset to prevent CDC issues?
Note that this design may not be portable to ASIC synthesis without further careful handling of initial values?
Thanks again for the great work — and for the detailed comments throughout the code!