diff --git a/.github/workflows/floogen.yml b/.github/workflows/floogen.yml index ab7b0bcf7..7d2cdd33c 100644 --- a/.github/workflows/floogen.yml +++ b/.github/workflows/floogen.yml @@ -11,13 +11,14 @@ on: push: branches: - main + - develop jobs: - unit-test: + unit-test-pip: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 + - uses: actions/checkout@v5 - name: Set up Python uses: actions/setup-python@v5 with: @@ -26,6 +27,26 @@ jobs: run: | python -m pip install --upgrade pip python -m pip install . + python -m pip install --group dev - name: Run unit tests run: | python -m pytest -v + + unit-test-uv: + runs-on: ubuntu-latest + steps: + - uses: actions/checkout@v5 + + - name: Set up Python + uses: actions/setup-python@v5 + with: + python-version: '3.10' + + - name: Install uv + uses: astral-sh/setup-uv@v6 + + - name: Sync project + dev group + run: uv sync --locked --group dev + + - name: Run unit tests + run: uv run -m pytest -v diff --git a/.github/workflows/gitlab-ci.yml b/.github/workflows/gitlab-ci.yml index e90268274..47d141189 100644 --- a/.github/workflows/gitlab-ci.yml +++ b/.github/workflows/gitlab-ci.yml @@ -11,6 +11,7 @@ on: push: branches: - main + - develop jobs: check: diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index bcecbb8d2..ca2b76bf8 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -11,6 +11,7 @@ on: push: branches: - main + - develop jobs: @@ -40,25 +41,14 @@ jobs: fail_on_error: true reviewdog_reporter: github-check - ########## - # PyLint # - ########## - pylint: + ######## + # Ruff # + ######## + ruff: runs-on: ubuntu-latest steps: - - uses: actions/checkout@v4 - - name: Set up Python - uses: actions/setup-python@v5 - with: - python-version: '3.10' - cache: 'pip' - - name: Install dependencies and package - run: | - python -m pip install --upgrade pip - pip install . - - name: Analysing the code with pylint - run: | - pylint $(git ls-files '*.py') + - uses: actions/checkout@v4 + - uses: astral-sh/ruff-action@v3 ################# # Check License # diff --git a/.github/workflows/publish-docs.yml b/.github/workflows/publish-docs.yml new file mode 100644 index 000000000..6c3c56374 --- /dev/null +++ b/.github/workflows/publish-docs.yml @@ -0,0 +1,32 @@ +# Copyright 2024 ETH Zurich and University of Bologna. +# Licensed under the Apache License, Version 2.0, see LICENSE for details. +# SPDX-License-Identifier: Apache-2.0 + +# Author: Tim Fischer + +name: publish-docs + +on: + push: + branches: + - main + workflow_dispatch: + +jobs: + + deploy: + runs-on: ubuntu-22.04 + steps: + - name: Checkout + uses: actions/checkout@v4 + with: + fetch-depth: 0 + - name: Install Python + uses: actions/setup-python@v5 + with: + python-version: '3.10' + cache: pip + - name: Install Python requirements + run: pip install .[docs] + - name: Deploy Documentation + run: mkdocs gh-deploy --force diff --git a/.gitignore b/.gitignore index 397ff3cc5..c8a3efcc8 100644 --- a/.gitignore +++ b/.gitignore @@ -48,6 +48,7 @@ docs/_rst/* docs/_build/* cover/* MANIFEST +site # Per-project virtualenvs .venv*/ @@ -68,6 +69,7 @@ hw/test/jobs # QuestaSim work +work_* work-vsim modelsim.ini transcript @@ -95,3 +97,6 @@ measurements *.csv **/*.log reviewdog + +# Physical design repository +pd diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 2682c4e65..87bb9f89c 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -2,12 +2,14 @@ # Solderpad Hardware License, Version 0.51, see LICENSE for details. # SPDX-License-Identifier: SHL-0.51 +# Author: Tim Fischer # Author: Michael Rogenmoser variables: - VSIM: questa-2023.4 vsim + QUESTA_SEPP: questa-2025.1 + VCS_SEPP: vcs-2025.06 BENDER: bender - PYTHON: /usr/local/anaconda3/bin/python + UV: /home/fischeti/.local/bin/uv stages: - init @@ -63,12 +65,7 @@ compile-meshes: - DUT: [axi_mesh, nw_mesh] ROUTE_ALGO: [xy, src, id] script: - # Install `floogen` - - $PYTHON -m venv .venv - - source .venv/bin/activate - - pip install . - # Generate sources - - floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format + - $UV run floogen -c floogen/examples/${DUT}_${ROUTE_ALGO}.yml -o generated --no-format # Compile the network - make compile-sim EXTRA_BENDER_FLAGS="-t ${DUT}" WORK="work_${DUT}_${ROUTE_ALGO}" | tee compile.log 2>&1 - '! grep "\*\* Error" compile.log' @@ -125,3 +122,25 @@ morty: script: - $BENDER sources -f > source_list.txt - morty -f source_list.txt + +################### +# Physical Design # +################### + +init-pd: + stage: init + script: + - make init-pd + artifacts: + paths: + - pd/ci.yml + +subpipe: + stage: build + needs: + - init-pd + trigger: + include: + - artifact: pd/ci.yml + job: init-pd + strategy: depend diff --git a/Bender.lock b/Bender.lock index b9527629b..e72f22b04 100644 --- a/Bender.lock +++ b/Bender.lock @@ -7,8 +7,8 @@ packages: dependencies: - common_cells axi: - revision: 9402c8a9ce0a7b5253c3c29e788612d771e8b5d6 - version: 0.39.3 + revision: 78831b6feba265d5ee2683bbf42b4150f8a35c43 + version: 0.39.8 source: Git: https://github.com/pulp-platform/axi.git dependencies: @@ -32,22 +32,28 @@ packages: dependencies: - common_cells common_cells: - revision: 0d67563b6b592549542544f1abc0f43e5d4ee8b4 - version: 1.35.0 + revision: 1d5c6fc3da60f0a920a5113b143624770bc1a279 + version: null source: Git: https://github.com/pulp-platform/common_cells.git dependencies: - common_verification - tech_cells_generic common_verification: - revision: 9c07fa860593b2caabd9b5681740c25fac04b878 - version: 0.2.3 + revision: fb1885f48ea46164a10568aeff51884389f67ae3 + version: 0.2.5 source: Git: https://github.com/pulp-platform/common_verification.git dependencies: [] + floo_noc_pd: + revision: null + version: null + source: + Path: pd + dependencies: [] idma: - revision: 95f366e56f7e772c283fb3c8b343afc4a3978375 - version: 0.6.2 + revision: 28a36e5e07705549e59fc33db96ab681bc1ca88e + version: 0.6.5 source: Git: https://github.com/pulp-platform/iDMA.git dependencies: @@ -58,16 +64,16 @@ packages: - obi - register_interface obi: - revision: 1aa411df145c4ebdd61f8fed4d003c33f7b20636 - version: 0.1.2 + revision: 0155fc34e900c7c884e081c0a1114a247937ff69 + version: 0.1.7 source: Git: https://github.com/pulp-platform/obi.git dependencies: - common_cells - common_verification register_interface: - revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d - version: 0.4.4 + revision: 8e8c209ea559d3b54f45cf30fcce95ce70ff5e49 + version: 0.4.6 source: Git: https://github.com/pulp-platform/register_interface.git dependencies: diff --git a/Bender.yml b/Bender.yml index 99a73cefb..c7832f795 100644 --- a/Bender.yml +++ b/Bender.yml @@ -7,13 +7,15 @@ package: authors: - "Michael Rogenmoser " - "Tim Fischer " + - "Lorenzo leone " dependencies: idma: { git: "https://github.com/pulp-platform/iDMA.git", version: 0.6.2 } - common_cells: { git: "https://github.com/pulp-platform/common_cells.git", version: 1.35.0 } + common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: "master" } # Revert to a versioned release once available common_verification: { git: "https://github.com/pulp-platform/common_verification.git", version: 0.2.3 } - axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.3 } + axi: { git: "https://github.com/pulp-platform/axi.git", version: 0.39.7 } axi_riscv_atomics: { git: "https://github.com/pulp-platform/axi_riscv_atomics.git", version: 0.8.2 } + floo_noc_pd: {path: ./pd} export_include_dirs: - hw/include @@ -26,19 +28,27 @@ sources: - hw/floo_fifo.sv - hw/floo_cdc.sv - hw/floo_route_select.sv - - hw/floo_route_comp.sv + - hw/floo_id_translation.sv - hw/floo_vc_arbiter.sv - hw/floo_wormhole_arbiter.sv - hw/floo_simple_rob.sv - hw/floo_rob.sv - hw/floo_rob_wrapper.sv - - hw/floo_meta_buffer.sv + - hw/floo_reduction_sync.sv + - hw/floo_route_xymask.sv # Level 2 + - hw/floo_route_select.sv + - hw/floo_route_comp.sv + - hw/floo_meta_buffer.sv + - hw/floo_reduction_arbiter.sv + # Level 3 + - hw/floo_output_arbiter.sv + # Level 4 - hw/floo_nw_join.sv - hw/floo_axi_chimney.sv - hw/floo_nw_chimney.sv - hw/floo_router.sv - # Level 3 (Wrappers) + # Level 5 (Wrappers) - hw/floo_axi_router.sv - hw/floo_nw_router.sv @@ -70,6 +80,7 @@ sources: - hw/test/floo_axi_rand_slave.sv - hw/test/floo_dma_test_node.sv - hw/test/axi_reorder_compare.sv + - hw/test/axi_reorder_compare_multicast.sv - hw/test/axi_reorder_remap_compare.sv - hw/test/axi_bw_monitor.sv - hw/test/floo_hbm_model.sv @@ -80,19 +91,36 @@ sources: - hw/tb/tb_floo_router.sv - hw/tb/tb_floo_rob.sv - hw/tb/tb_floo_vc_router.sv + - hw/tb/tb_floo_rob_multicast.sv + + - target: all(any(floo_test, floo_synth), axi_mesh) + files: + - generated/floo_axi_mesh_noc_pkg.sv + - generated/floo_axi_mesh_noc.sv - target: all(floo_test, axi_mesh) include_dirs: - hw/test/include files: - - generated/floo_axi_mesh_noc_pkg.sv - - generated/floo_axi_mesh_noc.sv - hw/tb/tb_floo_axi_mesh.sv + - target: all(any(floo_test, floo_synth), nw_mesh) + files: + - generated/floo_nw_mesh_noc_pkg.sv + - generated/floo_nw_mesh_noc.sv + - target: all(floo_test, nw_mesh) include_dirs: - hw/test/include files: - - generated/floo_nw_mesh_noc_pkg.sv - - generated/floo_nw_mesh_noc.sv - hw/tb/tb_floo_nw_mesh.sv + + - target: all(floo_synth, synthesis) + files: + # Level 0 + - hw/synth/floo_synth_params_pkg.sv + # Level 1 + - hw/synth/floo_synth_axi_chimney.sv + - hw/synth/floo_synth_nw_chimney.sv + - hw/synth/floo_synth_axi_router.sv + - hw/synth/floo_synth_nw_router.sv diff --git a/Makefile b/Makefile index 2b00fbe5c..b4632299c 100644 --- a/Makefile +++ b/Makefile @@ -9,8 +9,7 @@ # Common # ########## -MKFILE_PATH := $(abspath $(lastword $(MAKEFILE_LIST))) -MKFILE_DIR := $(dir $(MKFILE_PATH)) +FLOO_ROOT ?= $(shell pwd) .PHONY: all clean compile-sim run-sim run-sim-batch all: compile-sim @@ -23,12 +22,15 @@ run-sim-batch: run-vsim-batch # Programs # ############ +QUESTA_SEPP ?= +VCS_SEPP ?= + BENDER ?= bender -VSIM ?= questa-2023.4 vsim +VSIM ?= $(QUESTA_SEPP) vsim SPYGLASS ?= sg_shell VERIBLE_FMT ?= verible-verilog-format -VCS ?= vcs-2022.06 vcs -VLOGAN ?= vcs-2022.06 vlogan +VCS ?= $(VCS_SEPP) vcs +VLOGAN ?= $(VCS_SEPP) vlogan ##################### # Compilation Flags # @@ -91,10 +93,10 @@ endif ########### FLOOGEN ?= floogen -FLOO_CFG_DIR ?= $(MKFILE_DIR)floogen/examples -FLOOGEN_CFG ?= $(FLOO_CFG_DIR)/single_cluster.yml +FLOO_CFG_DIR ?= $(FLOO_ROOT)floogen/examples +FLOOGEN_CFG ?= $(FLOO_CFG_DIR)/axi_mesh_xy.yml -FLOOGEN_OUT_DIR ?= $(MKFILE_DIR)generated +FLOOGEN_OUT_DIR ?= $(FLOO_ROOT)generated .PHONY: install-floogen pkg-sources sources clean-sources @@ -210,3 +212,19 @@ clean-spyglass: rm -rf spyglass/floo_noc* rm -f spyglass/sg_shell_command.log rm -f spyglass/set_top.tcl + +################### +# Physical Design # +################### + +PD_REMOTE ?= git@iis-git.ee.ethz.ch:axi-noc/floo_noc_pd.git +PD_BRANCH ?= master +PD_DIR = $(FLOO_ROOT)/pd + +.PHONY: init-pd + +init-pd: + rm -rf $(PD_DIR) + git clone $(PD_REMOTE) $(PD_DIR) -b $(PD_BRANCH) + +-include $(PD_DIR)/pd.mk diff --git a/README.md b/README.md index b9f880157..7492b1a0e 100644 --- a/README.md +++ b/README.md @@ -9,7 +9,7 @@ Logo -This repository provides modules for the FlooNoC, a Network-on-Chip (NoC) which is part of the [PULP (Parallel Ultra-Low Power) Platform](https://pulp-platform.org/). The repository includes Network Interface IPs (named chimneys), Routers and further NoC components to build a complete NoC. FlooNoC mainly supports [AXI4+ATOPs](https://github.com/pulp-platform/axi/tree/master), but can be easily extended to other On-Chip protocols. Arbitrary topologies are supported with several routing algorithms. FlooNoC is designed to be scalable and modular, and can be easily extended with new components. Additionally, FlooNoC provides a generation framework for creating customized NoC configurations. +_FlooNoC_, is a Network-on-Chip (NoC) research project, which is part of the [PULP (Parallel Ultra-Low Power) Platform](https://pulp-platform.org/). The main idea behind _FlooNoC_ is to provide a scalable high-performance NoC for non-coherent systems. _FlooNoC_ was mainly designed to interface with [AXI4+ATOPs](https://github.com/pulp-platform/axi/tree/master), but can easily be extended to other On-Chip protocols. _FlooNoC_ already provides network interface IPs (named chimneys) for AXI4 protocol, which converts to a custom-link level protocol that provides significantly better scalability than AXI4. _FlooNoC_ also includes protocol-agnostic routers based on the custom link-level protocol to transport payloads. Finally, _FlooNoC_ also include additional NoC components to assemble a complete NoC in a modular fashion. _FlooNoC_ is also highly flexible and supports a wide variety of topologies and routing algorithms. A Network generation framework called _FlooGen_ makes it possible to easily generate entire networks based on a simple configuration file.
@@ -29,13 +29,18 @@ This repository provides modules for the FlooNoC, a Network-on-Chip (NoC) which ## 💡 Design Principles -Our NoC design is grounded in the following key principles: +_FlooNoC_ design is based on the following key principles: + +1. **Full AXI4 Support**: _FlooNoC_ fully supports AXI4+ATOPs from AXI5 as outlined [here](https://github.com/pulp-platform/axi/tree/master), providing a high-bandwidth and latency-tolerant solution. _FlooNoC_ achieves this with full support for bursts and multiple outstanding transactions. + +1. **Decoupled Links and Networks**: _FlooNoC_ uses a link-level protocol that is decoupled from the network-level protocol. This allows us to move the complexity of the network-level protocol into the network interfaces, while deploying low-complexity routers in the network, that enable better scalability than multi-layer AXI networks. + +1. **Wide Physical Channels**: _FlooNoC_ uses wide physical channels to meet the high-bandwidth requirements at network endpoints without being constrained by the operating frequency. In contrast to traditional NoCs which use serialization with header and tail flits to transport a message, _FlooNoC_ avoids any kind of serialization and sends entire messages in a single flit including header and tail information. + +1. **Separation of traffic**: _FlooNoC_ addresses diverse types of traffic that can occur in non-coherent systems, by decoupling multiple links to handle wide, high-bandwidth, burst-based traffic and narrow, latency-sensitive traffic with separate physical channels. + +1. **Modularity:** The _FlooNoC_ architecture is designed with modularity in mind. It includes a set of IPs that can be instantiated together to build a NoC. This approach not only promotes reusability but also facilitates flexibility in designing custom NoCs to cater to a variety of specific system requirements. -1. **Full AXI4 Support**: Our design fully supports AXI4+ATOPs from AXI5 as outlined [here](https://github.com/pulp-platform/axi/tree/master), particularly multiple outstanding burst transactions. It utilizes low-complexity routers and a decoupled link-level protocol to ensure scalability, thereby enabling tolerance to high-latency off-chip accesses. -1. **Decoupled Links and Networks**: We use a link-level protocol that is decoupled from the network-level protocol. This allows us to move the complexity of the network-level protocol into the network interfaces, while deploying low-complexity routers in the network, that enable better scalability. -1. **Wide Physical Channels**: We incorporate wide physical channels in order to meet the high-bandwidth requirements at network endpoints without being constrained by the operating frequency. This is in contrast to the traditional narrow link approach. Further, the NoC avoids any kind of serialization and sends entire messages in a single flit including header and tail information. -1. **Separation of traffic**: Our design acknowledges the diversity in traffic patterns, as it decouples links and networks to handle wide, high-bandwidth, burst-based traffic and narrow, latency-sensitive traffic with separate physical channels. -1. **Modularity:** Our design principles also emphasize modularity. We have developed a set of IPs that can be instantiated together to build a NoC. This approach not only promotes reusability but also facilitates flexibility in designing custom NoCs to cater to a variety of specific system requirements. ## 🔮 Origin of the name diff --git a/docs/Apache-License.md b/docs/Apache-License.md new file mode 120000 index 000000000..965b606f3 --- /dev/null +++ b/docs/Apache-License.md @@ -0,0 +1 @@ +../LICENSE-APACHE \ No newline at end of file diff --git a/docs/CONTRIBUTING.md b/docs/CONTRIBUTING.md new file mode 100644 index 000000000..75cd854cd --- /dev/null +++ b/docs/CONTRIBUTING.md @@ -0,0 +1,3 @@ +# Guide to Contributing + +TODO diff --git a/docs/SHL-License.md b/docs/SHL-License.md new file mode 120000 index 000000000..db811d44f --- /dev/null +++ b/docs/SHL-License.md @@ -0,0 +1 @@ +../LICENSE-SHL \ No newline at end of file diff --git a/docs/changelog.md b/docs/changelog.md new file mode 120000 index 000000000..04c99a55c --- /dev/null +++ b/docs/changelog.md @@ -0,0 +1 @@ +../CHANGELOG.md \ No newline at end of file diff --git a/docs/floogen/cli.md b/docs/floogen/cli.md new file mode 100644 index 000000000..e69de29bb diff --git a/docs/floogen/connections.md b/docs/floogen/connections.md new file mode 100644 index 000000000..e69de29bb diff --git a/docs/floogen/endpoints.md b/docs/floogen/endpoints.md new file mode 100644 index 000000000..e69de29bb diff --git a/docs/floogen/known_issues.md b/docs/floogen/known_issues.md new file mode 100644 index 000000000..e69de29bb diff --git a/docs/floogen/network_types.md b/docs/floogen/network_types.md new file mode 100644 index 000000000..ff9a13164 --- /dev/null +++ b/docs/floogen/network_types.md @@ -0,0 +1,21 @@ +# General information + +The first part of the configuration file contains some general information about the network: + +```yaml +name: my_noc +description: "My first NoC" +network_type: "axi" +``` + +## `name` + +The `name` field specifies the name of the network, which will be used to name the generated files. The example given above will generate the files `floo_my_noc_pkg.sv` and `floo_my_noc_top.sv` which contains the package and the top-level module of the same name. + +## `description` +The `description` field is a short description of the network. It is currently not used by _FlooGen_, and it is currently only for user reference. + +## `network_type` +The `network_type` field specifies the type of network that is being generated. Currently, only two types are supported: +- `axi`: This will generate a network where the endpoints expose a single AXI interface, which is mapped on two physical links `req` and `rsp`. +- `narrow_wide`: This will generate a network where the endpoints expose both a narrow and a wide AXI interface, which are mapped on to three physical links `req`, `rsp`, `wide`. It is still possible to disable the narrow or wide interface on a per-endpoint basis. diff --git a/docs/floogen/overview.md b/docs/floogen/overview.md new file mode 100644 index 000000000..a7249b2d9 --- /dev/null +++ b/docs/floogen/overview.md @@ -0,0 +1,114 @@ +# _FlooGen_: The NoC generation framework for _FlooNoC_ + +_FlooGen_ is the generation framework bundled with _FlooNoC_. Given a network description in YAML (topology, endpoints, routing, etc.), it produces SystemVerilog RTL (routers, interfaces, routing tables, packages) that you can plug into your design. + +## Operation at a glance + +1. **Read YAML config** — users define the network (nodes, links, protocols, endpoints). +2. **Internal graph model & validation** — FlooGen builds a graph representation of your network and checks for errors (e.g. overlapping address regions, invalid port assignments). +3. **Route and address map derivation** — from the graph, routing tables and address maps are computed for routers and endpoints. +4. **Code generation** — produces SystemVerilog modules, a package with types and constants, and optionally a top-level wrapper connecting components. + +## Get started with _FlooGen_ + +To install _FlooGen_, python >= 3.10 is required. _FlooGen_ supports [uv](https://docs.astral.sh/uv/), which is the most convenient way of using _FlooGen_, since it handles all the dependencies and virtual environment automatically. Alternatively, you can also install _FlooGen_ using `pip`. + +=== "uv" + + ```bash + # (Optional) Install uv if you don't have it yet + curl -LsSf https://astral.sh/uv/install.sh | sh + git clone https://github.com/pulp-platform/FlooNoC.git && cd FlooNoC + ``` + +=== "pip" + + ```bash + git clone https://github.com/pulp-platform/FlooNoC.git && cd FlooNoC + # (Optional) Set up virtual environment + python -m venv .venv + source .venv/bin/activate + # Install FlooGen with pip + pip install . + ``` + +You can try out _FlooGen_ by running it with an example configuration file: + +=== "uv" + + ```bash + uv run floogen -c floogen/examples/axi_mesh.yaml -o out + ``` + +=== "pip" + + ```bash + floogen -c floogen/examples/axi_mesh.yaml -o out + ``` + +which will generate two files in the `out/` directory: +- `axi_mesh_pkg.sv`: A SystemVerilog package containing all the types, constants and routing information needed to use the generated NoC. +- `axi_mesh_top.sv`: A top-level module instantiating all routers and network interfaces. The top-level module also requires the package generated above. + +## Minimal example + +Below is a small example configuration file for a 4×4 mesh using XY routing. Each section will be explained in more detail in the following sections: + +1. **[General](network_types.md)**: This section will the general global parameters that are needed to configure the NoC. +1. **[Routing](routing.md)**: This section will explain the routing algorithm configuration. +1. **[Protocols](protocols.md)**: This section will explain how to configure the different protocols that are used by the endpoints that are attached to the NoC. +1. **[Endpoints](endpoints.md)**: This section will explain how to configure the endpoints that are attached to the NoC. +1. **[Routers](routers.md)**: This section will explain how to instantiate the routers that make up the NoC. +1. **[Connections](connections.md)**: This section will explain how to connect the endpoints to the routers. This basically defines the topology of the NoC. + + +```yaml +name: axi_mesh +description: "AXI mesh with XY routing" +network_type: "axi" + +routing: + route_algo: "XY" + use_id_table: true + +protocols: + - name: "axi_in" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 4 + user_width: 1 + - name: "axi_out" + protocol: "AXI4" + data_width: 64 + addr_width: 48 + id_width: 2 + user_width: 1 + +endpoints: + - name: "cluster" + array: [4, 4] + addr_range: + base: 0x0000_0000_0000 + size: 0x0000_0001_0000 + mgr_port_protocol: + - "axi_in" + sbr_port_protocol: + - "axi_out" + +routers: + - name: "router" + array: [4, 4] + degree: 5 + +connections: + - src: "cluster" + dst: "router" + src_range: + - [0, 3] + - [0, 3] + dst_range: + - [0, 3] + - [0, 3] + dst_dir: "Eject" +``` diff --git a/docs/floogen/protocols.md b/docs/floogen/protocols.md new file mode 100644 index 000000000..e69de29bb diff --git a/docs/floogen/routers.md b/docs/floogen/routers.md new file mode 100644 index 000000000..e69de29bb diff --git a/docs/floogen/routing.md b/docs/floogen/routing.md new file mode 100644 index 000000000..e69de29bb diff --git a/docs/floogen/utils.md b/docs/floogen/utils.md new file mode 100644 index 000000000..b95b37173 --- /dev/null +++ b/docs/floogen/utils.md @@ -0,0 +1 @@ +::: floogen.utils diff --git a/docs/getting_started.md b/docs/getting_started.md new file mode 100644 index 000000000..d97baceb1 --- /dev/null +++ b/docs/getting_started.md @@ -0,0 +1,93 @@ +# Getting Started + +## Prerequisites + +### Bender + +_FlooNoC_ uses [Bender](https://github.com/pulp-platform/bender) for hardware IPs and dependency management. Bender is available through Cargo or as pre-compiled binaries for Linux, macOS, and Windows: + +=== "Cargo" + + ```bash + cargo install bender + ``` + +=== "Precompiled" + + ```bash + curl --proto '=https' --tlsv1.2 https://pulp-platform.github.io/bender/init -sSf | sh + ``` + +Make sure that the Bender binary directory is in your `PATH`, or set the `BENDER` environment variable to the path of the Bender binary. + +### Python + +Some parts of _FlooNoC_ including the _FlooGen_ generator are written in Python. The required Python version is 3.10 or higher. You can install Python from the [official website](https://www.python.org/downloads/). + +### Simulation Tools + +Currently, we don't provide any open-source simulation setup such as Verilator. _FlooNoC_ was internally tested and verified with QuestaSim-2023.4. To run the RTL simulations you need to have QuestaSim installed. By default, _FlooNoC_ uses the `vsim` command to run the simulations, which can be overridden by setting the `VSIM` environment variable. + +## Installation + +Clone the repository from GitHub: + +```bash +git clone https://github.com/pulp-platform/FlooNoC.git +``` +Install the python dependencies and _FlooGen_: + +```bash +pip install . +``` + +## Usage + +### Running the Testbenches + +Now you can compile and run the testbenches with the following command: + +```bash +make compile-sim +make run-sim VSIM_TB_DUT=tb_floo_dut +``` +where you replace `tb_floo_dut` with the testbench that you want to simulate. + +### Generating a _FlooNoC_ Network + +To generate a _FlooNoC_ network using the _FlooGen_ generator, you can use the following command: + +```bash +floogen -c examples/floo_dut.yaml -o generated +``` + +## Optional dependencies + +For the development on _FlooGen_, it is recommended to install the `dev` dependencies for python linting and testing: + +=== "bash" + + ```bash + pip install .[dev] + ``` + +=== "zsh" + + ```zsh + pip install .\[dev\] + + ``` +For documentation generation, you can install the `docs` dependencies: + +=== "bash" + + ```bash + pip install .[docs] + ``` + +=== "zsh" + + ```zsh + pip install .\[docs\] + + ``` diff --git a/docs/hw/chimneys.md b/docs/hw/chimneys.md new file mode 100644 index 000000000..ca3531dae --- /dev/null +++ b/docs/hw/chimneys.md @@ -0,0 +1,71 @@ +# Network interfaces (a.k.a. chimneys) + +Network interfaces (NIs) are essentially the gateway to the Network-on-Chip (NoC). Every endpoint in the system requires its own NI to issue and receive packets over the NoC. The main purpose of the NI is to translate the on-chip protocol (e.g. AXI) to the link-level protocol of the network. NIs are not trivial to implement since they need to adhere to all the rules of the on-chip protocol e.g. ordering, flow control, etc. However, the advantage of using NIs is that the rest of the network can be agnostic to the on-chip protocol, which results in simpler router microarchitecture and as well as better scalability. Currently, _FlooNoC_ was mainly designed to support AXI4 and ships with dedicated NIs. However, it is possible to extend _FlooNoC_ also with other protocols, by implementing custom NIs. + +??? quote "Why chimneys?" + The name of _FlooNoC_ is derived from the Floo Network of Harry Potter. In the books, the Floo Network is a magical network of fireplaces that allows witches and wizards to travel from one place to another. Therefore, the chimneys are the gateways to the Floo Network, which is why they are called chimneys. + +## AXI Network Interface + +_FlooNoC_ ships with two different AXI NIs: the `axi_chimney` and the `nw_chimney`, which mainly differ from the ports and links that are connected to them. As the name implies, the `axi_chimney` has a single AXI port and uses only `req`/`rsp` physical channels, while the `nw_chimney` has a narrow *and* a wide AXI port and additionally features a `wide` physical channel. In the following, we will describe the inner workings of the `axi_chimney` in more detail. The `nw_chimney` is very similar, with largely duplicate datapaths for the narrow and wide ports. + +### Ordering + +One of the main challenges of implementing an NI for the AXI protocol is the strict ordering requirement that is imposed by AXI. The NI interface needs to be able to guarantee that for transactions with the same `txnID` all responses arrive with the same order as how the request were injected into the network. By design, the _FlooNoC_ link-level protocol does not guarantee ordering. For instance, if one request is sent to destination `A` and second request to destination `B`, the response from `B` can arrive before the response from `A`. There are essentially to ways of solving this problem: _Reordering_ or _stalling_. + +#### Reordering + +Responses that arrive out-of-order are buffered in a reorder buffer (RoB) until they can be delivered in-order. This approach is more performant, since multiple requests can be issued to different endpoints at the same time. However, a RoB is costly in terms of area and needs to be limited in size. Furthermore, the NI still needs to ensure that all responses from the NoC can be handled, either by buffering them in the RoB or forwarding them to the on-chip protocol (if they are in order). Stalling the network is not an option, as this would inevitably lead to deadlocks. Therefore, the NI also needs to track or allocate space in the RoB and only inject new requests into the network if it can guarantee that the responses can be handled: + +#### Stalling + +Another way to solve the ordering problem is to simply stall the injection of new requests into the network if the NI cannot guarantee that the responses will arrive in order. This approach is very simple to implement, and has a very small overhead, but it can lead to significant performance degredation in some cases. Luckily, there are some optimizations that the AXI NIs apply, which reduce the number of stalls. First, transactions to the same destination are always guaranteed to arrive in order (assuming a static routing algorithm is used in side the network). This means that the NI can inject multiple requests into the network, while the destination stays the same. Second, the ordering requirement only applies to transactions with the same `txnID`. Therefore, downstream components can also use different IDs to avoid ordering issues. + +The AXI NIs of _FlooNoC_ offers both options, and there are different implementations that can be set with the `ChimneyCfg.RoBType` parameter. The following table shows the different options: + +| RoBType | Description | +|---------|-------------| +| `NoRoB` | No RoB, which stalls transactions of the same `txnID` going to different destinations until the previous transaction is completed. This is option is useful if the ordering of transactions is handled downstream, e.g. in the DMA by issuing AXI transactions with different `txnIDs`. The overhead of this RoB is very low, since it only requires counters for tracking the number of outstanding transactions of each `txnID`.| +| `NormalRoB` | The most performant but also most complex RoB, which supports reodering of responses. This reorder buffer retains the out-of-order nature of AXI transactions with different IDs. Supports multiple outstanding transactions and bursts | +| `SimpleRoB` | Simpler FIFO-like RoB, which does not support reordering of responses with the same AXI `txnID`. Transactions with different `txnIDs` are effectively serialized. Supports multiple outstanding transactions but currently does not support burst transactions. Mainly useful for B-responses which are single transactions. | + +The selection of the RoB type depends on the endpoints that are attached to it. For instance, cores with narrower AXI interfaces might are less costly to reorder with a RoB, while DMAs with wider interfaces and burst requests might be prohibitively expensive to reorder. `FlooNoC` gives the option to specify the RoB type and size in the `ChimneyCfg` parameter. In AXI, both read and write response exist, for which different RoBs can be selected. For instance, the `B` response is very small and the cost of reordering it is quite low, which might not be true for the `R` responses. + +### Routing + +Another task of the NI is also to create the header of the flit which contains all the information required to route a packet from source to destination. To do this, the NI needs to translate the request address to a destination ID, which can be done in two different ways: + +* Address Offset: The NI simply uses a fixed offset into the request address to determine the destination ID. For instance, assuming an node ID width of 3, and an address offset of 8, the address `0x0f00` would be translated to node ID `0x7`. This is the simplest way to route packets, but it is also the least flexible. For instance, if not all of the endpoints have the same address range size, a lot of address space might be wasted. For simpler systems, this might however be a good choice. The Address Offset method can be enabled by setting the `RouteCfg.IdAddrOffset`, respectively `RouteCfg.XYAddrOffsetX` and `RouteCfg.XYAddrOffsetX` in case of `XYRouting`. + +* Address Map: The other alternative is to use an address map to translate the request address to a node ID. This is usually in the form of a global System Address Map (SAM), which consists of a list of address ranges and the corresponding node IDs. To configure this, the `RouteCfg.UseIdTable` needs to be set and the System Address Map can be passed to the network interface with the `Sam` parameter (which also requires setting the `RouteCfg.NumSamRules` parameter). + +Source-based routing is handled a bit different, since the route instead of the destination ID needs to be included in the header. Calculating the route is done in two steps 1) the destination ID is computed the same way as for the node ID based routing and 2) the destination ID is used as an index into a routing table to determine the route. The routing table is passed to the network interface over the `route_table_i` port (which requires setting the `RouteCfg.NumRoutes` parameter). + +### AXI Transaction ID handling + +In order to guarantee the correct ordering of AXI transactions, _FlooNoC_ does some special handling of the AXI `txnID` in the following ways: + +* The `txnID` is part of the payload of a flit and is not used by the routers to implement any kind of ordering. This also means that inside the NoC, there might be multiple AXI transactions from different managers in flight, which might have the same `txnID`, but are not ordered with respect to each other. + +* When transactions exit the NoC over a network interface, the transactions are serialized to the AXI network downstream by remapping the original `txnID` to `'1`. The main reason behind this approach, is that the network interface needs to store the `src_id`'s for the resulting response. The `src_id` of a request is stored in a FIFO, meaning the requests and the responses need have the same order. The serialization should not cause any big performance problems if the downstream AXI subordinates cannot handle out-of-order transactions. Alternatively, the _FlooNoC_ network interfaces also have the option to generate downstream requests with different `txnID`'s by setting the `ChimneyCfg.MaxUniqueIds` to a value higher than `1`. This comes at a higher cost, since the `src_id` and additional information need to be stored in an ID queue, that allows out-of-order access. + +* Atomic Transactions are issued with `txnID` that are unique amongst all AXI transactions in flight. The number of atomic transactions in flight can be configured with the `MaxAtomicTxns` parameter. Atomic transactions are then issued with `txnID` in the range `[0, '1)`. This also means that the number of outstanding atomic transaction is limited by the ID width. + +### Configuration + +Network interfaces are typically configued over the `ChimneyCfg` struct. For `nw_chimney`'s there is a configuration struct for narrow and wide data path each. The `ChimneyCfg` has the following configurations: + + +| Field | Type | Description | +|-------|------|-------------| +| `EnSbrPort` | `bit` | Whether an AXI subordinate (e.g. DRAM controller) is attached to the network interfaces. If not, the network interface will parametrize away some internal modules that are not needed in that case. | +| `EnMgrPort` | `bit` | Whether an AXI manager (e.g. host core) is attached to the network interfaces. If not, the network interface will parametrize away some internal modules that are not needed in that case. | +| `MaxTxns` | `int` | The number of both incoming and outgoing transactions that can be handled by the network interface. | +| `MaxUniqueIds` | `int` | The number of unique transaction IDs that can be issued by the network to AXI subordinates downstream. By default the network interface issues with a single txnID, effectively serializing incoming transactions from all managers in the entire system. If multiple txnIDs are used, incoming transactions with different TxnIDs _might_ not be serialized. This is results in more complex logic in the network interfaces, but might be useful for downstream AXI networks that can handle out-of-order transactions. | +| `MaxTxnsPerId` | `int` | Number of outstanding transactions per txnID. Only used if `RoBType == NormalRoB`. | +| `BRoBType` | `rob_type_e` | The type of Reoder Buffer (RoB) that is used for B responses. | +| `BRoBSize` | `int` | The depth of the RoB for B responses. Only used if `BRoBType != NoRoB`. | +| `RRoBType` | `rob_type_e` | The type of Reoder Buffer (RoB) that is used for R responses. | +| `RRoBSize` | `int` | The depth of the RoB for R responses. Only used if `RRoBType != NoRoB`. | +| `CutAx` | `bit` | Whether to buffer incoming AXI requests at the network interface, to ease timing closure. | +| `CutRsp` | `bit` | Whether to buffer incoming links at the network interface | diff --git a/docs/hw/commons.md b/docs/hw/commons.md new file mode 100644 index 000000000..5d1107823 --- /dev/null +++ b/docs/hw/commons.md @@ -0,0 +1,3 @@ +# Common IPs + +*TODO* diff --git a/docs/hw/flits.md b/docs/hw/flits.md new file mode 100644 index 000000000..4cb9c996a --- /dev/null +++ b/docs/hw/flits.md @@ -0,0 +1,69 @@ +# Flits + +We start with the _flits_, also called flow control units, which is the smallest unit of data that is sent from node to another (e.g. from router to router, of network interface to router). Flits consists of two types of data: + +1. **Routing information**: Also called the header of the flit, this data is used by the routers to route the flit through the network. The header contains information such as the destination address, the source address, the flit type, etc. + +1. **Payload**: This is the actual data that is being sent from one node to another. Router do not look at the payload, they just forward it to the next hop. + +In traditional NoCs, the links have a fixed width (e.g. 32-bit). Usually, the payload and the information required for routing far exceeds this width. Therefore, the payload is split into multiple data flits and a header flit which encodes the routing information. Based on this information, routers in the network then know how to route the following data flits to the destination. + +In modern NoCs, this way of serializing payloads over the network is not very efficient anymore. With higher bandwidth requirements of the endpoints, the serialization becomes more and more a bottleneck, since the frequency of the links is limited. Further, serialization causes additional latency which is undesirable. Lastly, the overhead of the header flits is not negligible, especially when the payload is small. + +Therefore, In _FlooNoC_ and modern NoCs in general[^1], another approach is taken, which differs in two ways: + +[^1]: The [AMBA CHI](https://developer.arm.com/documentation/ihi0050/latest/) protocol also encodes the entire payload (cachelines in this case) in a single flit including all the information required for routing. + +1. **Flit width**: The width of the flits is not fixed anymore. Instead, the flits can be as wide as the payload to send the payload in a single cycle resp. in a single flit. + +1. **Parallel header**: Instead of sending the header before the payload, the header is sent in parallel to the payload. This way, the link utilization is not degraded by header flits. + +Below, we will discuss the header and the payload in more detail. + +## Header + +In _FlooNoC_ the header consists of the following fields: + +| Field | Type | Required by | Description | +| ----------- | --------------- | ---------- | --------------------- | +| `dst_id` | `dst_t` or `route_t` | Router | The destination ID of the flit. In the case of source-based routing, it encodes the entire route from source to destination. | +| `src_id` | `dst_t` | Chimney | The source ID of the flit. Used by the Chimney to set the `dst_id` for the response | +| `last` | `logic` | Router | Can be used by the Chimneys that a burst of flits is not interleaved with other flits from other endpoints. If not set the router performs wormhole routing i.e. it locks the direction until flit with the `last` bit set has been sent. | +| `axi_ch` | `axi_ch_e`[^2] | Chimney | Used by the Chimney to encode the type of packet e.g. which AXI channel | +| `rob_req` | `logic` | Chimney | Flag to signal that the flit might need to be reordered in the Chimney | +| `rob_idx` | `rob_idx_t` | Chimney | The index into the reorder buffer of the Chimney | +| `atop` | `logic` | Chimney | Flag to signal that the flit is an ATOP flit and can bypass the reodering logic. | + +!!! info "Additional fields" + + Additional fields can be added to the header if needed. The routers just ignore those fields and forward them to the next router/Chimney. + +!!! example "SystemVerilog macros" + + _FlooNoC_ provides System Verilog macros in `typedef.svh` to generate the header fields such as `FLOO_TYPEDEF_HDR_T`. + +[^2]: The type is arbitrary and depends on the type of Chimney used but it is usually an `enum`. For instance, the single-AXI chimney encodes only 5 channels in `axi_ch_e`, while the narrow-wide AXI chimney encodes 10 channels in `nw_ch_e`. This can also be extended. + +## Payload + +The payload itself can be any data that needs to be sent from one node to another. The payload is not interpreted by the routers, they just forward it to the next hop. The payload can be of any width. Usually, the payload consists of an AXI request or response of one of the 5 channels. + +## Types of flits + +The entire flit is constructed by concatenating the header and the payload. One can define many types of flits i.e. one for every payload. The only requirement is that the flit includes the following fields: + +| Field | Type | Description | +| ----------- | --------------- | --------------------- | +| `hdr` | `hdr_t` | The header of the flit, which is identical across the whole network | +| `payload` | `payload_t`[^3] | The payload of the flit, which can be of any width | +| `rsvd` | `logic[RsvdBits-1:0]` | Optional padding bits if the flit is smaller than the link width | + +[^3]: The payload type can be anything. For instance, sending an AXI AW is done by defining a `axi_aw_chan_t` struct for the payload type. + +!!! info "Additional fields" + + Again, additional fields can be added if needed. The only requirement is that the width of the flit matches exactly the width of the link. + +!!! example "SystemVerilog macros" + + _FlooNoC_ provides System Verilog macros in `typedef.svh` to generate the flits such as `FLOO_TYPEDEF_FLIT_T` for flits with the `rsvd` field and generic flits `FLOO_TYPEDEF_GENERIC_FLIT_T` without a `rsvd` field. diff --git a/docs/hw/links.md b/docs/hw/links.md new file mode 100644 index 000000000..002e28b13 --- /dev/null +++ b/docs/hw/links.md @@ -0,0 +1,106 @@ +# Channels + +Now that we established flits -- the smallest unit of data that is sent -- we can discuss how a flit is sent from one node to another. As we have explained in the [flits](flits.md) section, there usually exist multiple types of flits, which differ in the payload they carry. For instance, the payload can be an AXI request, an AXI response, or any other data that needs to be sent from one node to another. For multiple reasons, it makes sense to send these different types of flits over different "channels", which we will discuss in this section. + +## Why use multiple channels? + +Channels are a way to separate different types of flits. For instance, one channel can be used to send AXI requests, another channel can be used to send AXI responses, and a third channel can be used to send other types of data. This separation has multiple advantages: + +1. **Message-Level deadlocks**: If all flits are sent over a single channel, it could happen that message-level deadlocks are introduced. For instance, if node A sends a request to node B, and node B sends a request to node A, both nodes both nodes might need to wait for their response before accepting a new request, which can lead to a deadlock. By separating the request and response channel, we can ensure forward progress. + +1. **Latency**: Different types of flits might have different priorities. For instance, some messages are very latency-sensitive (e.g. synchronization messages), while others are much more latency-tolerant (e.g. bulk data transfers). By separating the channels, we can ensure that the congestion can be kept low on the latency-sensitive channel, which in turn reduces the latency of these messages. + +1. **Bandwidth**: Different types of flits might have different bandwidth requirements. For instance, the data widths of AXI can reach up to 1024 bit, and AXI additionally supports burst transfers. Using wide links is the natural way to increase the bandwidth of the channel. However, smaller flits like AXI write responses are only a fraction of the link width and would waste bandwidth if sent over a wide link. + +## Virtual vs. Physical channels + +There are essentially two different ways how to implement multiple channels: + +1. **Virtual channels**: Virtual channels are a way to multiplex multiple channels over a single physical channel. Virtual channel have the advantage that the physical channel can be used more efficiently, as it can be shared between multiple virtual channels. Moreover, message-level deadlocks can be prevented with virtual channels, as messages from different channels can be interleaved, resp. they can overtake each other. This is possible, since on the RX side of a virtual channel, every channel has its own buffers. So even if for instance the buffer for requests is full, responses can still be received. While virtual channels have its advantages, they also have some disadvantages. For instance, virtual channels require additional logic to multiplex and demultiplex the channels, which increases the complexity of the design. Furthermore, multiplexing onto a single physical channel limits the throughput of the channel. + +1. **Physical channels**: Physical channels on the other hand are _real_ physical channels in hardware. Effectively, physical channels result in multiple separate networks used to send different types of messages throught the network. The main advantage of physical channels is the throughpt of the channel, since it is not shared with other channels. Also, routers for physical channels can be streamlined, since they don't require multiplexing of virtual channels. One disadvantage of physical channels is that they require more routing resources, as each physical channel is implemented as a separate network. + +One of the main design principles of _FlooNoC_ is to use multiple physical channels instead of virtual channels. While the main drawback of physical channels is the increased routing resources, modern technologies come to rescue here. For instance, modern technologies usually can feature up to 20 metal layers and have routing resources of >10000 wires/mm that can be exploited to implement multiple physical channels. Not all of it is avaliable for routing of course, since some routing resources are used for cell connectivity and power distribution. However, the routing resources tend not to be the bottleneck in the design, especially not global wires on higher metal layers of the chip, which are primarly used for the routing of the physical links. + +!!! tip "Wires are cheap now" + + A very good source on this topic, which has also greatly influenced the use of physical channels during the development of _FlooNoC_ is the NOCS keynote [Reflections on 21 Years of NoCS](https://www.youtube.com/watch?v=Nk3oQm9NxcY) from Bill Dally, one of the pioneers in early NoC research. + +## _FlooNoC_ channels + +In _FlooNoC_, we use multiple physical channels to separate different types of traffic. The most basic form of _FlooNoC_ is to use two channels `req` and `rsp`, to send all request resp. responses. However, traffic in an SoC can be quite diverse, and comes with different requirements. For instance, synchronization messages are usually very small in the order of a few bytes, but are very latency-sensitive. On the other hand, bulk data transfers can be very large, but are usually more tolerant to latency, since they can be issued as multiple outstanding transactions. In some systems, this is the reason why mulitple AXI interfaces are used. A narrow one for configuration and synchronization messages and a wider one for bulk data transfers. In that case, _FlooNoC_ also featuers a `wide` channel to provide high bandwidth for bulk data transfers. + +## Channel Mapping + +### Single-AXI to `req`, `rsp` mapping + +If only a single AXI interface is used (e.g. with 32-bit address width and 64-bit data width), the AXI channels are mapped to the _FlooNoC_ channels as follows: + +| | `req` | `rsp` | primary payload | +| ----------------- | ---- | ---- | --- | +| `Aw` | :material-check: | - | `addr` (32-bit) | +| `Aw` | :material-check: | - | `addr` (32-bit) | +| `W` | :material-check: | - | `w_data` (64-bit) | +| `R` | - | :material-check: | `r_data` (64-bit) | +| `B` | - | :material-check: | `b_rsp` (2-bit) | + +The mapping is quite straightforward. Requests from AXI manager are sent over the `req` channel, while responses from AXI subordinates are sent over the `rsp` channel. Message-level deadlock are also avoided this way, since requests and responses are sent over different channels. + +## Narrow-Wide AXI to `req`, `rsp`, `wide` mapping + +In case two AXI interfaces are used, a narrow (e.g. 64-bit) and a wide one (e.g. 512-bit), the AXI channels are mapped to the _FlooNoC_ channels as follows: + +| | `req` | `rsp` | `wide` | primary payload | +| ----------------- | ---- | ---- | ---- | --- | +| `NarrowAw` | :material-check: | - | - | `addr` (32-bit) | +| `NarrowAr` | :material-check: | - | - | `addr` (32-bit) | +| `NarrowW` | :material-check: | - | - | `w_data` (64-bit) | +| `NarrowR` | - | :material-check: | - | `r_data` (64-bit) | +| `NarrowB` | - | :material-check: | - | `b_rsp` (2-bit) | +| `WideAw` | - | - | :material-check: | `addr` (32-bit) | +| `WideAr` | :material-check: | - | - | `addr` (32-bit) | +| `WideW` | - | - | :material-check: | `w_data` (512-bit) | +| `WideR` | - | - | :material-check: | `r_data` (512-bit) | +| `WideB` | - | :material-check: | - | `b_rsp` (2-bit) | + +In this case, the narrow AXI to `req`, `rsp` mapping is the same as in the single-AXI case. However, the wide AXI interface mapping is a different and requires some explanation. Unsurprisingly, the wide data channels `WideR` and `WideW` are mapped to the `wide` channel to make use of its high bandwidth. The AXI read request `WideAr` and the write response `WideB` are mapped to the `req` and `rsp` channel, respectively. Those are smaller messages and would underutilize the `wide` channel. The outlier here is the AXI write requests `WideAw`, which is mapped to the `wide` channel, eventhough it is a small message. The reason for this is related to the ordering of AXI transactions. + +??? info "AXI ordering for the curious" + + AXI supports out-of-order transactions by specifying transaction IDs (`txnID`). Transactions with the same `txnID` need to be ordered with respect to each other i.e. they cannot overtake each other. Transactions with different `txnID` however are free to do so. The `txnID` is specified in the initial requests and the corresponding read and write response also carries the same `txnID`. However, the write data is a bit different in this regard. The write data `W` does not feature any `txnID` and needs to be sent (and eventually arrive at the AXI subordinate) in the same order as the write requests `Aw`. This also needs to be guaranteed in systems with multiple AXI managers that send write requests to the same AXI subordinate. If the `Aw` and `W` are sent over different channels, it might be that the order of them is not preserved since those differnent channels might have different congestion levels. To avoid this, the `WideAw` and `WideW` are sent over the same channel, which is the `wide` channel in this case. Furthermore, it also needs to be guaranteed that `WideW` payloads from different AXI requesters are not interleaved in the network, since they cannot be distinguished when arriving at the destination (which would also very likely require large reorder buffers). The non-interleaving needs to be guaranteed by the routers as well, which will be discussed later in the [routers](routers.md) section. + + +_FlooNoC_ uses `unions` to represent the different types of flits that are sent over the same physical channel. For instance, the `req` channel for a single-AXI configuration is defined as follows: + +```verilog +typedef union packed { + floo_aw_flit_t axi_aw; + floo_w_flit_t axi_w; + floo_ar_flit_t axi_ar; + floo_generic_flit_t generic; +} floo_req_chan_t; +``` + +A `union` essentially allows to represent multiple types of data in the same number of bits. This is also why `rsvd` bits are used in the flits, to ensure that the flits sent over a channel all have the same size. The `generic` is not meant to represent a flit with an actual payload, but can be used to decode the type of flit from its header. + +!!! example "SystemVerilog Macros" + Similar to the flits, _FlooNoC_ provides System Verilog macros in `typedef.svh` to generate the channel types such as `FLOO_TYPEDEF_AXI_CHAN_ALL` for a single-AXI configuration and `FLOO_TYPEDEF_NW_CHAN_ALL` for a narrow-wide AXI configuration. + + +## Links + +The links itself wraps a channel and additionally handles the flow control needed to send data from one node to another. _FlooNoC_ primarily uses valid-ready handshaking flow control, but also has some support for credit-based flow control (see routers section for more information). The link then looks as follows: + +```verilog + typedef struct packed { + logic valid; + logic ready; + floo_req_chan_t req; + } floo_req_t; +``` + +!!! info "Bidirectional links" + Currently, _FlooNoC_ only supports bidirectional links. This is why both `valid` and `ready` are encoded in the same link, eventhough they are separate from each other (i.e. the `ready` is an RX signal, while the `valid` is a TX signal). + +!!! example "SystemVerilog Macros" + Again, _FlooNoC_ provides System Verilog macros in `typedef.svh` to generate the flit types. For instance, `FLOO_TYPEDEF_AXI_LINK_ALL` for a single-AXI configuration and `FLOO_TYPEDEF_NW_LINK_ALL` for a narrow-wide AXI configuration. diff --git a/docs/hw/overview.md b/docs/hw/overview.md new file mode 100644 index 000000000..85544bc3f --- /dev/null +++ b/docs/hw/overview.md @@ -0,0 +1,19 @@ +# Overview of the Hardware IPs + +_FlooNoC_ is a collection of Network-on-Chip (NoC) IPs written in SystemVerilog that can used to assemble an NoC. In system architecture, there are a myriad of different considerations that go into the implementation of the on-chip network. From the topology of the network, the routing algorithm, flow-control, the use of virtual or physical channels, etc. This is why our goal was to make the _FlooNoC_ IPs as modular, configurable and extendible as possible, so that they can be easily integrated into any system. + +However, this also means that the hardware IPs are heavily parametrizable and the user has to make a lot of decisions when configuring the _FlooNoC_ IPs. This is what this documentation aims to help with. It will guide through all the available IPs, explain their architecture, and show how they need to be configured and what the trade-offs are. The documentation is structured as follows: + +1. **[Links](links.md)**: This section will explain the custom link-level protocol, which is used to connect the routers and network interfaces in the NoC. + +1. **[Routing Algorithms](route_algos.md)**: This section will explain the different routing algorithms that are available in _FlooNoC_ and how they can be configured. + +1. **[Network Interfaces](chimneys.md)**: This section will explain the different network interfaces which are used to convert to the custom link-level protocol of _FlooNoC_. + +1. **[Routers](routers.md)**: This section will explain the routers routers that are available in _FlooNoC_ and how they can be configured. + +1. **[Common IPs](commons.md)**: Apart from the two essential IPs, routers and network interfaces, there are also some common IPs that can be used to extend the functionality of the NoC. This section will explain these IPs. + +1. **[Verification IPs](vips.md)**: This section will explain the verification IPs that are available in _FlooNoC_ and how they can be used to verify the NoC. + +1. **[Tips & Tricks](tips.md)**: This section will give some tips and tricks on how to use the _FlooNoC_ IPs. diff --git a/docs/hw/route_algos.md b/docs/hw/route_algos.md new file mode 100644 index 000000000..9cf510c74 --- /dev/null +++ b/docs/hw/route_algos.md @@ -0,0 +1,79 @@ +# Routing Algorithms + +One of the main design principles of _FlooNoC_ is that it is flexible and can support multiple routing algorithms as well as arbitrary topologies. Currently, _FlooNoC_ supports the following routing algorithms: + +1. **Dimension-ordered Routing (DOR)**: Also known as XY-Routing and arguably the most popular routingn algorithm used in 2D mesh networks, due to its simple implementation and guarantee of deadlock freedom. + +1. **Source-based routing**: A routing algorithm where the source specifies the entire route to the destination. + +1. **Table-based routing**: A routing algorithm where the selection of port is based on a table that is provided to the router. + +All of those routing algorithms are static respectively deterministic. While dynanmic routing algorithms might feature better performance since it can adapt to changing network conditions, they are also more complex to implement and might introduce deadlocks. Furthermore, _FlooNoC_ uses the deterministic routing assumption of the network to guarante the correct ordering of AXI transactions. For instance, _FlooNoC_ relies on the fact that flits from the same source and channel to the same destination remain ordered, which is not given in dynamic routing algorithms. + +## Dimension-ordered (DOR) + +Dimension-ordered routing is a simple routing algorithm that routes flits based on XY-coordinates, which is why it is commonly used in 2D mesh networks. In dimension ordered routing, a flit is always routed in one dimension and then in the other. Since this routing cannot introduce any cycles, it is deadlock-free by design. The implementation of DOR is also very simple, as it only requires the current and destination coordinates of the flit. Each router knows its own XY coordinates and compares them to the destination coordinates of the flit. The routing algorithm then is the following: + +$$ +Port = \begin{cases} +East & id_{dst, x} > id_{router, x} \\ +West & id_{dst, x} < id_{router, x} \\ +North & id_{dst, x} = id_{router, x} \land id_{dst, y} > id_{router, y} \\ +South & id_{dst, x} = id_{router, x} \land id_{dst, y} < id_{router, y} \\ +Eject & id_{dst, x} = id_{router, x} \land id_{dst, y} = id_{router, y} +\end{cases} +$$ + +Meaning, the flits is routed to either the east or west until it reaches the correct X-coordinate, after which it is routed to the north or south until. If both coordinates match, the flit is ejected from the network i.e. it is sent to (one of the) local port(s) of the router. + +### Advantages + +The DOR routing algorithm is very simple but effective and results in very low complexity in the hardware. Furthermore, it is deadlock-free by design since it cannot introduce any cycles. Also, XY-routing allows for some optimization in the router design. Since a flit is always routed first in X and then in Y, some connections in the router are illegal and can be disabled to reduce the number of connections in the router. For instance, the connection from north to east or west is not possible as this would imply that the flit was routed in the Y-dimension before the X-dimension. + +### Disadvantages + +The main disadvantage of DOR routing is that it only works in 2D meshes. Also, there are some corner cases where DOR routing can create problems. For instance, if nodes are attached to the boundary of the mesh, a flit entering from the north boundary cannot reach the east boundary, since it would have to change X and Y direction multiple times. + +## Source-based Routing + +Source-based routing is another simple routing algorithm where the entire route to the destination is specified by node which injects the flit into the network. The route is encoded in the header of the flit as an array of ports that each router should take. The size of the route encoding depends on the diameter of the network (the maximum number of hops) as well as the router radix (number of router ports). For instance, a route might be encoded like this in a 4x4 2D mesh network: + +```verilog + route_t route = '{3'b0, 3'b1, 3'b2, 3'b3, 3'b4, 3'b5, 3'b6}; +``` + +A router usually has 5 ports (4 for the cardinal directions and one local port), which can be encoded in 3 bits. Further, the maximum number of hops in a router is 7 (including the routers where the flit is injected and ejected), which results in a route encoding of 21 bits. This route encoding is part of the flit header and is checked by each router. + +??? example "Flit header differences" + The header of a flit is different for source-based routing compared to the other routing algorithms. Instead of encoding the destination id (`dst_id`) as a node ID (of type `id_t`), the destination id is encoded as a route (`route_t`). The source id (`src_id`) is still encoded as a node ID, since the source node generally does not know the route back to itself from the destination. Instead it provides the `src_id`, which can be translated back to a route by the destination node. + + +The implementation of this routing algorithm is also very simple, since every router _consumes_ a port from the route encoding, which means it simply shifts the route encoding by the number of bits that is required to encode the number of possible ports. This way, a router does not neet to be aware of how many hops a flit has already passed, since it can simply look at the first bits of the route encoding to determine the next port. + +### Advantages + +The main advantage of source-based routing is that it is very flexible and can be used in arbitrary topologies, that go beyond 2D meshes. The routes can also be optimized for instance to reduce congestion or to minimize the number of hops. Theoretically, source-based routing can also be dynamic, since the source can change the route encoding based on the network conditions. However, as mentioned before, _FlooNoC_ currently does not support dynamic routing algorithms. + +### Disadvantages + +The main disadvantage of source-based routing is that the bits required for encoding the route grows with the network diameter and at some point it becomes infeasible to encode the route in the flit header. Also, source-based routing is not inherently deadlock-free, if the routes are not carefully chosen. Lastly, the route encodings need to be provided to the source respectively the network interface, which can become quite large, since every destination requires its own route encoding. + +## Table-based Routing + +Table-based routing shifts the routing computation to the routers themselves. Each router has a table that specifies the output port for each destination. Instead of using actual tables, it is also possible to use address decoders which can reduce the number of entries in the table, since it allows to specify a range of destinations that are routed to the same port. An instance of such a routing table could look like the following: + +```verilog + localparam router_rule_t [NumRules-1:0] RouterTable = '{ + '{idx: 1, start_addr: 0, end_addr: 2}, // -> port 1 for destination 0, 1 + '{idx: 2, start_addr: 2, end_addr: 3}, // -> port 2 for destination 2 + '{idx: 3, start_addr: 3, end_addr: 10} // -> port 3 for destination 3 to 9 + }; +``` + +where `idx` is the port number and `start_addr` and `end_addr` is the range of destination node IDs that are routed to the port. + +### Advantages +Similar to source-routing, table-based routing can be used for any kind of topology and the routes respectively the routing tables can be optimized to avoid congestion etc., Also, table-based routing can be dynamic, since the routing tables could be updated dynamically (which is not supported by _FlooNoC_). + +### Disadvantages +Table-based routing has a similar problem as source-based routing, since the router tables grow with the number of destinations. Also, table-based routing is not inherently deadlock-free, if the routing tables are not carefully chosen. Lastly, the routing tables need to be provided to the routers, which can become quite large, since every destination requires its own routing table. diff --git a/docs/hw/routers.md b/docs/hw/routers.md new file mode 100644 index 000000000..ff4f3e83d --- /dev/null +++ b/docs/hw/routers.md @@ -0,0 +1,3 @@ +# Routers + +*TODO* diff --git a/docs/hw/tips.md b/docs/hw/tips.md new file mode 100644 index 000000000..a0c1a693a --- /dev/null +++ b/docs/hw/tips.md @@ -0,0 +1 @@ +# Tips & Tricks diff --git a/docs/hw/vips.md b/docs/hw/vips.md new file mode 100644 index 000000000..ced2cfd7f --- /dev/null +++ b/docs/hw/vips.md @@ -0,0 +1,3 @@ +# Verification IPs (VIPs) of _FlooNoC_ + +*TODO* diff --git a/docs/img/floo_noc_favicon_logo.png b/docs/img/floo_noc_favicon_logo.png new file mode 100644 index 000000000..be19c4552 Binary files /dev/null and b/docs/img/floo_noc_favicon_logo.png differ diff --git a/docs/img/floo_noc_favicon_logo.svg b/docs/img/floo_noc_favicon_logo.svg new file mode 100644 index 000000000..23a7eb856 --- /dev/null +++ b/docs/img/floo_noc_favicon_logo.svg @@ -0,0 +1,102 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/docs/img/floo_noc_material_logo.png b/docs/img/floo_noc_material_logo.png new file mode 100644 index 000000000..85b0c540b Binary files /dev/null and b/docs/img/floo_noc_material_logo.png differ diff --git a/docs/img/floo_noc_material_logo.svg b/docs/img/floo_noc_material_logo.svg new file mode 100644 index 000000000..0090fc825 --- /dev/null +++ b/docs/img/floo_noc_material_logo.svg @@ -0,0 +1,98 @@ + + + + + + + + + + + + + + + + + + + + diff --git a/docs/index.md b/docs/index.md new file mode 100644 index 000000000..0e7cb8869 --- /dev/null +++ b/docs/index.md @@ -0,0 +1,57 @@ +# FlooNoC: A Fast, Low-Overhead On-chip Network + +_FlooNoC_, is a Network-on-Chip (NoC) research project, which is part of the [PULP (Parallel Ultra-Low Power) Platform](https://pulp-platform.org/). The main idea behind _FlooNoC_ is to provide a scalable high-performance NoC for non-coherent systems. _FlooNoC_ was mainly designed to interface with [AXI4+ATOPs](https://github.com/pulp-platform/axi/tree/master), but can easily be extended to other On-Chip protocols. _FlooNoC_ already provides network interface IPs (named chimneys) for AXI4 protocol, which converts to a custom-link level protocol that provides significantly better scalability than AXI4. _FlooNoC_ also includes protocol-agnostic routers based on the custom link-level protocol to transport payloads. Finally, _FlooNoC_ also include additional NoC components to assemble a complete NoC in a modular fashion. _FlooNoC_ is also highly flexible and supports a wide variety of topologies and routing algorithms. A Network generation framework called _FlooGen_ makes it possible to easily generate entire networks based on a simple configuration file. + +## Quick Links + +
+ +- :material-fast-forward:{ .lg .middle } __Setup & Installation__ + + --- + + Install Bender for HW IPs and python dependencies for _FlooGen_ + + [:octicons-arrow-right-24: Getting started](getting_started.md) + +- :fontawesome-solid-microchip:{ .lg .middle } __Hardware IPs__ + + --- + + Check out the documentation of _FlooNoC_ hardware IPs. + + [:octicons-arrow-right-24: Hardware IPs](hw/overview.md) + +- :material-magic-staff:{ .lg .middle } __Network Generation__ + + --- + + Learn how to generate a _FlooNoC_ network using _FlooGen_ + + [:octicons-arrow-right-24: FlooGen](floogen/overview.md) + +- :material-scale-balance:{ .lg .middle } __License__ + + --- + + _FlooNoC_ is available open-source on [GitHub](https://github.com/pulp-platform/FlooNoC) under permissive licenses. + + [:octicons-arrow-right-24: License](license.md) + +- :material-bookshelf:{ .lg .middle } __Publication__ + + --- + + Read the publication of _FlooNoC_. + + [:octicons-arrow-right-24: Publication](https://arxiv.org/abs/2409.17606) + +- :material-file-document:{ .lg .middle } __Changelog__ + + --- + + Check out what has changed in the latest version of _FlooNoC_. + + [:octicons-arrow-right-24: Changelog](changelog.md) + +
diff --git a/docs/javascripts/mathjax.js b/docs/javascripts/mathjax.js new file mode 100644 index 000000000..7e48906af --- /dev/null +++ b/docs/javascripts/mathjax.js @@ -0,0 +1,19 @@ +window.MathJax = { + tex: { + inlineMath: [["\\(", "\\)"]], + displayMath: [["\\[", "\\]"]], + processEscapes: true, + processEnvironments: true + }, + options: { + ignoreHtmlClass: ".*|", + processHtmlClass: "arithmatex" + } +}; + +document$.subscribe(() => { + MathJax.startup.output.clearCache() + MathJax.typesetClear() + MathJax.texReset() + MathJax.typesetPromise() +}) diff --git a/docs/license.md b/docs/license.md new file mode 100644 index 000000000..6ef3f5a97 --- /dev/null +++ b/docs/license.md @@ -0,0 +1,3 @@ +# License + +All code checked into this repository is made available under a permissive license. All software sources of _FlooGen_ under `floogen` are licensed under the [Apache License 2.0](Apache-License.md), and all hardware sources in the `hw` folder are licensed under the [Solderpad Hardware License 0.51](SHL-License.md). diff --git a/docs/repository_structure.md b/docs/repository_structure.md new file mode 100644 index 000000000..6de42acee --- /dev/null +++ b/docs/repository_structure.md @@ -0,0 +1,23 @@ +# Repository Structure and Contents + +This document describes the structure of the repository and the contents of the directories. + +## The `hw` hardware directory + +The `hw` directory contains all the hardware-related files for all the SystemVerilog IPs. The directory is structured as follows: + +- `*.sv`: SystemVerilog packages and modules for the IPs. +- `test`: Verification IPs (VIPs) such as monitors, random initiators for the testbenches. +- `tb`: Testbenches for the IPs. + +## The `floogen` _FlooGen_ directory + +The `floogen` directory contains the Python framework for _FlooGen_ to generate complete _FlooNoC_ networks based on a simple configuration file. The directory is structured as follows: + +- `examples`: A couple of example configuration files. +- `model`: The python models for routers, network interfaces and endpoints that are used by _FlooGen_. +- `templates`: Mako templates for the generation of the SystemVerilog files. +- `tests`: Unit tests for the _FlooGen_ framework. +- `floo_gen.py`: The main script for _FlooGen_. +- `config_parser.py`: The configuration parser for _FlooGen_. +- `utils.py`: Various utility functions for _FlooGen_. diff --git a/docs/stylesheets/extra.css b/docs/stylesheets/extra.css new file mode 100644 index 000000000..2ea440b2d --- /dev/null +++ b/docs/stylesheets/extra.css @@ -0,0 +1,9 @@ +/* Copyright 2024 ETH Zurich and University of Bologna. */ +/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ +/* SPDX-License-Identifier: Apache-2.0 */ + +:root { + --md-primary-fg-color: #02793C; + --md-primary-fg-color--light: #21B42A; + --md-primary-fg-color--dark: #05422B; +} diff --git a/floogen/cli.py b/floogen/cli.py index 55e619443..993c589c6 100755 --- a/floogen/cli.py +++ b/floogen/cli.py @@ -55,14 +55,15 @@ def render_sources(network: Network, args: argparse.Namespace): if args.rdl: rdl_file_name = outdir / f"{network.name}.rdl" with open(rdl_file_name, "w+", encoding="utf-8") as rdl_file: - rdl_file.write(network.render_rdl(rdl_as_mem=args.rdl_as_mem)) + rdl_file.write(network.render_rdl(rdl_as_mem=args.rdl_as_mem, + rdl_memwidth=args.rdl_memwidth)) else: if not args.only_top and not args.rdl: print(rendered_pkg) if not args.only_pkg and not args.rdl: print(rendered_top) if args.rdl: - print(network.render_rdl(rdl_as_mem=args.rdl_as_mem)) + print(network.render_rdl(rdl_as_mem=args.rdl_as_mem, rdl_memwidth=args.rdl_memwidth)) def parse_args(): @@ -109,6 +110,13 @@ def parse_args(): default=False, help="Add memory blocks for address regions without 'rdl_name' declared.", ) + parser.add_argument( + "--rdl-memwidth", + dest="rdl_memwidth", + type=int, + default=8, + help="Use the memory width of the RDL address region as the width of the memory block.", + ) parser.add_argument( "--no-format", dest="no_format", diff --git a/floogen/config_parser.py b/floogen/config_parser.py index 7114330cd..a7f68cc6d 100644 --- a/floogen/config_parser.py +++ b/floogen/config_parser.py @@ -24,12 +24,12 @@ def get_error_context(config_file: Path, line, column, context_before=4, context """Retrieves the context surrounding an error in a configuration file.""" lines_to_return = [] with config_file.open() as file: - for line_idx, l in enumerate(file.readlines()): + for line_idx, line in enumerate(file.readlines()): if line_idx + 1 == line: - lines_to_return.append(l) + lines_to_return.append(line) lines_to_return.append(click.style(column * " " + "^\n", blink=True, fg="yellow")) elif line_idx + 1 >= line - context_before and line_idx + 1 <= line + context_after: - lines_to_return.append(l) + lines_to_return.append(line) return "".join(lines_to_return) diff --git a/floogen/model/endpoint.py b/floogen/model/endpoint.py index ddff37a50..82b47121e 100644 --- a/floogen/model/endpoint.py +++ b/floogen/model/endpoint.py @@ -7,7 +7,7 @@ from typing import Optional, List, Union, Tuple from pydantic import BaseModel, ConfigDict, field_validator, model_validator -from floogen.model.routing import AddrRange, Id, Coord +from floogen.model.routing import AddrRange, SimpleId, Coord from floogen.model.protocol import Protocols @@ -23,7 +23,7 @@ class EndpointDesc(BaseModel): array: Optional[Union[Tuple[int], Tuple[int, int]]] = None num: Optional[int] = None addr_range: List[AddrRange] = [] - xy_id_offset: Optional[Id] = None + xy_id_offset: Optional[Union[SimpleId, Coord]] = None mgr_port_protocol: Optional[List[str]] = None sbr_port_protocol: Optional[List[str]] = None @@ -39,11 +39,7 @@ def int_to_tuple(cls, v): @classmethod def dict_to_coord_obj(cls, v): """Convert dict to Coord object.""" - match v: - case None: - return None - case {"x": x, "y": y}: - return Coord(x=x, y=y) + return Coord.from_dict(v) @field_validator("addr_range", mode="before") @classmethod diff --git a/floogen/model/graph.py b/floogen/model/graph.py index 310708530..cad321bc7 100644 --- a/floogen/model/graph.py +++ b/floogen/model/graph.py @@ -55,6 +55,10 @@ def get_node_arr_idx(self, node): """Return the node array index.""" return self.nodes[node]["arr_idx"] + def get_node_arr_dim(self, node): + """Return the node array dimension.""" + return self.nodes[node]["arr_dim"] + def get_node_lvl(self, node): """Return the node level.""" return self.nodes[node]["lvl"] @@ -237,7 +241,7 @@ def add_nodes_as_array( case [n]: for i in range(n): node = f"{name}_{i}" - self.add_node(node, type=node_type, arr_idx=(i,), obj=node_obj) + self.add_node(node, type=node_type, arr_idx=(i,), arr_dim=array, obj=node_obj) if i > 0 and connect: self.add_edge(node, f"{name}_{i-1}", type=edge_type, obj=edge_obj) self.add_edge(f"{name}_{i-1}", node, type=edge_type, obj=edge_obj) @@ -245,7 +249,8 @@ def add_nodes_as_array( for i in range(n): for j in range(m): node = f"{name}_{i}_{j}" - self.add_node(node, type=node_type, arr_idx=(i, j), obj=node_obj) + self.add_node(node, type=node_type, arr_idx=(i, j), + arr_dim=array, obj=node_obj) if i > 0 and connect: self.add_edge( node, diff --git a/floogen/model/network.py b/floogen/model/network.py index 833d38f09..77c99e96b 100644 --- a/floogen/model/network.py +++ b/floogen/model/network.py @@ -15,7 +15,7 @@ from mako.lookup import Template from pydantic import BaseModel, ConfigDict, StringConstraints, field_validator, model_validator -from floogen.model.routing import Routing, RouteAlgo, RouteMapRule, RouteRule, RouteMap, RouteTable +from floogen.model.routing import Routing, RouteAlgo, RouteMapRule, RouteRule, RouteMap, RouteTable, RouteMapRuleMcast from floogen.model.routing import Coord, SimpleId, AddrRange, XYDirections from floogen.model.graph import Graph from floogen.model.endpoint import EndpointDesc, Endpoint @@ -458,7 +458,7 @@ def compile_endpoints(self): prot["source"] = ep_name prot["dest"] = ep.get_ni_name(ep_name) if ep.array is not None: - prot["array"] = ep.array + prot["arr_dim"] = ep.array prot["arr_idx"] = self.graph.get_node_arr_idx(ep_name) protocol = AXI4Bus(**prot, **protocol.__dict__) mgr_ports.append(protocol) @@ -475,7 +475,7 @@ def compile_endpoints(self): prot["source"] = ep.get_ni_name(ep_name) prot["dest"] = ep_name if ep.array is not None: - prot["array"] = ep.array + prot["arr_dim"] = ep.array prot["arr_idx"] = self.graph.get_node_arr_idx(ep_name) protocol = AXI4Bus(**prot, **protocol.__dict__) sbr_ports.append(protocol) @@ -507,21 +507,22 @@ def compile_nis(self): # 1D array case case (_,): - node_idx = self.graph.get_node_arr_idx(ni_name)[0] - ni_dict["arr_idx"] = SimpleId(id=node_idx) + arr_idx = self.graph.get_node_arr_idx(ni_name) + arr_dim = self.graph.get_node_arr_dim(ni_name) + ni_dict["arr_idx"] = SimpleId(id=arr_idx[0]) if ep_desc.is_sbr(): ni_dict["addr_range"] = [ - rng.model_copy().set_idx(node_idx) for rng in ep_desc.addr_range + rng.model_copy().set_arr(arr_idx, arr_dim) for rng in ep_desc.addr_range ] # 2D array case - case (_, n): - x, y = self.graph.get_node_arr_idx(ni_name) - idx = x * n + y - ni_dict["arr_idx"] = Coord(x=x, y=y) + case (_, _): + arr_idx = self.graph.get_node_arr_idx(ni_name) + arr_dim = self.graph.get_node_arr_dim(ni_name) + ni_dict["arr_idx"] = Coord(x=arr_idx[0], y=arr_idx[1]) if ep_desc.is_sbr(): ni_dict["addr_range"] = [ - rng.model_copy().set_idx(idx) for rng in ep_desc.addr_range + rng.model_copy().set_arr(arr_idx, arr_dim) for rng in ep_desc.addr_range ] # Invalid case case _: @@ -583,6 +584,8 @@ def gen_routing_info(self): f"Routing algorithm {self.routing.route_algo} is not supported yet" ) self.routing.sam = self.gen_sam() + if self.routing.en_multicast: + self.routing.multicast_sam = self.gen_multicast_sam() # Provide the routing info to the network interfaces for ni in self.graph.get_ni_nodes(): ni.routing = self.routing @@ -662,17 +665,31 @@ def gen_sam(self): dest = ni.id if self.routing.xy_id_offset is not None: dest -= self.routing.xy_id_offset - for i, addr_range in enumerate(ni.addr_range): - rule_name = ni.render_enum_name() + for _, addr_range in enumerate(ni.addr_range): + rule_name = ni.endpoint.name if addr_range.desc is not None: rule_name += f"_{addr_range.desc}" - elif len(ni.addr_range) > 1: - rule_name += f"_{i}" - rule_name += "_sam_idx" - addr_rule = RouteMapRule(dest=dest, addr_range=addr_range, desc=rule_name) + addr_rule = RouteMapRule(dest=dest, addr_range=addr_range, en_multicast=addr_range.en_multicast, desc=rule_name) addr_table.append(addr_rule) return RouteMap(name="sam", rules=addr_table) + def gen_multicast_sam(self): + """Generate the multicast system address map, which contains additional mask + information.""" + addr_table = [] + for addr_rule in self.routing.sam.rules: + mask_fields = {} + if addr_rule.addr_range.en_multicast: + mask_offset_x = clog2(addr_rule.addr_range.size) + mask_fields = { + "mask_len": (self.routing.num_x_bits, self.routing.num_y_bits), + "mask_offset": (mask_offset_x + self.routing.num_y_bits, mask_offset_x), + "base_id": (addr_rule.dest.x - addr_rule.addr_range.arr_idx[0], + addr_rule.dest.y - addr_rule.addr_range.arr_idx[1]), + } + addr_table.append(RouteMapRuleMcast(**addr_rule.model_dump(), **mask_fields)) + return RouteMap(name="mcast_sam", rules=addr_table) + def render_ports(self, pkg_name=""): """Render the ports in the generated code.""" ports, declared_ports = [], [] @@ -771,8 +788,9 @@ def render_ep_enum(self): def render_sam_idx_enum(self): """Render the system address map index enum in the generated code.""" fields_dict = {} - for i, desc in enumerate(reversed(self.routing.sam.rules)): - fields_dict[desc.desc] = i + for i, rule in enumerate(reversed(self.routing.sam.rules)): + rule_desc = f"{rule.render_desc()}_sam_idx" + fields_dict[rule_desc] = i return sv_enum_typedef(name="sam_idx_e", fields_dict=fields_dict) def render_network(self): @@ -783,9 +801,9 @@ def render_package(self): """Render the network package in the generated code.""" return self.pkg_tpl.render(noc=self) - def render_rdl(self, rdl_as_mem=False): + def render_rdl(self, rdl_as_mem=False, rdl_memwidth=8): """Render the network RDL in the generated code.""" - return self.rdl_tpl.render(noc=self, rdl_as_mem=rdl_as_mem) + return self.rdl_tpl.render(noc=self, rdl_as_mem=rdl_as_mem, rdl_memwidth=rdl_memwidth) def visualize(self, savefig=True, filename: pathlib.Path = "network.png"): """Visualize the network graph.""" diff --git a/floogen/model/network_interface.py b/floogen/model/network_interface.py index 0281cf4ca..8669d53a3 100644 --- a/floogen/model/network_interface.py +++ b/floogen/model/network_interface.py @@ -5,13 +5,13 @@ # # Author: Tim Fischer -from typing import Optional, ClassVar, List +from typing import Optional, ClassVar, List, Union from importlib.resources import files, as_file from pydantic import BaseModel from mako.lookup import Template -from floogen.model.routing import Id, SimpleId, Coord, AddrRange, Routing, RouteMap +from floogen.model.routing import SimpleId, Coord, AddrRange, Routing, RouteMap from floogen.model.protocol import AXI4 from floogen.model.link import NarrowWideLink, AxiLink from floogen.model.endpoint import EndpointDesc @@ -26,9 +26,9 @@ class NetworkInterface(BaseModel): description: str = "" routing: Routing table: Optional[RouteMap] = None - id: Optional[Id] = None + id: Optional[Union[SimpleId, Coord]] = None uid: Optional[SimpleId] = None - arr_idx: Optional[Id] = None + arr_idx: Optional[Union[SimpleId, Coord]] = None addr_range: Optional[List[AddrRange]] = None def is_sbr(self) -> bool: diff --git a/floogen/model/protocol.py b/floogen/model/protocol.py index dab2332aa..98df7d9a3 100644 --- a/floogen/model/protocol.py +++ b/floogen/model/protocol.py @@ -81,7 +81,7 @@ class AXI4Bus(AXI4): base_name: str source: Union[str, List[str]] dest: Union[str, List[str]] - array: Optional[List[int]] = None + arr_dim: Optional[List[int]] = None arr_idx: Optional[List[int]] = None is_declared: bool = False subtype: str = "" @@ -92,15 +92,15 @@ def _invert_dir(self): def _array_to_sv_array(self): """Convert the array to a SystemVerilog array.""" - if self.array is not None: - return "".join([f"[{i-1}:0]" if i != 1 else "" for i in self.array]) + if self.arr_dim is not None: + return "".join([f"[{i-1}:0]" if i != 1 else "" for i in self.arr_dim]) return "" def _idx_to_sv_idx(self): """Convert the array to a SystemVerilog array.""" if self.arr_idx is not None: string = "" - for idx, val in zip(self.arr_idx, self.array): + for idx, val in zip(self.arr_idx, self.arr_dim): if val != 1: string += f"[{idx}]" return string diff --git a/floogen/model/router.py b/floogen/model/router.py index 0c5c8581e..9bf7aacfb 100644 --- a/floogen/model/router.py +++ b/floogen/model/router.py @@ -13,7 +13,7 @@ from pydantic import BaseModel, ConfigDict, field_validator, model_validator from mako.lookup import Template -from floogen.model.routing import RouteMap, Id, Coord, RouteAlgo +from floogen.model.routing import RouteMap, SimpleId, Coord, RouteAlgo from floogen.model.link import Link import floogen.templates @@ -26,7 +26,7 @@ class RouterDesc(BaseModel): name: str array: Optional[Union[Tuple[int], Tuple[int, int]]] = None tree: Optional[List[int]] = None - xy_id_offset: Optional[Id] = None + xy_id_offset: Optional[Union[SimpleId, Coord]] = None auto_connect: Optional[bool] = True degree: Optional[int] = None @@ -46,6 +46,11 @@ def tree_int_to_tuple(cls, v): return (v,) return v + @field_validator("xy_id_offset", mode="before") + @classmethod + def dict_to_coord_obj(cls, v): + """Convert dict to Coord object.""" + return Coord.from_dict(v) class Router(BaseModel, ABC): """Abstract router class of an actual router""" diff --git a/floogen/model/routing.py b/floogen/model/routing.py index f245baebb..3e648c349 100644 --- a/floogen/model/routing.py +++ b/floogen/model/routing.py @@ -6,8 +6,7 @@ # Author: Tim Fischer from enum import Enum -from typing import Optional, List, Tuple -from abc import ABC, abstractmethod +from typing import Optional, List, Tuple, Union from pydantic import BaseModel, Field, ConfigDict, model_validator, field_validator @@ -65,25 +64,7 @@ def __str__(self): def __int__(self): return self.value -class Id(BaseModel, ABC): - """ID class.""" - - @abstractmethod - def render(self): - """Declare the Id generated code.""" - - @classmethod - def __get_validators__(cls): - yield cls.validate - - @classmethod - def validate(cls, value): - if not issubclass(value, Id): - raise ValueError("Invalid Object") - return value - - -class SimpleId(Id): +class SimpleId(BaseModel): """ID class.""" id: int @@ -118,7 +99,7 @@ def render(self, as_index=False): return f"[{self.id}]" -class Coord(Id): +class Coord(BaseModel): """2D coordinate class.""" x: int @@ -143,6 +124,17 @@ def __lt__(self, other): return self.port_id < other.port_id return False + @staticmethod + def from_dict(coord_dict: dict): + """Create a Coord object from a dictionary.""" + if isinstance(coord_dict, dict): + return Coord( + x=coord_dict.get("x", 0), + y=coord_dict.get("y", 0), + port_id=coord_dict.get("port_id", 0) + ) + return None + def render(self, as_index=False): """Render the SystemVerilog coordinate.""" if not as_index: @@ -168,15 +160,17 @@ def get_dir(node, neighbor) -> XYDirections: class AddrRange(BaseModel): """Address range class.""" - model_config = ConfigDict(extra="forbid") + model_config = ConfigDict(extra="forbid", validate_assignement=True) start: int = Field(ge=0) end: int = Field(ge=0) size: int base: Optional[int] = None - idx: Optional[int] = None - desc: Optional[str] = None + arr_idx: Optional[Tuple[int, ...]] = None + arr_dim: Optional[Tuple[int, ...]] = None rdl_name: Optional[str] = None + en_multicast: bool = False + desc: Optional[str] = None def __str__(self): return f"[{self.start:X}:{self.end:X}]" @@ -188,9 +182,18 @@ def validate_input(self): raise ValueError("Invalid address range specification") addr_dict = {k: v for k, v in self.items() if v is not None} match addr_dict: - case {"size": size, "base": base, "idx": idx}: - addr_dict["start"] = base + size * idx - addr_dict["end"] = addr_dict["start"] + size + case {"size": size, "base": base, "arr_idx": arr_idx}: + match arr_idx: + case (m,): + addr_dict["start"] = base + size * m + addr_dict["end"] = addr_dict["start"] + size + case (m, n): + if addr_dict["arr_dim"] is None: + raise ValueError("Array dimension must be specified for 2D arrays") + addr_dict["start"] = base + size * (m * addr_dict["arr_dim"][1] + n) + addr_dict["end"] = addr_dict["start"] + size + case _: + raise ValueError("Invalid array index specification") case {"size": size, "base": base}: addr_dict["start"] = base addr_dict["end"] = base + size @@ -212,11 +215,16 @@ def validate_output(self): raise ValueError("Address range start must be less than end") return self - def set_idx(self, idx): + def set_arr(self, arr_idx, arr_dim): """Update the address range with the given index.""" - self.idx = idx + self.arr_idx = arr_idx + self.arr_dim = arr_dim if self.base is not None: - self.start = self.base + self.size * idx + match arr_idx: + case (m,): + self.start = self.base + self.size * m + case (m, n): + self.start = self.base + self.size * (m * arr_dim[1] + n) self.end = self.start + self.size else: raise ValueError("Address range base not set") @@ -228,7 +236,7 @@ class RouteMapRule(BaseModel): model_config = ConfigDict(arbitrary_types_allowed=True) - dest: Id + dest: Union[SimpleId, Coord] addr_range: AddrRange desc: Optional[str] = None @@ -240,37 +248,94 @@ def __lt__(self, other): def render(self, aw=None): """Render the SystemVerilog routing rule.""" + struct_fields = { + "idx": self.dest.render(), + "start_addr": self.addr_range.start, + "end_addr": self.addr_range.end + } if aw is not None: - return ( - f"'{{idx: {self.dest.render()}, " - f"start_addr: {aw}'h{self.addr_range.start:0{cdiv(aw,4)}x}, " - f"end_addr: {aw}'h{self.addr_range.end:0{cdiv(aw,4)}x}}}" - ) - return ( - f"'{{idx: {self.dest.render()}, " - f"start_addr: {self.addr_range.start}, " - f"end_addr: {self.addr_range.end}}}" - ) + # Routing table use simple integers, and don't have any address width + struct_fields["start_addr"] = f"{aw}'h{self.addr_range.start:0{cdiv(aw,4)}x}" + struct_fields["end_addr"] = f"{aw}'h{self.addr_range.end:0{cdiv(aw,4)}x}" + + return sv_struct_render(struct_fields) + + def render_desc(self): + '''Render the description of the routing rule.''' + rule_desc = self.desc + match self.addr_range.arr_idx: + case (m,): + rule_desc += f"_{m}" + case (m, n): + rule_desc += f"_x{m}_y{n}" + case _: + pass + return rule_desc - def get_rdl(self, instance_name, rdl_as_mem=False): + def get_rdl(self, instance_name, rdl_as_mem=False, rdl_memwidth=8): """Render the SystemRDL routing rule.""" if self.addr_range.rdl_name is not None: - return [{"start_addr": self.addr_range.start, + return [ + { + "start_addr": self.addr_range.start, + "size": self.addr_range.size, "rdl_name": self.addr_range.rdl_name, - "instance_name": instance_name}] + "instance_name": instance_name, + "arr_dim": self.addr_range.arr_dim, + } + ] if rdl_as_mem: - return [{"start_addr": self.addr_range.start, - "rdl_name": f"external mem {{ \ -mementries = 0x{(self.addr_range.end - self.addr_range.start):X}; memwidth = 8; }}", - "instance_name": instance_name}] + mementries = (self.addr_range.end - self.addr_range.start) // rdl_memwidth * 8 + mem_string = ( + f"external mem {{ mementries = 0x{mementries:X}; memwidth = {rdl_memwidth}; }}" + ) + return [ + { + "start_addr": self.addr_range.start, + "size": self.addr_range.size, + "rdl_name": mem_string, + "instance_name": instance_name, + "arr_dim": self.addr_range.arr_dim, + } + ] return [] +class RouteMapRuleMcast(RouteMapRule): + """Routing rule class for multicast information.""" + + mask_offset: Optional[Tuple[int, int]] = None + mask_len: Optional[Tuple[int, int]] = None + base_id: Optional[Tuple[int, int]] = None + + def render(self, aw=None): + """Render the SystemVerilog routing rule.""" + if aw is None: + raise ValueError("Address width must be specified for multicast routing") + + # In multicast, the `idx` field becomes a nested structure + # where the `id` is the original `idx` + struct_fields = { + "idx": {"id": self.dest.render()}, + "start_addr": f"{aw}'h{self.addr_range.start:0{cdiv(aw,4)}x}", + "end_addr": f"{aw}'h{self.addr_range.end:0{cdiv(aw,4)}x}", + } + + # Non-multicast nodes, don't need any mask information + if self.mask_offset is None: + struct_fields["idx"]["mask_x"] = {"default": "'0"} + struct_fields["idx"]["mask_y"] = {"default": "'0"} + else: + struct_fields["idx"]["mask_x"] = {"offset": self.mask_offset[0], "len": self.mask_len[0], "base_id": self.base_id[0]} + struct_fields["idx"]["mask_y"] = {"offset": self.mask_offset[1], "len": self.mask_len[1], "base_id": self.base_id[1]} + + return sv_struct_render(struct_fields) + class RouteRule(BaseModel): """Routing rule class.""" route: Optional[List[Tuple[int, int]]] - id: Id + id: Union[SimpleId, Coord] desc: Optional[str] = None def render(self, num_route_bits): @@ -416,8 +481,17 @@ def render(self, aw=None): string += sv_param_decl(f"{snake_to_camel(self.name)}NumRules", len(rules)) + "\n" addr_type = f"logic [{aw-1}:0]" if aw is not None else "id_t" rule_type_dict = {} - rule_type_dict = {"idx": "id_t", "start_addr": addr_type, "end_addr": addr_type} - string += sv_struct_typedef(self.rule_type(), rule_type_dict) + if not isinstance(rules[0], RouteMapRuleMcast): + rule_type_dict = {"idx": "id_t", "start_addr": addr_type, "end_addr": addr_type} + string += sv_struct_typedef(self.rule_type(), rule_type_dict) + else: + rule_type_dict = {"offset": "int unsigned", "len": "int unsigned", "base_id": "int unsigned"} + string += sv_struct_typedef("mask_sel_t", rule_type_dict) + rule_type_dict = {"id": "id_t", "mask_x": "mask_sel_t", "mask_y": "mask_sel_t"} + string += sv_struct_typedef("mcast_idx_t", rule_type_dict) + rule_type_dict = {"idx": "mcast_idx_t", "start_addr": addr_type, "end_addr": addr_type} + string += sv_struct_typedef(self.rule_type(), rule_type_dict) + rules_str = "" if not rules: string += sv_param_decl( @@ -430,7 +504,7 @@ def render(self, aw=None): rules_str += f"{rule.render(aw)}" rules_str += ',' if i != len(rules) - 1 else ' ' if rule.desc is not None: - rules_str += f"// {rule.desc}\n" + rules_str += f"// {snake_to_camel(rule.render_desc())}\n" string += sv_param_decl( f"{snake_to_camel(self.name)}", value="'{\n" + rules_str + "\n}", @@ -439,19 +513,37 @@ def render(self, aw=None): ) return string - def render_rdl(self, rdl_as_mem=False): + def render_rdl(self, rdl_as_mem=False, rdl_memwidth=8): """Render the SystemRDL addrmap internals.""" string = "" rules = self.rules.copy() rdl_setups = [] for i, rule in enumerate(rules): + match rule.addr_range.arr_idx: + case None: + pass + case (m,) if m != 0: + continue + case (m, n) if m != 0 or n != 0: + continue block_name = f"{self.name}_{i}" if rule.desc is not None: block_name = rule.desc - rdl_setups.extend(rule.get_rdl(f"{block_name}", rdl_as_mem)) + rdl_setups.extend(rule.get_rdl(f"{block_name}", rdl_as_mem, rdl_memwidth)) newlist = sorted(rdl_setups, key=lambda d: d['start_addr']) for item in newlist: - string += f" {item['rdl_name']} {item['instance_name']} @0x{item['start_addr']:X};\n" + string += f" {item['rdl_name']} {item['instance_name']}" + match item['arr_dim']: + case (m,): + string += f"[{m}]" + case (m, n): + string += f"[{m*n}]" + case _: + pass + string += f" @0x{item['start_addr']:X}" + if item['arr_dim'] is not None: + string += f" += 0x{item['size']:X}" + string += ";\n" return string def render_rdl_inc(self): @@ -484,7 +576,7 @@ class Routing(BaseModel): sam: Optional[RouteMap] = None table: Optional[RouteMap] = None addr_offset_bits: Optional[int] = None - xy_id_offset: Optional[Id] = None + xy_id_offset: Optional[Union[SimpleId, Coord]] = None num_endpoints: Optional[int] = None num_id_bits: Optional[int] = None num_x_bits: Optional[int] = None @@ -494,6 +586,11 @@ class Routing(BaseModel): rob_idx_bits: int = 1 port_id_bits: int = 1 num_vc_id_bits: int = 0 + en_multicast: bool = False + multicast_sam: Optional[RouteMap] = None + en_parallel_reduction: bool = False + en_narrow_offload_reduction: bool = False + en_wide_offload_reduction: bool = False @field_validator("route_algo", mode="before") @classmethod @@ -503,6 +600,28 @@ def validate_route_algo(cls, v): v = RouteAlgo[v] return v + @model_validator(mode="after") + def validate_collective(self): + """Reduction can be supported with multicast only.""" + if not self.en_multicast and ( + self.en_parallel_reduction or + self.en_narrow_offload_reduction or + self.en_wide_offload_reduction + ): + raise ValueError( + "Multicast must be enabled to use any reduction feature " + ) + return self + + @model_validator(mode="after") + def validate_multicast_route_algo(self): + """Multicast is supported with XY routing only""" + if self.en_multicast and self.route_algo != RouteAlgo.XY: + raise ValueError( + "Multicast is only supported with XY routing algorithm, " + f"but got {self.route_algo}" + ) + return self def render_param_decl(self) -> str: """Render the SystemVerilog parameter declaration.""" string = "" @@ -563,6 +682,18 @@ def render_hdr_typedef(self, network_type) -> str: ch_type = "axi_ch_e" if network_type == "axi" else "nw_ch_e" if self.num_vc_id_bits == 0: + if self.en_multicast: + if ( self.en_parallel_reduction + or self.en_narrow_offload_reduction + or self.en_wide_offload_reduction + ): + return ( + f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t," + f"id_t, collect_comm_e, reduction_op_t)") + + return ( + f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t," + f"id_t, collect_comm_e)") return f"`FLOO_TYPEDEF_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t)" return f"`FLOO_TYPEDEF_VC_HDR_T(hdr_t, {dst_type}, id_t, {ch_type}, rob_idx_t, vc_id_t)" @@ -578,5 +709,9 @@ def render_route_cfg(self, name) -> str: self.route_algo == RouteAlgo.ID and not self.use_id_table else 0, "NumSamRules": len(self.sam), "NumRoutes": self.num_endpoints if self.route_algo == RouteAlgo.SRC else 0, + "EnMultiCast": bool_to_sv(self.en_multicast), + "EnParallelReduction": bool_to_sv(self.en_parallel_reduction), + "EnNarrowOffloadReduction": bool_to_sv(self.en_narrow_offload_reduction), + "EnWideOffloadReduction": bool_to_sv(self.en_wide_offload_reduction) } return sv_param_decl(name, sv_struct_render(fields), dtype="route_cfg_t") diff --git a/floogen/templates/floo_addrmap.rdl.mako b/floogen/templates/floo_addrmap.rdl.mako index 9ea832a63..009e3b123 100644 --- a/floogen/templates/floo_addrmap.rdl.mako +++ b/floogen/templates/floo_addrmap.rdl.mako @@ -11,6 +11,6 @@ ${noc.routing.sam.render_rdl_inc()} addrmap ${noc.name}_addrmap { -${noc.routing.sam.render_rdl(rdl_as_mem)} +${noc.routing.sam.render_rdl(rdl_as_mem, rdl_memwidth)} }; diff --git a/floogen/templates/floo_top_noc_pkg.sv.mako b/floogen/templates/floo_top_noc_pkg.sv.mako index 26bddbe05..c027fcdc5 100644 --- a/floogen/templates/floo_top_noc_pkg.sv.mako +++ b/floogen/templates/floo_top_noc_pkg.sv.mako @@ -26,6 +26,9 @@ package floo_${noc.name}_noc_pkg; % if noc.routing.use_id_table: ${noc.routing.sam.render(aw=noc.routing.addr_width)} + % if noc.routing.en_multicast: + ${noc.routing.multicast_sam.render(aw=noc.routing.addr_width)} + %endif % else: localparam int unsigned NumSamRules = 1; typedef logic sam_rule_t; diff --git a/floogen/tests/address_test.py b/floogen/tests/address_test.py index 81c402347..7ddc2b82f 100644 --- a/floogen/tests/address_test.py +++ b/floogen/tests/address_test.py @@ -16,7 +16,8 @@ def test_addr_range_creation1(): assert addr_range.end == 50 assert addr_range.size == 50 assert addr_range.base is None - assert addr_range.idx is None + assert addr_range.arr_idx is None + assert addr_range.arr_dim is None def test_addr_range_creation2(): @@ -26,17 +27,18 @@ def test_addr_range_creation2(): assert addr_range.end == 150 assert addr_range.size == 100 assert addr_range.base is None - assert addr_range.idx is None + assert addr_range.arr_idx is None def test_addr_range_creation3(): """Test the creation of an AddrRange object.""" - addr_range = AddrRange(base=50, size=100, idx=5) + addr_range = AddrRange(base=50, size=100, arr_idx=(5,)) assert addr_range.start == 550 assert addr_range.end == 650 assert addr_range.size == 100 assert addr_range.base == 50 - assert addr_range.idx == 5 + assert addr_range.arr_idx == (5,) + assert addr_range.arr_dim is None def test_addr_range_creation4(): @@ -46,18 +48,20 @@ def test_addr_range_creation4(): assert addr_range.end == 150 assert addr_range.size == 100 assert addr_range.base == 50 - assert addr_range.idx is None + assert addr_range.arr_idx is None + assert addr_range.arr_dim is None -def test_addr_range_set_idx(): - """Test the set_idx method of an AddrRange object.""" +def test_addr_range_arr_idx(): + """Test the arr_idx method of an AddrRange object.""" addr_range = AddrRange(base=50, size=100) - addr_range.set_idx(1) + addr_range.set_arr((1, ), (5, )) assert addr_range.start == 150 assert addr_range.end == 250 assert addr_range.size == 100 assert addr_range.base == 50 - assert addr_range.idx == 1 + assert addr_range.arr_idx == (1,) + assert addr_range.arr_dim == (5,) def test_invalid_addr_range(): @@ -70,7 +74,7 @@ def test_invalid_addr_range(): with pytest.raises(ValueError): addr_range = AddrRange(start=0, end=100, size=100) - addr_range.set_idx(2) + addr_range.set_arr(2, 5) def test_routing_table_len(): """Test the length of a RoutingTable object.""" diff --git a/floogen/utils.py b/floogen/utils.py index 24174c3fc..f8a45df20 100644 --- a/floogen/utils.py +++ b/floogen/utils.py @@ -11,38 +11,114 @@ from typing import Union, List -def cdiv(x, y) -> int: - """Returns the ceiling of x/y.""" +def cdiv(x: Union[int, float], y: Union[int, float]) -> int: + """Compute the ceiling of x / y. + + Examples: + >>> cdiv(7, 2) + 4 + + Args: + x (int, float): Numerator. + y (int, float): Denominator. + + Returns: + int: Ceiling of x / y. + """ return -(-x // y) -def clog2(x) -> int: - """Returns the ceiling of log2(x).""" +def clog2(x: Union[int, float]) -> int: + """Returns the ceiling of log2(x). + + Examples: + >>> clog2(7) + 3 + + Args: + x (int): Input value. + + Returns: + int: Ceiling of log2(x). + """ + return math.ceil(math.log2(x)) def camel_to_snake(name: str) -> str: - """Converts a camel case string to snake case.""" + """Converts a camel case string to snake case. + + Examples: + >>> camel_to_snake("CamelCase") + 'camel_case' + + Args: + name (str): Input camel case string. + + Returns: + str: Converted snake case string. + """ return "".join(["_" + i.lower() if i.isupper() else i for i in name]).lstrip("_") def snake_to_camel(name: str) -> str: - """Converts a snake case string to camel case.""" + """Converts a snake case string to camel case. + + Examples: + >>> snake_to_camel("snake_case") + 'SnakeCase' + + Args: + name (str): Input snake case string. + + Returns: + str: Converted camel case string. + """ return "".join([i.capitalize() for i in name.split("_")]) def short_dir(direction: str) -> str: - """Returns the short direction string.""" + """Returns the short direction string. + + Args: + direction (str): "input" or "output". + + Returns: + str: "in" or "out". + """ return "in" if direction == "input" else "out" def bool_to_sv(value: bool) -> str: - """Converts a boolean to a SystemVerilog string.""" + """Converts a boolean to a SystemVerilog string. + + Examples: + >>> bool_to_sv(True) + "1'b1" + + Args: + value (bool): Input boolean value. + + Returns: + str: "1'b1" if True, "1'b0" if False. + """ return "1'b1" if value else "1'b0" def int_to_hex(value: int, width: int) -> str: - """Converts an integer to a hex string.""" + """Converts an integer to a hex string. + + Examples: + >>> int_to_hex(255, 8) + "8'hff" + + Args: + value (int): Input integer value. + width (int): Bit width of the value. + + Returns: + str: Hex string representation of the integer. + """ return f"{width}'h{value:0{width//4}x}" @@ -53,7 +129,24 @@ def sv_param_decl( dtype: str = "int unsigned", array_size: Union[int, str, List[Union[int, str]]] = None, ) -> str: - """Declare a SystemVerilog parameter.""" + """Declare a SystemVerilog parameter. + + Examples: + >>> sv_param_decl("Width", 8) + "localparam int unsigned Width = 8;" + >>> sv_param_decl("Depth", 16, ptype="parameter", dtype="my_type_t", array_size=4) + "parameter my_type_t [3:0] Depth = 16;" + + Args: + name (str): Name of the parameter. + value (int, str): Value of the parameter. + ptype (str, optional): Type of the parameter, either "localparam" or "parameter". Defaults to "localparam". + dtype (str, optional): Data type of the parameter. Defaults to "int unsigned". + array_size (int, str, list, optional): Size of the array. Can be an integer, a string (for expressions), or a list of integers/strings for multi-dimensional arrays. Defaults to None. + + Returns: + str: SystemVerilog parameter declaration. + """ assert ptype in ["localparam", "parameter"] def _array_fmt(size): if isinstance(size, int): @@ -71,7 +164,20 @@ def _array_fmt(size): def sv_typedef(name: str, dtype: str = "logic", array_size: int = None) -> str: - """Declare a SystemVerilog typedef.""" + """Declare a SystemVerilog typedef. + + Examples: + >>> sv_typedef("my_type_t", "logic", 8) + "typedef logic[7:0] my_type_t;" + + Args: + name (str): Name of the typedef. + dtype (str, optional): Data type of the typedef. Defaults to "logic". + array_size (int, optional): Size of the array. If None, a scalar type is declared. Defaults to None. + + Returns: + str: SystemVerilog typedef declaration. + """ assert array_size is None or isinstance(array_size, int) if array_size is None: return f"typedef {dtype} {name};\n" @@ -90,14 +196,59 @@ def sv_struct_typedef(name: str, fields: dict, union=False) -> str: return typedef def sv_struct_render(fields: dict) -> str: - """Declare a SystemVerilog struct.""" + """Declare a SystemVerilog struct based on a (nested) dictionary, + where they keys of the dictionary are the field names, and the values are + the actual values to assign. + + Examples: + >>> sv_struct_render({'field1': '3'd0', 'field2': 'some_signal'}) + "'{field1: 3'd0,field2: some_signal}'" + >>> sv_struct_render({'field1': '3'd0', 'field2': {'subfield1': 'some_signal', 'subfield2': 'SomeParam'}}) + "'{ + field1: 3'd0, + field2: '{ + subfield1: some_signal, + subfield2: SomeParam + } + }" + + Args: + fields (dict): Dictionary of field names and their corresponding values. + + Returns: + str: SystemVerilog struct instantiation. + """ decl = "'{" for field, value in fields.items(): + # If the `value` itself is a dict, recursively render it as a struct + if isinstance(value, dict): + value = sv_struct_render(value) decl += f" {field}: {value},\n" return decl[:-2] + "}" def sv_enum_typedef(name: str, fields_dict: dict=None, fields_list: list=None) -> str: - """Declare a SystemVerilog enum typedef.""" + """Declare a SystemVerilog enum typedef. + + Examples: + >>> sv_enum_typedef("my_enum_e", fields_list=["field_one", "field_two"]) + "typedef enum logic[0:0] { + FieldOne = 0, + FieldTwo = 1 + } my_enum_e;" + >>> sv_enum_typedef("my_enum_e", fields_dict={"field_one": 4, "field_two": 6}) + "typedef enum logic[2:0] { + FieldOne = 4, + FieldTwo = 6 + } my_enum_e;" + + Args: + name (str): Name of the enum typedef. + fields_dict (dict, optional): Dictionary of field names and their corresponding values. Defaults to None. + fields_list (list, optional): List of field names. Values will be assigned automatically starting from 0. Defaults to None. + + Returns: + str: SystemVerilog enum typedef declaration. + """ if fields_dict is not None: bitwidth = clog2(max(fields_dict.values()) + 1) typedef = f"typedef enum logic[{bitwidth-1}:0] {{\n" @@ -116,7 +267,18 @@ def sv_enum_typedef(name: str, fields_dict: dict=None, fields_list: list=None) - def verible_format(string: str, verible_fmt_bin=None, verible_fmt_args=None) -> str: - """Format the string using verible-verilog-format.""" + """Format the string using verible-verilog-format. + + Args: + string (str): Input string to format. + verible_fmt_bin (str, optional): Path to the verible-verilog-format binary. + If None, it will try to find it in the PATH. Defaults to None. + verible_fmt_args (str, optional): Additional arguments to pass to verible-verilog-format. + If None, no additional arguments are passed. Defaults to None. + + Returns: + str: Formatted string, or the original string if verible-verilog-format is not found. + """ if verible_fmt_bin is None: verible_fmt_bin = shutil.which("verible-verilog-format") # Fallback to `which` if verible_fmt_bin is None: diff --git a/hw/floo_axi_chimney.sv b/hw/floo_axi_chimney.sv index 275dd7584..2a372a096 100644 --- a/hw/floo_axi_chimney.sv +++ b/hw/floo_axi_chimney.sv @@ -3,10 +3,12 @@ // SPDX-License-Identifier: SHL-0.51 // // Tim Fischer +// Lorenzso Leone `include "common_cells/registers.svh" `include "common_cells/assertions.svh" `include "axi/typedef.svh" +`include "axi/assign.svh" `include "floo_noc/typedef.svh" /// A bidirectional network interface for connecting AXI4 Buses to the NoC @@ -45,6 +47,11 @@ module floo_axi_chimney #( /// The System Address Map (SAM) rules /// (only used if `RouteCfg.UseIdTable == 1'b1`) parameter sam_rule_t [RouteCfg.NumSamRules-1:0] Sam = '0, + /// SAM Index type to support multicast info + parameter type sam_idx_t = id_t, + /// Struct consisting of offset and len to speficy the position of the mask bits + /// (only used if `EnMultiCast && RouteCfg.UseIdTable == 1'b1 && RouteCfg.RouteAlgo == XYRouting`) + parameter type mask_sel_t = logic, /// AXI manager request channel type parameter type axi_in_req_t = logic, /// AXI manager response channel type @@ -58,7 +65,15 @@ module floo_axi_chimney #( /// Floo `rsp` link type parameter type floo_rsp_t = logic, /// SRAM configuration type - parameter type sram_cfg_t = logic + parameter type sram_cfg_t = logic, + /// Struct to interpret the multicast mask in the user bits. Only used if `EnMultiCast == 1'b1`. + /// It expects at least a field `mask`, which has the same size as the address: + /// typedef struct packed { + /// logic [AxiCfg.AddrWidth-1:0] mask; + /// logic [AxiCfg.UserWidth-1:0] user; + /// } user_struct_t; + /// The `mask` field will not be transported over the NoC, while the `user` field will be. + parameter type user_struct_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -97,16 +112,23 @@ module floo_axi_chimney #( `AXI_TYPEDEF_AW_CHAN_T(axi_out_aw_chan_t, axi_addr_t, axi_out_id_t, axi_user_t) `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi, AxiCfg, hdr_t) + // Type of the mask encoded in the user field. + // It's always equal to the address field. + // For future extension, add an extra opcode in the user_struct_t + typedef axi_addr_t user_mask_t ; + // Duplicate AXI port signals to degenerate ports // in case they are not used axi_req_t axi_req_in; axi_rsp_t axi_rsp_out; + user_mask_t axi_req_in_mask; // AX queue axi_aw_chan_t axi_aw_queue; axi_ar_chan_t axi_ar_queue; logic axi_aw_queue_valid_out, axi_aw_queue_ready_in; logic axi_ar_queue_valid_out, axi_ar_queue_ready_in; + user_mask_t axi_mask_queue; // AXI req/rsp arbiter floo_req_chan_t [AxiW:AxiAr] floo_req_arb_in; @@ -156,8 +178,10 @@ module floo_axi_chimney #( // Routing dst_t [NumAxiChannels-1:0] dst_id; dst_t axi_aw_id_q; - route_t [NumAxiChannels-1:0] route_out; + id_t [NumAxiChannels-1:0] mcast_mask; + id_t axi_aw_mask_q; id_t [NumAxiChannels-1:0] id_out; + id_t [NumAxiChannels-1:0] mask_id; meta_buf_t aw_out_hdr_in, aw_out_hdr_out; meta_buf_t ar_out_hdr_in, ar_out_hdr_out; @@ -167,9 +191,19 @@ module floo_axi_chimney #( /////////////////////// if (ChimneyCfg.EnMgrPort) begin : gen_sbr_port - - assign axi_req_in = axi_in_req_i; - assign axi_in_rsp_o = axi_rsp_out; + // We cast the incoming AXI types to the ones that are actually transported + // If multicast is enabled, the bits holding the mask are dropped. + `AXI_ASSIGN_REQ_STRUCT(axi_req_in, axi_in_req_i) + `AXI_ASSIGN_RESP_STRUCT(axi_in_rsp_o, axi_rsp_out) + + // Extract the multicast mask bits from the AXI user bits + if (RouteCfg.EnMultiCast) begin : gen_mask + user_struct_t user; + assign user = axi_in_req_i.aw.user; + assign axi_req_in_mask = user.mcast_mask; + end else begin : gen_no_mask + assign axi_req_in_mask = '0; + end if (ChimneyCfg.CutAx) begin : gen_ax_cuts spill_register #( @@ -197,14 +231,30 @@ module floo_axi_chimney #( .valid_o ( axi_ar_queue_valid_out ), .ready_i ( axi_ar_queue_ready_in ) ); + if (RouteCfg.EnMultiCast) begin : gen_mask_cuts + spill_register #( + .T (logic [AxiCfg.UserWidth-1:0]) + ) i_usermask_queue ( + .clk_i, + .rst_ni, + .data_i ( axi_req_in_mask ), + .valid_i ( axi_req_in.aw_valid ), + .ready_o ( ), + .data_o ( axi_mask_queue ), + .valid_o ( ), + .ready_i ( axi_aw_queue_ready_in ) + ); + end else begin : gen_no_mask_cuts + assign axi_mask_queue = '0; + end end else begin : gen_no_ax_cuts assign axi_aw_queue = axi_in_req_i.aw; assign axi_aw_queue_valid_out = axi_in_req_i.aw_valid; assign axi_rsp_out.aw_ready = axi_aw_queue_ready_in; - assign axi_ar_queue = axi_in_req_i.ar; assign axi_ar_queue_valid_out = axi_in_req_i.ar_valid; assign axi_rsp_out.ar_ready = axi_ar_queue_ready_in; + assign axi_mask_queue = axi_req_in_mask; end end else begin : gen_err_slv_port @@ -225,6 +275,7 @@ module floo_axi_chimney #( assign axi_ar_queue = '0; assign axi_aw_queue_valid_out = 1'b0; assign axi_ar_queue_valid_out = 1'b0; + assign axi_mask_queue = '0; end if (ChimneyCfg.CutRsp) begin : gen_rsp_cuts @@ -264,7 +315,9 @@ module floo_axi_chimney #( logic aw_out_queue_valid, aw_out_queue_ready; - axi_out_aw_chan_t axi_aw_queue_out; + axi_out_aw_chan_t axi_aw_queue_out, axi_aw_queue_in; + + `AXI_ASSIGN_AW_STRUCT(axi_aw_queue_in, meta_buf_req_out.aw) // Since AW and W are transferred over the same link, it can happen that // a downstream module does not accept the AW until the W is valid. @@ -276,7 +329,7 @@ module floo_axi_chimney #( .rst_ni ( rst_ni ), .valid_i ( meta_buf_req_out.aw_valid ), .ready_o ( aw_out_queue_ready ), - .data_i ( meta_buf_req_out.aw ), + .data_i ( axi_aw_queue_in ), .valid_o ( aw_out_queue_valid ), .ready_i ( axi_out_rsp_i.aw_ready ), .data_o ( axi_aw_queue_out ) @@ -285,7 +338,7 @@ module floo_axi_chimney #( always_comb begin axi_out_req_o = meta_buf_req_out; axi_out_req_o.aw_valid = aw_out_queue_valid; - axi_out_req_o.aw = axi_aw_queue_out; + `AXI_SET_AW_STRUCT(axi_out_req_o.aw, axi_aw_queue_out); meta_buf_rsp_in = axi_out_rsp_i; meta_buf_rsp_in.aw_ready = aw_out_queue_ready; end @@ -340,7 +393,7 @@ module floo_axi_chimney #( .sram_cfg_i, .ax_valid_i ( aw_rob_valid_in ), .ax_ready_o ( aw_rob_ready_out ), - .ax_len_i ( axi_aw_queue.len ), + .ax_len_i ( '0 ), // B responses are single-beat .ax_id_i ( axi_aw_queue.id ), .ax_dest_i ( id_out[AxiAw] ), .ax_valid_o ( aw_rob_valid_out ), @@ -409,6 +462,8 @@ module floo_axi_chimney #( axi_addr_t [NumAxiChannels-1:0] axi_req_addr; id_t [NumAxiChannels-1:0] axi_rsp_src_id; + user_mask_t [NumAxiChannels-1:0] axi_req_user; + mask_sel_t [NumAxiChannels-1:0] x_mask_sel, y_mask_sel; assign axi_req_addr[AxiAw] = axi_aw_queue.addr; assign axi_req_addr[AxiAr] = axi_ar_queue.addr; @@ -416,66 +471,92 @@ module floo_axi_chimney #( assign axi_rsp_src_id[AxiB] = aw_out_hdr_out.hdr.src_id; assign axi_rsp_src_id[AxiR] = ar_out_hdr_out.hdr.src_id; - for (genvar ch = 0; ch < NumAxiChannels; ch++) begin : gen_route_comp + assign axi_req_user [AxiAw] = axi_mask_queue; + assign axi_req_user [AxiAr] = '0; + + for (genvar ch = 0; ch < NumAxiChannels; ch++) begin : gen_route localparam axi_ch_e Ch = axi_ch_e'(ch); - if (Ch == AxiAw || Ch == AxiAr) begin : gen_req_route_comp + if (Ch == AxiAw || Ch == AxiAr) begin : gen_req_route // Translate the address from AXI requests to a destination ID - // (or route if `SourceRouting` is used) - floo_route_comp #( - .RouteCfg ( RouteCfg ), - .id_t ( id_t ), - .addr_t ( axi_addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) - ) i_floo_req_route_comp ( - .clk_i, - .rst_ni, - .route_table_i, - .addr_map_i ( Sam ), - .id_i ( id_t'('0) ), - .addr_i ( axi_req_addr[ch] ), - .route_o ( route_out[ch] ), - .id_o ( id_out[ch] ) - ); - end else if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting && - (Ch == AxiB || Ch == AxiR)) begin : gen_rsp_route_comp - // Generally, the source ID from the request is used to route back - // the responses. However, in the case of `SourceRouting`, the source ID - // first needs to be translated into a route. - floo_route_comp #( - .RouteCfg ( RouteCfg ), - .UseIdTable ( 1'b0 ), // Overwrite `RouteCfg` - .id_t ( id_t ), - .addr_t ( axi_addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) - ) i_floo_rsp_route_comp ( + floo_id_translation #( + .RouteCfg (RouteCfg), + .Sam (Sam), + .sam_idx_t (sam_idx_t), + .id_t (id_t), + .addr_t (axi_addr_t), + .addr_rule_t(sam_rule_t), + .mask_sel_t (mask_sel_t) + ) i_floo_id_translation ( .clk_i, .rst_ni, - .route_table_i, - .addr_i ( '0 ), - .addr_map_i ( '0 ), - .id_i ( axi_rsp_src_id[ch] ), - .route_o ( route_out[ch] ), - .id_o ( id_out[ch] ) + .valid_i (axi_aw_queue_valid_out), + .addr_i (axi_req_addr[ch]), + .id_o (id_out[ch]), + .mask_addr_x_o (x_mask_sel[ch]), + .mask_addr_y_o (y_mask_sel[ch]) ); + end else if ((Ch == AxiB || Ch == AxiR)) begin : gen_rsp_route + // For responses, the `src_id` from the request is used to route back + // the responses. + assign id_out[ch] = axi_rsp_src_id[ch]; + end else if (Ch == AxiW) begin : gen_w_route + // The destination ID of W's is the previous AW's ID + assign id_out[ch] = axi_aw_id_q; end - end - if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_route_field - assign route_out[AxiW] = axi_aw_id_q; - assign dst_id = route_out; - end else begin : gen_dst_field - assign dst_id[AxiAw] = id_out[AxiAw]; - assign dst_id[AxiAr] = id_out[AxiAr]; - assign dst_id[AxiB] = aw_out_hdr_out.hdr.src_id; - assign dst_id[AxiR] = ar_out_hdr_out.hdr.src_id; - assign dst_id[AxiW] = axi_aw_id_q; + // The actual `dst_id` depends on the routing algorithm + if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_dst_srcroute + // Look up the `route` in the routing table + assign dst_id[ch] = route_table_i[id_out[ch]]; + end else begin : gen_no_dst_srcroute + // Otherwise, assign the destination ID directly + assign dst_id[ch] = id_out[ch]; + end end - `FFL(axi_aw_id_q, dst_id[AxiAw], axi_aw_queue_valid_out && + `FFL(axi_aw_id_q, id_out[AxiAw], axi_aw_queue_valid_out && axi_aw_queue_ready_in, '0) + if (RouteCfg.EnMultiCast) begin : gen_mcast + localparam int unsigned AddrWidth = $bits(axi_addr_t); + axi_addr_t [NumAxiChannels-1:0] x_addr_mask; + axi_addr_t [NumAxiChannels-1:0] y_addr_mask; + + for (genvar ch = 0; ch < NumAxiChannels; ch++) begin : gen_mcast_id_mask + localparam axi_ch_e Ch = axi_ch_e'(ch); + if (Ch == AxiAw) begin : gen_req_mcast_id_mask + // Evaluate the ID Mask according to the info read from the SAM through the flooo_id_translation module + if (RouteCfg.UseIdTable && + RouteCfg.RouteAlgo == floo_pkg::XYRouting) begin: gen_mcast_idtable + assign x_addr_mask[ch] = (({AddrWidth{1'b1}} >> (AddrWidth - x_mask_sel[ch].len)) + << x_mask_sel[ch].offset); + assign y_addr_mask[ch] = (({AddrWidth{1'b1}} >> (AddrWidth - y_mask_sel[ch].len)) + << y_mask_sel[ch].offset); + assign mask_id[ch].x = (axi_req_user[ch] & x_addr_mask[ch]) >> x_mask_sel[ch].offset; + assign mask_id[ch].y = (axi_req_user[ch] & y_addr_mask[ch]) >> y_mask_sel[ch].offset; + assign mask_id[ch].port_id = '0; + end else if (RouteCfg.RouteAlgo == floo_pkg::XYRouting) begin: gen_mcast_noidtable + assign mask_id[ch].x = axi_req_user[ch][RouteCfg.XYAddrOffsetX +: $bits(id_out[ch].x)]; + assign mask_id[ch].y = axi_req_user[ch][RouteCfg.XYAddrOffsetY +: $bits(id_out[ch].y)]; + assign mask_id[ch].port_id = '0; + end else begin: gen_mcast_nosupported + assign mask_id[ch] = '0; // We don't support multicast for other routing algorithms + end + end + end + + assign mcast_mask[AxiAw] = mask_id[AxiAw]; + assign mcast_mask[AxiAr] = '0; + assign mcast_mask[AxiW] = axi_aw_mask_q; + assign mcast_mask[AxiR] = ar_out_hdr_out.hdr.mask; + assign mcast_mask[AxiB] = aw_out_hdr_out.hdr.mask; + + `FFL(axi_aw_mask_q, mcast_mask[AxiAw], axi_aw_queue_valid_out && + axi_aw_queue_ready_in, '0) + end else begin: gen_no_mcast_mask + assign mcast_mask = '0; + end + /////////////////// // FLIT PACKING // /////////////////// @@ -485,11 +566,13 @@ module floo_axi_chimney #( floo_axi_aw.hdr.rob_req = aw_rob_req_out; floo_axi_aw.hdr.rob_idx = aw_rob_idx_out; floo_axi_aw.hdr.dst_id = dst_id[AxiAw]; + floo_axi_aw.hdr.mask = mcast_mask[AxiAw]; floo_axi_aw.hdr.src_id = id_i; floo_axi_aw.hdr.last = 1'b0; floo_axi_aw.hdr.axi_ch = AxiAw; floo_axi_aw.hdr.atop = axi_aw_queue.atop != axi_pkg::ATOP_NONE; floo_axi_aw.payload = axi_aw_queue; + floo_axi_aw.hdr.commtype = (mcast_mask[AxiAw] != '0)? Multicast : Unicast; end always_comb begin @@ -497,10 +580,12 @@ module floo_axi_chimney #( floo_axi_w.hdr.rob_req = aw_rob_req_out; floo_axi_w.hdr.rob_idx = aw_rob_idx_out; floo_axi_w.hdr.dst_id = dst_id[AxiW]; + floo_axi_w.hdr.mask = mcast_mask[AxiW]; floo_axi_w.hdr.src_id = id_i; floo_axi_w.hdr.last = axi_req_in.w.last; floo_axi_w.hdr.axi_ch = AxiW; floo_axi_w.payload = axi_req_in.w; + floo_axi_w.hdr.commtype = (mcast_mask[AxiW] != '0)? Multicast : Unicast; end always_comb begin @@ -508,10 +593,12 @@ module floo_axi_chimney #( floo_axi_ar.hdr.rob_req = ar_rob_req_out; floo_axi_ar.hdr.rob_idx = ar_rob_idx_out; floo_axi_ar.hdr.dst_id = dst_id[AxiAr]; + floo_axi_ar.hdr.mask = mcast_mask[AxiAr]; floo_axi_ar.hdr.src_id = id_i; floo_axi_ar.hdr.last = 1'b1; floo_axi_ar.hdr.axi_ch = AxiAr; floo_axi_ar.payload = axi_ar_queue; + floo_axi_ar.hdr.commtype = '0; end always_comb begin @@ -519,12 +606,15 @@ module floo_axi_chimney #( floo_axi_b.hdr.rob_req = aw_out_hdr_out.hdr.rob_req; floo_axi_b.hdr.rob_idx = aw_out_hdr_out.hdr.rob_idx; floo_axi_b.hdr.dst_id = dst_id[AxiB]; + floo_axi_b.hdr.mask = mcast_mask[AxiB]; floo_axi_b.hdr.src_id = id_i; floo_axi_b.hdr.last = 1'b1; floo_axi_b.hdr.axi_ch = AxiB; floo_axi_b.hdr.atop = aw_out_hdr_out.hdr.atop; floo_axi_b.payload = meta_buf_rsp_out.b; floo_axi_b.payload.id = aw_out_hdr_out.id; + floo_axi_b.hdr.commtype = (aw_out_hdr_out.hdr.commtype == Multicast)? + ParallelReduction : Unicast; end always_comb begin @@ -532,12 +622,14 @@ module floo_axi_chimney #( floo_axi_r.hdr.rob_req = ar_out_hdr_out.hdr.rob_req; floo_axi_r.hdr.rob_idx = ar_out_hdr_out.hdr.rob_idx; floo_axi_r.hdr.dst_id = dst_id[AxiR]; + floo_axi_r.hdr.mask = mcast_mask[AxiR]; floo_axi_r.hdr.src_id = id_i; floo_axi_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts floo_axi_r.hdr.axi_ch = AxiR; floo_axi_r.hdr.atop = ar_out_hdr_out.hdr.atop; floo_axi_r.payload = meta_buf_rsp_out.r; floo_axi_r.payload.id = ar_out_hdr_out.id; + floo_axi_r.hdr.commtype = '0; end always_comb begin @@ -685,15 +777,23 @@ module floo_axi_chimney #( .MaxUniqueIds ( ChimneyCfg.MaxUniqueIds ), .AtopSupport ( AtopSupport ), .MaxAtomicTxns ( MaxAtomicTxns ), + .Sam ( Sam ), .buf_t ( meta_buf_t ), - .axi_in_req_t ( axi_in_req_t ), - .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_in_req_t ( axi_req_t ), + .axi_in_rsp_t ( axi_rsp_t ), .axi_out_req_t ( axi_out_req_t ), - .axi_out_rsp_t ( axi_out_rsp_t ) + .axi_out_rsp_t ( axi_out_rsp_t ), + .RouteCfg ( RouteCfg ), + .addr_t ( axi_addr_t ), + .sam_rule_t ( sam_rule_t ), + .id_t ( id_t ), + .sam_idx_t ( sam_idx_t ), + .mask_sel_t ( mask_sel_t ) ) i_floo_meta_buffer ( .clk_i, .rst_ni, .test_enable_i, + .id_i ( id_i ), .axi_req_i ( meta_buf_req_in ), .axi_rsp_o ( meta_buf_rsp_out ), .axi_req_o ( meta_buf_req_out ), @@ -707,8 +807,8 @@ module floo_axi_chimney #( axi_err_slv #( .AxiIdWidth ( AxiCfg.InIdWidth ), .ATOPs ( AtopSupport ), - .axi_req_t ( axi_in_req_t ), - .axi_resp_t ( axi_in_rsp_t ) + .axi_req_t ( axi_req_t ), + .axi_resp_t ( axi_rsp_t ) ) i_axi_err_slv ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/hw/floo_id_translation.sv b/hw/floo_id_translation.sv new file mode 100644 index 000000000..1743520ac --- /dev/null +++ b/hw/floo_id_translation.sv @@ -0,0 +1,84 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer +// Lorenzo Leone + +`include "common_cells/assertions.svh" + +/// This module simply translates the address to an endpoint ID. +/// It uses either an address decoder for the system address map, +/// or a simple offset based translation. +module floo_id_translation #( + /// The route config + parameter floo_pkg::route_cfg_t RouteCfg = floo_pkg::RouteDefaultCfg, + /// The type of the ID + parameter type id_t = logic, + /// The type of the IDX field in the address rule + parameter type sam_idx_t = id_t, + /// The address type + parameter type addr_t = logic, + /// The type of the address rules + parameter type addr_rule_t = logic, + /// The System Address Map + parameter addr_rule_t [RouteCfg.NumSamRules-1:0] Sam, + /// The type of the offset + len to identify which bits in the address can be masked + parameter type mask_sel_t = logic +) ( + input logic clk_i, // Only used for assertions + input logic rst_ni, // Only used for assertions + input logic valid_i, // Only used for assertions + input addr_t addr_i, + output id_t id_o, + output mask_sel_t mask_addr_x_o, + output mask_sel_t mask_addr_y_o +); + + + if (RouteCfg.UseIdTable) begin : gen_addr_decoder + logic dec_error; + sam_idx_t idx_out; + mask_sel_t x_mask_sel, y_mask_sel; + addr_t x_addr_mask, y_addr_mask; + + addr_decode #( + .NoRules ( RouteCfg.NumSamRules ), + .addr_t ( addr_t ), + .rule_t ( addr_rule_t ), + .idx_t ( sam_idx_t ) + ) i_addr_dst_decode ( + .addr_i, + .addr_map_i ( Sam ), + .idx_o ( idx_out ), + .dec_valid_o ( ), + .dec_error_o ( dec_error ), + .en_default_idx_i ( 1'b0 ), + .default_idx_i ( '0 ) + ); + + `ASSERT(DecodeError, !(dec_error && valid_i), clk_i, !rst_ni, + $sformatf("Error decoding address 0x%0x.", addr_i)); + + if (RouteCfg.EnMultiCast) begin: gen_mcast_id_mask + assign mask_addr_x_o = idx_out.mask_x; + assign mask_addr_y_o = idx_out.mask_y; + assign id_o = idx_out.id; + end else begin: gen_no_mcast + // If no multicast, simply forward the decoder id to the output + assign mask_addr_x_o = '0; + assign mask_addr_y_o = '0; + assign id_o = idx_out; + end + end else if (RouteCfg.RouteAlgo == floo_pkg::XYRouting) begin : gen_xy_offset + assign id_o.port_id = '0; // Not supported at the moment + assign id_o.x = addr_i[RouteCfg.XYAddrOffsetX +: $bits(id_o.x)]; + assign id_o.y = addr_i[RouteCfg.XYAddrOffsetY +: $bits(id_o.y)]; + end else if (RouteCfg.RouteAlgo == floo_pkg::IdTable) begin : gen_id_offset + assign id_o = addr_i[RouteCfg.IdAddrOffset +: $bits(id_o)]; + end else begin: gen_unsupported_routing + $fatal(1, "Routing algorithm %0s only supports table-based address translation", + RouteCfg.RouteAlgo); + end + +endmodule diff --git a/hw/floo_meta_buffer.sv b/hw/floo_meta_buffer.sv index cd058574f..64ba8e2ce 100644 --- a/hw/floo_meta_buffer.sv +++ b/hw/floo_meta_buffer.sv @@ -2,7 +2,9 @@ // Solderpad Hardware License, Version 0.51, see LICENSE for details. // SPDX-License-Identifier: SHL-0.51 // -// Author: Tim Fischer +// Tim Fischer +// Lorenzo Leone +// Chen Wu `include "common_cells/registers.svh" `include "common_cells/assertions.svh" @@ -33,11 +35,23 @@ module floo_meta_buffer #( /// AXI out response channel parameter type axi_out_rsp_t = logic, /// Information to be buffered for responses - parameter type buf_t = logic + parameter type buf_t = logic, + // used for AXI mask <-> NoC mask conversion + parameter floo_pkg::route_cfg_t RouteCfg = '0, + parameter type addr_t = logic, + /// The type of the address rules + parameter type sam_rule_t = logic, + /// The System Address Map + parameter sam_rule_t [RouteCfg.NumSamRules-1:0] Sam, + parameter type id_t = logic, + /// SAM Index type to support multicast info + parameter type sam_idx_t = id_t, + parameter type mask_sel_t = logic ) ( input logic clk_i, input logic rst_ni, input logic test_enable_i, + input id_t id_i, input axi_in_req_t axi_req_i, output axi_in_rsp_t axi_rsp_o, output axi_out_req_t axi_req_o, @@ -65,6 +79,8 @@ module floo_meta_buffer #( id_out_t no_atop_aw_req_id, no_atop_ar_req_id; + addr_t axi_addr; + if (MaxUniqueIds == 1) begin : gen_no_atop_fifos // The ID is set to the constant '1 for non-atomic transactions @@ -200,6 +216,49 @@ module floo_meta_buffer #( assign r_buf_o = (is_atop_r_rsp && AtopSupport)? atop_r_buf[axi_rsp_i.r.id] : no_atop_r_buf; assign b_buf_o = (is_atop_b_rsp && AtopSupport)? atop_b_buf[axi_rsp_i.b.id] : no_atop_b_buf; + // NoC addr/mask to AXI addr/mask conversion + localparam int unsigned AddrWidth = $bits(addr_t); + if (RouteCfg.EnMultiCast && RouteCfg.UseIdTable && + (RouteCfg.RouteAlgo == floo_pkg::XYRouting)) + begin : gen_mcast_table_conversion + id_t out, in_mask, in_id; + mask_sel_t x_mask_sel, y_mask_sel; + addr_t x_addr_mask, y_addr_mask; + addr_t in_addr; + id_t base_id; + + assign in_mask = aw_buf_i.hdr.mask; + assign in_id = aw_buf_i.hdr.dst_id; + assign base_id = '{x: x_mask_sel.base_id, y: y_mask_sel.base_id, port_id: '0}; + assign out = ((~in_mask & in_id) | (in_mask & id_i)) & ~base_id; + assign in_addr = axi_req_i.aw.addr; + floo_id_translation #( + .RouteCfg (RouteCfg), + .Sam (Sam), + .sam_idx_t (sam_idx_t), + .id_t (id_t), + .addr_t (addr_t), + .addr_rule_t(sam_rule_t), + .mask_sel_t (mask_sel_t) + ) i_floo_id_translation ( + .clk_i, + .rst_ni, + .valid_i (axi_req_i.aw_valid), + .addr_i (in_addr), + .id_o (), + .mask_addr_x_o (x_mask_sel), + .mask_addr_y_o (y_mask_sel) + ); + always_comb begin + x_addr_mask = (({AddrWidth{1'b1}} >> (AddrWidth - x_mask_sel.len)) << x_mask_sel.offset); + y_addr_mask = (({AddrWidth{1'b1}} >> (AddrWidth - y_mask_sel.len)) << y_mask_sel.offset); + end + assign axi_addr = (in_addr & ~(x_addr_mask | y_addr_mask)) + | ((out.x << x_mask_sel.offset) | (out.y << y_mask_sel.offset)); + end else begin : gen_no_mcast + assign axi_addr = axi_req_i.aw.addr; + end + if (AtopSupport) begin : gen_atop_support logic [MaxAtomicTxns-1:0] ar_atop_reg_full, aw_atop_reg_full; @@ -290,6 +349,7 @@ module floo_meta_buffer #( !no_atop_id_available : !aw_no_atop_buf_full); axi_rsp_o.aw_ready = axi_rsp_i.aw_ready && ((is_atop_aw)? !no_atop_id_available : !aw_no_atop_buf_full); + axi_req_o.aw.addr = axi_addr; end end else begin : gen_no_atop_support @@ -309,6 +369,7 @@ module floo_meta_buffer #( axi_rsp_o.ar_ready = axi_rsp_i.ar_ready && !ar_no_atop_buf_full; axi_req_o.aw_valid = axi_req_i.aw_valid && !aw_no_atop_buf_full; axi_rsp_o.aw_ready = axi_rsp_i.aw_ready && !aw_no_atop_buf_full; + axi_req_o.aw.addr = axi_addr; end end diff --git a/hw/floo_nw_chimney.sv b/hw/floo_nw_chimney.sv index 6da153344..47b1c40d0 100644 --- a/hw/floo_nw_chimney.sv +++ b/hw/floo_nw_chimney.sv @@ -3,10 +3,13 @@ // SPDX-License-Identifier: SHL-0.51 // // Tim Fischer +// Lorenzo Leone +// Chen Wu `include "common_cells/registers.svh" `include "common_cells/assertions.svh" `include "axi/typedef.svh" +`include "axi/assign.svh" `include "floo_noc/typedef.svh" /// A bidirectional network interface for connecting narrow & wide AXI Buses to the multi-link NoC @@ -50,6 +53,11 @@ module floo_nw_chimney #( /// The System Address Map (SAM) rules /// (only used if `RouteCfg.UseIdTable == 1'b1`) parameter sam_rule_t [RouteCfg.NumSamRules-1:0] Sam = '0, + /// SAM Index type to support multicast info + parameter type sam_idx_t = id_t, + /// Struct consisting of offset and len to speficy the position of the mask bits + /// (only used if `EnMultiCast && RouteCfg.UseIdTable == 1'b1 && RouteCfg.RouteAlgo == XYRouting`) + parameter type mask_sel_t = logic, /// Narrow AXI manager request channel type parameter type axi_narrow_in_req_t = logic, /// Narrow AXI manager response channel type @@ -74,7 +82,10 @@ module floo_nw_chimney #( parameter type floo_wide_t = logic, /// SRAM configuration type `tc_sram_impl` in RoB /// Only used if technology-dependent SRAM is used - parameter type sram_cfg_t = logic + parameter type sram_cfg_t = logic, + /// Struct for user field in AXI + /// currently only used if EnMultiCast + parameter type user_struct_t = logic ) ( input logic clk_i, input logic rst_ni, @@ -129,12 +140,18 @@ module floo_nw_chimney #( axi_narrow_out_id_t, axi_narrow_user_t) `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow, axi_wide, AxiCfgN, AxiCfgW, hdr_t) + // Type of the mask encoded in the user field. + // It's always equal to the address field. + // For future extension, add an extra opcode in the user_struct_t + typedef axi_addr_t user_mask_t ; + // Duplicate AXI port signals to degenerate ports // in case they are not used axi_narrow_req_t axi_narrow_req_in; axi_narrow_rsp_t axi_narrow_rsp_out; axi_wide_req_t axi_wide_req_in; axi_wide_rsp_t axi_wide_rsp_out; + user_mask_t axi_narrow_req_in_mask, axi_wide_req_in_mask; // AX queue axi_narrow_aw_chan_t axi_narrow_aw_queue; @@ -145,7 +162,9 @@ module floo_nw_chimney #( logic axi_narrow_ar_queue_valid_out, axi_narrow_ar_queue_ready_in; logic axi_wide_aw_queue_valid_out, axi_wide_aw_queue_ready_in; logic axi_wide_ar_queue_valid_out, axi_wide_ar_queue_ready_in; + user_mask_t axi_narrow_mask_queue, axi_wide_mask_queue; + // AXI req/rsp arbiter floo_req_chan_t [WideAr:NarrowAw] floo_req_arb_in; floo_rsp_chan_t [WideB:NarrowB] floo_rsp_arb_in; floo_wide_chan_t [WideR:WideAw] floo_wide_arb_in; @@ -194,12 +213,12 @@ module floo_nw_chimney #( floo_wide_generic_flit_t floo_wide_unpack_generic; // Meta Buffers - axi_narrow_in_req_t axi_narrow_meta_buf_req_in; - axi_narrow_in_rsp_t axi_narrow_meta_buf_rsp_out; + axi_narrow_req_t axi_narrow_meta_buf_req_in; + axi_narrow_rsp_t axi_narrow_meta_buf_rsp_out; axi_narrow_out_req_t axi_narrow_meta_buf_req_out; axi_narrow_out_rsp_t axi_narrow_meta_buf_rsp_in; - axi_wide_in_req_t axi_wide_meta_buf_req_in; - axi_wide_in_rsp_t axi_wide_meta_buf_rsp_out; + axi_wide_req_t axi_wide_meta_buf_req_in; + axi_wide_rsp_t axi_wide_meta_buf_rsp_out; axi_wide_out_req_t axi_wide_meta_buf_req_out; axi_wide_out_rsp_t axi_wide_meta_buf_rsp_in; @@ -217,8 +236,10 @@ module floo_nw_chimney #( // Routing dst_t [NumNWAxiChannels-1:0] dst_id; dst_t narrow_aw_id_q, wide_aw_id_q; - route_t [NumNWAxiChannels-1:0] route_out; + id_t narrow_aw_mask_q, wide_aw_mask_q; + id_t [NumNWAxiChannels-1:0] mcast_mask; id_t [NumNWAxiChannels-1:0] id_out; + id_t [NumNWAxiChannels-1:0] mask_id; narrow_meta_buf_t narrow_aw_buf_hdr_in, narrow_aw_buf_hdr_out; @@ -231,9 +252,20 @@ module floo_nw_chimney #( /////////////////////// if (ChimneyCfgN.EnMgrPort) begin : gen_narrow_sbr_port - - assign axi_narrow_req_in = axi_narrow_in_req_i; - assign axi_narrow_in_rsp_o = axi_narrow_rsp_out; + // We cast the incoming AXI types to the ones that are actually transported + // If multicast is enabled, the bits holding the mask are dropped. + `AXI_ASSIGN_REQ_STRUCT(axi_narrow_req_in, axi_narrow_in_req_i) + `AXI_ASSIGN_RESP_STRUCT(axi_narrow_in_rsp_o, axi_narrow_rsp_out) + + // Extract the multicast mask bits from the AXI user bits + if (RouteCfg.EnMultiCast) begin : gen_mask + user_struct_t user; + assign user = axi_narrow_in_req_i.aw.user; + // TODO(lleone): Check subfield name is `mcast_mask` + assign axi_narrow_req_in_mask = user.mcast_mask; + end else begin : gen_no_mask + assign axi_narrow_req_in_mask = '0; + end if (ChimneyCfgN.CutAx) begin : gen_ax_cuts spill_register #( @@ -241,8 +273,8 @@ module floo_nw_chimney #( ) i_narrow_aw_queue ( .clk_i, .rst_ni, - .data_i ( axi_narrow_in_req_i.aw ), - .valid_i ( axi_narrow_in_req_i.aw_valid ), + .data_i ( axi_narrow_req_in.aw ), + .valid_i ( axi_narrow_req_in.aw_valid ), .ready_o ( axi_narrow_rsp_out.aw_ready ), .data_o ( axi_narrow_aw_queue ), .valid_o ( axi_narrow_aw_queue_valid_out ), @@ -254,21 +286,40 @@ module floo_nw_chimney #( ) i_narrow_ar_queue ( .clk_i, .rst_ni, - .data_i ( axi_narrow_in_req_i.ar ), - .valid_i ( axi_narrow_in_req_i.ar_valid ), + .data_i ( axi_narrow_req_in.ar ), + .valid_i ( axi_narrow_req_in.ar_valid ), .ready_o ( axi_narrow_rsp_out.ar_ready ), .data_o ( axi_narrow_ar_queue ), .valid_o ( axi_narrow_ar_queue_valid_out ), .ready_i ( axi_narrow_ar_queue_ready_in ) ); + if (RouteCfg.EnMultiCast) begin : gen_mask_cuts + spill_register #( + .T (user_mask_t) + ) i_narrow_usermask_queue ( + .clk_i, + .rst_ni, + .data_i ( axi_narrow_req_in_mask ), + .valid_i ( axi_narrow_req_in.aw_valid ), + .ready_o ( ), + .data_o ( axi_narrow_mask_queue ), + .valid_o ( ), + .ready_i ( axi_narrow_aw_queue_ready_in ) + ); + end else begin : gen_no_mask_cuts + assign axi_narrow_mask_queue = '0; + end + + end else begin : gen_ax_no_cuts - assign axi_narrow_aw_queue = axi_narrow_in_req_i.aw; - assign axi_narrow_aw_queue_valid_out = axi_narrow_in_req_i.aw_valid; + assign axi_narrow_aw_queue = axi_narrow_req_in.aw; + assign axi_narrow_aw_queue_valid_out = axi_narrow_req_in.aw_valid; assign axi_narrow_rsp_out.aw_ready = axi_narrow_aw_queue_ready_in; - assign axi_narrow_ar_queue = axi_narrow_in_req_i.ar; - assign axi_narrow_ar_queue_valid_out = axi_narrow_in_req_i.ar_valid; + assign axi_narrow_ar_queue = axi_narrow_req_in.ar; + assign axi_narrow_ar_queue_valid_out = axi_narrow_req_in.ar_valid; assign axi_narrow_rsp_out.ar_ready = axi_narrow_ar_queue_ready_in; + assign axi_narrow_mask_queue = axi_narrow_req_in_mask; end end else begin : gen_narrow_err_slv_port @@ -289,12 +340,20 @@ module floo_nw_chimney #( assign axi_narrow_ar_queue = '0; assign axi_narrow_aw_queue_valid_out = 1'b0; assign axi_narrow_ar_queue_valid_out = 1'b0; + assign axi_narrow_mask_queue = '0; end if (ChimneyCfgW.EnMgrPort) begin : gen_wide_sbr_port - - assign axi_wide_req_in = axi_wide_in_req_i; - assign axi_wide_in_rsp_o = axi_wide_rsp_out; + // We cast the incoming AXI types to the ones that are actually transported + // If multicast is enabled, the bits holding the mask are dropped. + `AXI_ASSIGN_REQ_STRUCT(axi_wide_req_in, axi_wide_in_req_i) + `AXI_ASSIGN_RESP_STRUCT(axi_wide_in_rsp_o, axi_wide_rsp_out) + + if (RouteCfg.EnMultiCast) begin : gen_mask + assign axi_wide_req_in_mask = axi_wide_in_req_i.aw.user; + end else begin : gen_no_mask + assign axi_wide_req_in_mask = '0; + end if (ChimneyCfgW.CutAx) begin : gen_ax_cuts spill_register #( @@ -302,8 +361,8 @@ module floo_nw_chimney #( ) i_wide_aw_queue ( .clk_i, .rst_ni, - .data_i ( axi_wide_in_req_i.aw ), - .valid_i ( axi_wide_in_req_i.aw_valid ), + .data_i ( axi_wide_req_in.aw ), + .valid_i ( axi_wide_req_in.aw_valid ), .ready_o ( axi_wide_rsp_out.aw_ready ), .data_o ( axi_wide_aw_queue ), .valid_o ( axi_wide_aw_queue_valid_out ), @@ -315,20 +374,39 @@ module floo_nw_chimney #( ) i_wide_ar_queue ( .clk_i, .rst_ni, - .data_i ( axi_wide_in_req_i.ar ), - .valid_i ( axi_wide_in_req_i.ar_valid ), + .data_i ( axi_wide_req_in.ar ), + .valid_i ( axi_wide_req_in.ar_valid ), .ready_o ( axi_wide_rsp_out.ar_ready ), .data_o ( axi_wide_ar_queue ), .valid_o ( axi_wide_ar_queue_valid_out ), .ready_i ( axi_wide_ar_queue_ready_in ) ); + + if (RouteCfg.EnMultiCast) begin : gen_mask_cuts + spill_register #( + .T (user_mask_t) + ) i_wide_usermask_queue ( + .clk_i, + .rst_ni, + .data_i ( axi_wide_req_in_mask ), + .valid_i ( axi_wide_req_in.aw_valid ), + .ready_o ( ), + .data_o ( axi_wide_mask_queue ), + .valid_o ( ), + .ready_i ( axi_wide_aw_queue_ready_in ) + ); + end else begin : gen_no_mask_cuts + assign axi_wide_mask_queue = '0; + end + end else begin : gen_ax_no_cuts - assign axi_wide_aw_queue = axi_wide_in_req_i.aw; - assign axi_wide_aw_queue_valid_out = axi_wide_in_req_i.aw_valid; + assign axi_wide_aw_queue = axi_wide_req_in.aw; + assign axi_wide_aw_queue_valid_out = axi_wide_req_in.aw_valid; assign axi_wide_rsp_out.aw_ready = axi_wide_aw_queue_ready_in; - assign axi_wide_ar_queue = axi_wide_in_req_i.ar; - assign axi_wide_ar_queue_valid_out = axi_wide_in_req_i.ar_valid; + assign axi_wide_ar_queue = axi_wide_req_in.ar; + assign axi_wide_ar_queue_valid_out = axi_wide_req_in.ar_valid; assign axi_wide_rsp_out.ar_ready = axi_wide_ar_queue_ready_in; + assign axi_wide_mask_queue = axi_wide_req_in_mask; end end else begin : gen_wide_err_slv_port @@ -349,6 +427,7 @@ module floo_nw_chimney #( assign axi_wide_ar_queue = '0; assign axi_wide_aw_queue_valid_out = 1'b0; assign axi_wide_ar_queue_valid_out = 1'b0; + assign axi_wide_mask_queue = '0; end if (ChimneyCfgN.CutRsp && ChimneyCfgW.CutRsp) begin : gen_rsp_cuts @@ -405,8 +484,11 @@ module floo_nw_chimney #( logic narrow_aw_out_queue_valid, narrow_aw_out_queue_ready; logic wide_aw_out_queue_valid, wide_aw_out_queue_ready; - axi_narrow_out_aw_chan_t axi_narrow_aw_queue_out; - axi_wide_out_aw_chan_t axi_wide_aw_queue_out; + axi_narrow_out_aw_chan_t axi_narrow_aw_queue_out, axi_narrow_aw_queue_in; + axi_wide_out_aw_chan_t axi_wide_aw_queue_out, axi_wide_aw_queue_in; + + `AXI_ASSIGN_AW_STRUCT(axi_narrow_aw_queue_in, axi_narrow_meta_buf_req_out.aw) + `AXI_ASSIGN_AW_STRUCT(axi_wide_aw_queue_in, axi_wide_meta_buf_req_out.aw) // Since AW and W are transferred over the same link, it can happen that // a downstream module does not accept the AW until the W is valid. @@ -418,7 +500,7 @@ module floo_nw_chimney #( .rst_ni ( rst_ni ), .valid_i ( axi_narrow_meta_buf_req_out.aw_valid ), .ready_o ( narrow_aw_out_queue_ready ), - .data_i ( axi_narrow_meta_buf_req_out.aw ), + .data_i ( axi_narrow_aw_queue_in ), .valid_o ( narrow_aw_out_queue_valid ), .ready_i ( axi_narrow_out_rsp_i.aw_ready ), .data_o ( axi_narrow_aw_queue_out ) @@ -431,7 +513,7 @@ module floo_nw_chimney #( .rst_ni ( rst_ni ), .valid_i ( axi_wide_meta_buf_req_out.aw_valid ), .ready_o ( wide_aw_out_queue_ready ), - .data_i ( axi_wide_meta_buf_req_out.aw ), + .data_i ( axi_wide_aw_queue_in ), .valid_o ( wide_aw_out_queue_valid ), .ready_i ( axi_wide_out_rsp_i.aw_ready ), .data_o ( axi_wide_aw_queue_out ) @@ -440,12 +522,12 @@ module floo_nw_chimney #( always_comb begin axi_narrow_out_req_o = axi_narrow_meta_buf_req_out; axi_narrow_out_req_o.aw_valid = narrow_aw_out_queue_valid; - axi_narrow_out_req_o.aw = axi_narrow_aw_queue_out; + `AXI_SET_AW_STRUCT(axi_narrow_out_req_o.aw, axi_narrow_aw_queue_out); axi_narrow_meta_buf_rsp_in = axi_narrow_out_rsp_i; axi_narrow_meta_buf_rsp_in.aw_ready = narrow_aw_out_queue_ready; axi_wide_out_req_o = axi_wide_meta_buf_req_out; axi_wide_out_req_o.aw_valid = wide_aw_out_queue_valid; - axi_wide_out_req_o.aw = axi_wide_aw_queue_out; + `AXI_SET_AW_STRUCT(axi_wide_out_req_o.aw, axi_wide_aw_queue_out); axi_wide_meta_buf_rsp_in = axi_wide_out_rsp_i; axi_wide_meta_buf_rsp_in.aw_ready = wide_aw_out_queue_ready; end @@ -521,7 +603,7 @@ module floo_nw_chimney #( .sram_cfg_i, .ax_valid_i ( narrow_aw_rob_valid_in ), .ax_ready_o ( narrow_aw_rob_ready_out ), - .ax_len_i ( axi_narrow_aw_queue.len ), + .ax_len_i ( '0 ), // B responses are single-beat .ax_id_i ( axi_narrow_aw_queue.id ), .ax_dest_i ( id_out[NarrowAw] ), .ax_valid_o ( narrow_aw_rob_valid_out ), @@ -564,7 +646,7 @@ module floo_nw_chimney #( .sram_cfg_i, .ax_valid_i ( axi_wide_aw_queue_valid_out ), .ax_ready_o ( axi_wide_aw_queue_ready_in ), - .ax_len_i ( axi_wide_aw_queue.len ), + .ax_len_i ( '0 ), // B responses are single-beat .ax_id_i ( axi_wide_aw_queue.id ), .ax_dest_i ( id_out[WideAw] ), .ax_valid_o ( wide_aw_rob_valid_out ), @@ -689,7 +771,9 @@ module floo_nw_chimney #( ///////////////// axi_addr_t [NumNWAxiChannels-1:0] axi_req_addr; + user_mask_t [NumNWAxiChannels-1:0] axi_req_user; id_t [NumNWAxiChannels-1:0] axi_rsp_src_id; + mask_sel_t [NumNWAxiChannels-1:0] x_mask_sel, y_mask_sel; assign axi_req_addr[NarrowAw] = axi_narrow_aw_queue.addr; assign axi_req_addr[NarrowAr] = axi_narrow_ar_queue.addr; @@ -701,77 +785,111 @@ module floo_nw_chimney #( assign axi_rsp_src_id[WideB] = wide_aw_buf_hdr_out.hdr.src_id; assign axi_rsp_src_id[WideR] = wide_ar_buf_hdr_out.hdr.src_id; - for (genvar ch = 0; ch < NumNWAxiChannels; ch++) begin : gen_route_comp + assign axi_req_user[NarrowAw] = axi_narrow_mask_queue; + assign axi_req_user[NarrowAr] = '0; + assign axi_req_user[WideAw] = axi_wide_mask_queue; + assign axi_req_user[WideAr] = '0; + + for (genvar ch = 0; ch < NumNWAxiChannels; ch++) begin : gen_route localparam nw_ch_e Ch = nw_ch_e'(ch); if (Ch == NarrowAw || Ch == NarrowAr || - Ch == WideAw || Ch == WideAr) begin : gen_req_route_comp + Ch == WideAw || Ch == WideAr) begin : gen_req_route // Translate the address from AXI requests to a destination ID - // (or route if `SourceRouting` is used) - floo_route_comp #( - .RouteCfg ( RouteCfg ), - .id_t ( id_t ), - .addr_t ( axi_addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) - ) i_floo_req_route_comp ( + floo_id_translation #( + .RouteCfg (RouteCfg), + .Sam (Sam), + .sam_idx_t (sam_idx_t), + .id_t (id_t), + .addr_t (axi_addr_t), + .addr_rule_t(sam_rule_t), + .mask_sel_t (mask_sel_t) + ) i_floo_id_translation ( .clk_i, .rst_ni, - .route_table_i, - .addr_map_i ( Sam ), - .id_i ( id_t'('0) ), - .addr_i ( axi_req_addr[ch] ), - .route_o ( route_out[ch] ), - .id_o ( id_out[ch] ) - ); - end else if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting && - (Ch == NarrowB || Ch == NarrowR || - Ch == WideB || Ch == WideR)) begin : gen_rsp_route_comp - // Generally, the source ID from the request is used to route back - // the responses. However, in the case of `SourceRouting`, the source ID - // first needs to be translated into a route. - floo_route_comp #( - .RouteCfg ( RouteCfg ), - .UseIdTable ( 1'b0 ), // Overwrite `RouteCfg` - .id_t ( id_t ), - .addr_t ( axi_addr_t ), - .addr_rule_t ( sam_rule_t ), - .route_t ( route_t ) - ) i_floo_rsp_route_comp ( - .clk_i, - .rst_ni, - .route_table_i, - .addr_i ( '0 ), - .addr_map_i ( '0 ), - .id_i ( axi_rsp_src_id[ch] ), - .route_o ( route_out[ch] ), - .id_o ( id_out[ch] ) + .valid_i (axi_narrow_aw_queue_valid_out), + .addr_i (axi_req_addr[ch]), + .id_o (id_out[ch]), + .mask_addr_x_o (x_mask_sel[ch]), + .mask_addr_y_o (y_mask_sel[ch]) ); + end else if ((Ch == NarrowB || Ch == NarrowR || + Ch == WideB || Ch == WideR)) begin : gen_rsp_route + // For responses, the `src_id` from the request is used to route back + // the responses. + assign id_out[ch] = axi_rsp_src_id[ch]; + end else if (Ch == NarrowW) begin : gen_w_narrow_route + // The destination ID of Narrow W's is the previous Narrow AW's ID + assign id_out[ch] = narrow_aw_id_q; + end else if (Ch == WideW) begin : gen_w_wode_route + // The destination ID of Wide W's is the previous Wide AW's ID + assign id_out[ch] = wide_aw_id_q; end - end - if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin : gen_route_field - assign route_out[NarrowW] = narrow_aw_id_q; - assign route_out[WideW] = wide_aw_id_q; - assign dst_id = route_out; - end else begin : gen_dst_field - assign dst_id[NarrowAw] = id_out[NarrowAw]; - assign dst_id[NarrowAr] = id_out[NarrowAr]; - assign dst_id[WideAw] = id_out[WideAw]; - assign dst_id[WideAr] = id_out[WideAr]; - assign dst_id[NarrowB] = narrow_aw_buf_hdr_out.hdr.src_id; - assign dst_id[NarrowR] = narrow_ar_buf_hdr_out.hdr.src_id; - assign dst_id[WideB] = wide_aw_buf_hdr_out.hdr.src_id; - assign dst_id[WideR] = wide_ar_buf_hdr_out.hdr.src_id; - assign dst_id[NarrowW] = narrow_aw_id_q; - assign dst_id[WideW] = wide_aw_id_q; + // The actual `dst_id` depends on the routing algorithm + if (RouteCfg.RouteAlgo == floo_pkg::SourceRouting) begin: gen_dst_srcroute + // Look up the `route` in the routing table + assign dst_id[ch] = route_table_i[id_out[ch]]; + end else begin : gen_no_dst_srcroute + // Otherwise, assign the destination ID directly + assign dst_id[ch] = id_out[ch]; + end end - `FFL(narrow_aw_id_q, dst_id[NarrowAw], axi_narrow_aw_queue_valid_out && + `FFL(narrow_aw_id_q, id_out[NarrowAw], axi_narrow_aw_queue_valid_out && axi_narrow_aw_queue_ready_in, '0) - `FFL(wide_aw_id_q, dst_id[WideAw], axi_wide_aw_queue_valid_out && + `FFL(wide_aw_id_q, id_out[WideAw], axi_wide_aw_queue_valid_out && axi_wide_aw_queue_ready_in, '0) + if (RouteCfg.EnMultiCast) begin : gen_mcast + localparam int unsigned AddrWidth = $bits(axi_addr_t); + axi_addr_t [NumNWAxiChannels-1:0] x_addr_mask; + axi_addr_t [NumNWAxiChannels-1:0] y_addr_mask; + + for (genvar ch = 0; ch < NumNWAxiChannels; ch++) begin : gen_mcast_id_mask + localparam nw_ch_e Ch = nw_ch_e'(ch); + if (Ch == NarrowAw || Ch == WideAw ) begin : gen_req_mcast_id_mask + // Evaluate the ID Mask according to the info read from the SAM through the flooo_id_translation module + if (RouteCfg.UseIdTable && + RouteCfg.RouteAlgo == floo_pkg::XYRouting) begin: gen_mcast_idtable + assign x_addr_mask[ch] = (({AddrWidth{1'b1}} >> (AddrWidth - x_mask_sel[ch].len)) + << x_mask_sel[ch].offset); + assign y_addr_mask[ch] = (({AddrWidth{1'b1}} >> (AddrWidth - y_mask_sel[ch].len)) + << y_mask_sel[ch].offset); + assign mask_id[ch].x = (axi_req_user[ch] & x_addr_mask[ch]) >> x_mask_sel[ch].offset; + assign mask_id[ch].y = (axi_req_user[ch] & y_addr_mask[ch]) >> y_mask_sel[ch].offset; + assign mask_id[ch].port_id = '0; + end else if (RouteCfg.RouteAlgo == floo_pkg::XYRouting) begin: gen_mcast_noidtable + assign mask_id[ch].x = axi_req_user[ch][RouteCfg.XYAddrOffsetX +: $bits(id_out[ch].x)]; + assign mask_id[ch].y = axi_req_user[ch][RouteCfg.XYAddrOffsetY +: $bits(id_out[ch].y)]; + assign mask_id[ch].port_id = '0; + end else begin: gen_mcast_nosupported + assign mask_id[ch] = '0; // We don't support multicast for other routing algorithms + end + end + end + + assign mcast_mask[NarrowAw] = mask_id[NarrowAw]; + assign mcast_mask[NarrowAr] = '0; + assign mcast_mask[WideAw] = mask_id[WideAw]; + assign mcast_mask[WideAr] = '0; + assign mcast_mask[NarrowW] = narrow_aw_mask_q; + assign mcast_mask[WideW] = wide_aw_mask_q; + + assign mcast_mask[NarrowR] = narrow_ar_buf_hdr_out.hdr.mask; + assign mcast_mask[NarrowB] = narrow_aw_buf_hdr_out.hdr.mask; + assign mcast_mask[WideR] = wide_ar_buf_hdr_out.hdr.mask; + assign mcast_mask[WideB] = wide_aw_buf_hdr_out.hdr.mask; + + `FFL(narrow_aw_mask_q, mcast_mask[NarrowAw], axi_narrow_aw_queue_valid_out && + axi_narrow_aw_queue_ready_in, '0) + `FFL(wide_aw_mask_q, mcast_mask[WideAw], axi_wide_aw_queue_valid_out && + axi_wide_aw_queue_ready_in, '0) + + end else begin: gen_no_mcast_mask + assign mcast_mask = '0; + end + /////////////////// // FLIT PACKING // /////////////////// @@ -781,11 +899,13 @@ module floo_nw_chimney #( floo_narrow_aw.hdr.rob_req = narrow_aw_rob_req_out; floo_narrow_aw.hdr.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out); floo_narrow_aw.hdr.dst_id = dst_id[NarrowAw]; + floo_narrow_aw.hdr.mask = mcast_mask[NarrowAw]; floo_narrow_aw.hdr.src_id = id_i; floo_narrow_aw.hdr.last = 1'b0; // AW and W need to be sent together floo_narrow_aw.hdr.axi_ch = NarrowAw; floo_narrow_aw.hdr.atop = axi_narrow_aw_queue.atop != axi_pkg::ATOP_NONE; floo_narrow_aw.payload = axi_narrow_aw_queue; + floo_narrow_aw.hdr.commtype = (mcast_mask[NarrowAw] != '0)? Multicast : Unicast; end always_comb begin @@ -793,10 +913,12 @@ module floo_nw_chimney #( floo_narrow_w.hdr.rob_req = narrow_aw_rob_req_out; floo_narrow_w.hdr.rob_idx = rob_idx_t'(narrow_aw_rob_idx_out); floo_narrow_w.hdr.dst_id = dst_id[NarrowW]; + floo_narrow_w.hdr.mask = mcast_mask[NarrowW]; floo_narrow_w.hdr.src_id = id_i; floo_narrow_w.hdr.last = axi_narrow_req_in.w.last; floo_narrow_w.hdr.axi_ch = NarrowW; floo_narrow_w.payload = axi_narrow_req_in.w; + floo_narrow_w.hdr.commtype = (mcast_mask[NarrowW] != '0)? Multicast : Unicast; end always_comb begin @@ -804,23 +926,28 @@ module floo_nw_chimney #( floo_narrow_ar.hdr.rob_req = narrow_ar_rob_req_out; floo_narrow_ar.hdr.rob_idx = rob_idx_t'(narrow_ar_rob_idx_out); floo_narrow_ar.hdr.dst_id = dst_id[NarrowAr]; + floo_narrow_ar.hdr.mask = mcast_mask[NarrowAr]; floo_narrow_ar.hdr.src_id = id_i; floo_narrow_ar.hdr.last = 1'b1; floo_narrow_ar.hdr.axi_ch = NarrowAr; floo_narrow_ar.payload = axi_narrow_ar_queue; + floo_narrow_ar.hdr.commtype = '0; end always_comb begin - floo_narrow_b = '0; - floo_narrow_b.hdr.rob_req = narrow_aw_buf_hdr_out.hdr.rob_req; - floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_buf_hdr_out.hdr.rob_idx); - floo_narrow_b.hdr.dst_id = dst_id[NarrowB]; - floo_narrow_b.hdr.src_id = id_i; - floo_narrow_b.hdr.last = 1'b1; - floo_narrow_b.hdr.axi_ch = NarrowB; - floo_narrow_b.hdr.atop = narrow_aw_buf_hdr_out.hdr.atop; - floo_narrow_b.payload = axi_narrow_meta_buf_rsp_out.b; - floo_narrow_b.payload.id = narrow_aw_buf_hdr_out.id; + floo_narrow_b = '0; + floo_narrow_b.hdr.rob_req = narrow_aw_buf_hdr_out.hdr.rob_req; + floo_narrow_b.hdr.rob_idx = rob_idx_t'(narrow_aw_buf_hdr_out.hdr.rob_idx); + floo_narrow_b.hdr.dst_id = dst_id[NarrowB]; + floo_narrow_b.hdr.mask = mcast_mask[NarrowB]; + floo_narrow_b.hdr.src_id = id_i; + floo_narrow_b.hdr.last = 1'b1; + floo_narrow_b.hdr.axi_ch = NarrowB; + floo_narrow_b.hdr.atop = narrow_aw_buf_hdr_out.hdr.atop; + floo_narrow_b.payload = axi_narrow_meta_buf_rsp_out.b; + floo_narrow_b.payload.id = narrow_aw_buf_hdr_out.id; + floo_narrow_b.hdr.commtype = (narrow_aw_buf_hdr_out.hdr.commtype == Multicast)? + ParallelReduction : Unicast; end always_comb begin @@ -828,12 +955,14 @@ module floo_nw_chimney #( floo_narrow_r.hdr.rob_req = narrow_ar_buf_hdr_out.hdr.rob_req; floo_narrow_r.hdr.rob_idx = rob_idx_t'(narrow_ar_buf_hdr_out.hdr.rob_idx); floo_narrow_r.hdr.dst_id = dst_id[NarrowR]; + floo_narrow_r.hdr.mask = mcast_mask[NarrowR]; floo_narrow_r.hdr.src_id = id_i; floo_narrow_r.hdr.axi_ch = NarrowR; floo_narrow_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts floo_narrow_r.hdr.atop = narrow_ar_buf_hdr_out.hdr.atop; floo_narrow_r.payload = axi_narrow_meta_buf_rsp_out.r; floo_narrow_r.payload.id = narrow_ar_buf_hdr_out.id; + floo_narrow_r.hdr.commtype = '0; end always_comb begin @@ -841,10 +970,12 @@ module floo_nw_chimney #( floo_wide_aw.hdr.rob_req = wide_aw_rob_req_out; floo_wide_aw.hdr.rob_idx = rob_idx_t'(wide_aw_rob_idx_out); floo_wide_aw.hdr.dst_id = dst_id[WideAw]; + floo_wide_aw.hdr.mask = mcast_mask[WideAw]; floo_wide_aw.hdr.src_id = id_i; floo_wide_aw.hdr.last = 1'b0; // AW and W need to be sent together floo_wide_aw.hdr.axi_ch = WideAw; floo_wide_aw.payload = axi_wide_aw_queue; + floo_wide_aw.hdr.commtype = (mcast_mask[WideAw] != '0)? Multicast : Unicast; end always_comb begin @@ -852,10 +983,12 @@ module floo_nw_chimney #( floo_wide_w.hdr.rob_req = wide_aw_rob_req_out; floo_wide_w.hdr.rob_idx = rob_idx_t'(wide_aw_rob_idx_out); floo_wide_w.hdr.dst_id = dst_id[WideW]; + floo_wide_w.hdr.mask = mcast_mask[WideW]; floo_wide_w.hdr.src_id = id_i; floo_wide_w.hdr.last = axi_wide_req_in.w.last; floo_wide_w.hdr.axi_ch = WideW; floo_wide_w.payload = axi_wide_req_in.w; + floo_wide_w.hdr.commtype = (mcast_mask[WideW] != '0)? Multicast : Unicast; end always_comb begin @@ -863,10 +996,12 @@ module floo_nw_chimney #( floo_wide_ar.hdr.rob_req = wide_ar_rob_req_out; floo_wide_ar.hdr.rob_idx = rob_idx_t'(wide_ar_rob_idx_out); floo_wide_ar.hdr.dst_id = dst_id[WideAr]; + floo_wide_ar.hdr.mask = mcast_mask[WideAr]; floo_wide_ar.hdr.src_id = id_i; floo_wide_ar.hdr.last = 1'b1; floo_wide_ar.hdr.axi_ch = WideAr; floo_wide_ar.payload = axi_wide_ar_queue; + floo_wide_ar.hdr.commtype = '0; end always_comb begin @@ -874,11 +1009,14 @@ module floo_nw_chimney #( floo_wide_b.hdr.rob_req = wide_aw_buf_hdr_out.hdr.rob_req; floo_wide_b.hdr.rob_idx = rob_idx_t'(wide_aw_buf_hdr_out.hdr.rob_idx); floo_wide_b.hdr.dst_id = dst_id[WideB]; + floo_wide_b.hdr.mask = mcast_mask[WideB]; floo_wide_b.hdr.src_id = id_i; floo_wide_b.hdr.last = 1'b1; floo_wide_b.hdr.axi_ch = WideB; floo_wide_b.payload = axi_wide_meta_buf_rsp_out.b; floo_wide_b.payload.id = wide_aw_buf_hdr_out.id; + floo_wide_b.hdr.commtype = (wide_aw_buf_hdr_out.hdr.commtype == Multicast)? + ParallelReduction : Unicast; end always_comb begin @@ -886,11 +1024,13 @@ module floo_nw_chimney #( floo_wide_r.hdr.rob_req = wide_ar_buf_hdr_out.hdr.rob_req; floo_wide_r.hdr.rob_idx = rob_idx_t'(wide_ar_buf_hdr_out.hdr.rob_idx); floo_wide_r.hdr.dst_id = dst_id[WideR]; + floo_wide_r.hdr.mask = mcast_mask[WideR]; floo_wide_r.hdr.src_id = id_i; floo_wide_r.hdr.axi_ch = WideR; floo_wide_r.hdr.last = 1'b1; // There is no reason to do wormhole routing for R bursts floo_wide_r.payload = axi_wide_meta_buf_rsp_out.r; floo_wide_r.payload.id = wide_ar_buf_hdr_out.id; + floo_wide_r.hdr.commtype = '0; end always_comb begin @@ -1146,29 +1286,37 @@ module floo_nw_chimney #( if (ChimneyCfgN.EnSbrPort) begin : gen_narrow_mgr_port floo_meta_buffer #( - .InIdWidth ( AxiCfgN.InIdWidth ), - .OutIdWidth ( AxiCfgN.OutIdWidth ), - .MaxTxns ( ChimneyCfgN.MaxTxns ), - .MaxUniqueIds ( ChimneyCfgN.MaxUniqueIds ), - .AtopSupport ( AtopSupport ), - .MaxAtomicTxns ( MaxAtomicTxns ), - .buf_t ( narrow_meta_buf_t ), - .axi_in_req_t ( axi_narrow_in_req_t ), - .axi_in_rsp_t ( axi_narrow_in_rsp_t ), - .axi_out_req_t ( axi_narrow_out_req_t ), - .axi_out_rsp_t ( axi_narrow_out_rsp_t ) + .InIdWidth ( AxiCfgN.InIdWidth ), + .OutIdWidth ( AxiCfgN.OutIdWidth ), + .MaxTxns ( ChimneyCfgN.MaxTxns ), + .MaxUniqueIds ( ChimneyCfgN.MaxUniqueIds ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .Sam ( Sam ), + .buf_t ( narrow_meta_buf_t ), + .axi_in_req_t ( axi_narrow_req_t ), + .axi_in_rsp_t ( axi_narrow_rsp_t ), + .axi_out_req_t ( axi_narrow_out_req_t ), + .axi_out_rsp_t ( axi_narrow_out_rsp_t ), + .RouteCfg ( RouteCfg ), + .addr_t ( axi_addr_t ), + .sam_rule_t ( sam_rule_t ), + .id_t ( id_t ), + .sam_idx_t ( sam_idx_t ), + .mask_sel_t ( mask_sel_t ) ) i_narrow_meta_buffer ( .clk_i, .rst_ni, .test_enable_i, - .axi_req_i ( axi_narrow_meta_buf_req_in ), - .axi_rsp_o ( axi_narrow_meta_buf_rsp_out ), - .axi_req_o ( axi_narrow_meta_buf_req_out ), - .axi_rsp_i ( axi_narrow_meta_buf_rsp_in ), - .aw_buf_i ( narrow_aw_buf_hdr_in ), - .ar_buf_i ( narrow_ar_buf_hdr_in ), - .r_buf_o ( narrow_ar_buf_hdr_out ), - .b_buf_o ( narrow_aw_buf_hdr_out ) + .id_i ( id_i ), + .axi_req_i ( axi_narrow_meta_buf_req_in ), + .axi_rsp_o ( axi_narrow_meta_buf_rsp_out ), + .axi_req_o ( axi_narrow_meta_buf_req_out ), + .axi_rsp_i ( axi_narrow_meta_buf_rsp_in ), + .aw_buf_i ( narrow_aw_buf_hdr_in ), + .ar_buf_i ( narrow_ar_buf_hdr_in ), + .r_buf_o ( narrow_ar_buf_hdr_out ), + .b_buf_o ( narrow_aw_buf_hdr_out ) ); end else begin : gen_no_narrow_mgr_port axi_err_slv #( @@ -1196,15 +1344,23 @@ module floo_nw_chimney #( .MaxUniqueIds ( ChimneyCfgW.MaxUniqueIds ), .AtopSupport ( 1'b0 ), .MaxAtomicTxns ( '0 ), + .Sam ( Sam ), .buf_t ( wide_meta_buf_t ), - .axi_in_req_t ( axi_wide_in_req_t ), - .axi_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_in_req_t ( axi_wide_req_t ), + .axi_in_rsp_t ( axi_wide_rsp_t ), .axi_out_req_t ( axi_wide_out_req_t ), - .axi_out_rsp_t ( axi_wide_out_rsp_t ) + .axi_out_rsp_t ( axi_wide_out_rsp_t ), + .RouteCfg ( RouteCfg ), + .addr_t ( axi_addr_t ), + .sam_rule_t ( sam_rule_t ), + .id_t ( id_t ), + .sam_idx_t ( sam_idx_t ), + .mask_sel_t ( mask_sel_t ) ) i_wide_meta_buffer ( .clk_i, .rst_ni, .test_enable_i, + .id_i ( id_i ), .axi_req_i ( axi_wide_meta_buf_req_in ), .axi_rsp_o ( axi_wide_meta_buf_rsp_out ), .axi_req_o ( axi_wide_meta_buf_req_out ), @@ -1218,8 +1374,8 @@ module floo_nw_chimney #( axi_err_slv #( .AxiIdWidth ( AxiCfgW.InIdWidth ), .ATOPs ( 1'b1 ), - .axi_req_t ( axi_wide_in_req_t ), - .axi_resp_t ( axi_wide_in_rsp_t ) + .axi_req_t ( axi_wide_req_t ), + .axi_resp_t ( axi_wide_rsp_t ) ) i_axi_err_slv ( .clk_i ( clk_i ), .rst_ni ( rst_ni ), diff --git a/hw/floo_nw_router.sv b/hw/floo_nw_router.sv index e18c786a0..8e9b144e3 100644 --- a/hw/floo_nw_router.sv +++ b/hw/floo_nw_router.sv @@ -6,6 +6,7 @@ `include "axi/typedef.svh" `include "floo_noc/typedef.svh" +`include "common_cells/registers.svh" /// Wrapper of a multi-link router for narrow and wide links module floo_nw_router #( @@ -28,6 +29,8 @@ module floo_nw_router #( /// Disable illegal connections in router /// (only applies for `RouteAlgo == XYRouting`) parameter bit XYRouteOpt = 1'b1, + /// Enable multicast feature + parameter bit EnMultiCast = 1'b0, /// Node ID type parameter type id_t = logic, /// Header type @@ -120,23 +123,26 @@ module floo_nw_router #( end floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), .NumInput ( NumInputs ), .NumOutput ( NumOutputs ), - .flit_t ( floo_req_generic_flit_t ), + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), .InFifoDepth ( InFifoDepth ), .OutFifoDepth ( OutFifoDepth ), .RouteAlgo ( RouteAlgo ), .XYRouteOpt ( XYRouteOpt ), - .id_t ( id_t ), .NumAddrRules ( NumAddrRules ), - .addr_rule_t ( addr_rule_t ) + .NoLoopback ( 1'b1 ), + .EnMultiCast ( EnMultiCast ), + .EnReduction ( 1'b0 ), + .id_t ( id_t ), + .addr_rule_t ( addr_rule_t ), + .flit_t ( floo_req_generic_flit_t ) ) i_req_floo_router ( .clk_i, .rst_ni, .test_enable_i, - .xy_id_i(id_i), + .xy_id_i ( id_i ), .id_route_map_i, .valid_i ( req_valid_in ), .ready_o ( req_ready_out ), @@ -146,25 +152,48 @@ module floo_nw_router #( .data_o ( req_out ) ); + // We construct the masks for the narrow and wide B responses here. + // Every bit of the payload is set to 0, except for the bits that + // correspond to the resp field. + localparam axi_narrow_b_chan_t NarrowBMask = '{resp: 2'b11, default: '0}; + localparam floo_axi_narrow_b_flit_t NarrowBFlitMask = '{ + payload: NarrowBMask, + hdr: '0, + rsvd: '0 + }; + localparam axi_narrow_b_chan_t WideBMask = '{resp: 2'b11, default: '0}; + localparam floo_axi_wide_b_flit_t WideBFlitMask = '{ + payload: WideBMask, + hdr: '0, + rsvd: '0 + }; + // Enable reduction for the B response. + // Disable multicast for the B response. floo_router #( - .NumPhysChannels ( 1 ), - .NumVirtChannels ( 1 ), .NumInput ( NumInputs ), .NumOutput ( NumOutputs ), + .NumPhysChannels ( 1 ), + .NumVirtChannels ( 1 ), .InFifoDepth ( InFifoDepth ), .OutFifoDepth ( OutFifoDepth ), .RouteAlgo ( RouteAlgo ), .XYRouteOpt ( XYRouteOpt ), - .flit_t ( floo_rsp_generic_flit_t ), - .id_t ( id_t ), .NumAddrRules ( NumAddrRules ), - .addr_rule_t ( addr_rule_t ) + .NoLoopback ( 1'b1 ), + .EnMultiCast ( 1'b0 ), + .EnReduction ( EnMultiCast ), + .id_t ( id_t ), + .addr_rule_t ( addr_rule_t ), + .flit_t ( floo_rsp_generic_flit_t ), + .payload_t ( floo_rsp_payload_t ), + .NarrowRspMask ( floo_rsp_generic_flit_t'(NarrowBFlitMask.payload) ), + .WideRspMask ( floo_rsp_generic_flit_t'(WideBFlitMask.payload) ) ) i_rsp_floo_router ( .clk_i, .rst_ni, .test_enable_i, - .xy_id_i(id_i), + .xy_id_i ( id_i ), .id_route_map_i, .valid_i ( rsp_valid_in ), .ready_o ( rsp_ready_out ), @@ -176,22 +205,25 @@ module floo_nw_router #( floo_router #( + .NumRoutes ( NumRoutes ), .NumPhysChannels ( 1 ), .NumVirtChannels ( 1 ), - .NumRoutes ( NumRoutes ), - .flit_t ( floo_wide_generic_flit_t ), .InFifoDepth ( InFifoDepth ), .OutFifoDepth ( OutFifoDepth ), .RouteAlgo ( RouteAlgo ), .XYRouteOpt ( XYRouteOpt ), - .id_t ( id_t ), .NumAddrRules ( NumAddrRules ), - .addr_rule_t ( addr_rule_t ) + .NoLoopback ( 1'b1 ), + .EnMultiCast ( EnMultiCast ), + .EnReduction ( 1'b0 ), + .id_t ( id_t ), + .addr_rule_t ( addr_rule_t ), + .flit_t ( floo_wide_generic_flit_t ) ) i_wide_req_floo_router ( .clk_i, .rst_ni, .test_enable_i, - .xy_id_i(id_i), + .xy_id_i ( id_i ), .id_route_map_i, .valid_i ( wide_valid_in ), .ready_o ( wide_ready_out ), diff --git a/hw/floo_output_arbiter.sv b/hw/floo_output_arbiter.sv new file mode 100644 index 000000000..5df88ab91 --- /dev/null +++ b/hw/floo_output_arbiter.sv @@ -0,0 +1,104 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Chen Wu + +`include "common_cells/assertions.svh" + +module floo_output_arbiter import floo_pkg::*; +#( + /// Number of input ports + parameter int unsigned NumRoutes = 1, + /// Type definitions + parameter type flit_t = logic, + parameter type payload_t = logic, + parameter payload_t NarrowRspMask = '0, + parameter payload_t WideRspMask = '0, + parameter type id_t = logic +) ( + input logic clk_i, + input logic rst_ni, + /// Current XY-coordinate of the router + input id_t xy_id_i, + /// Input ports + input logic [NumRoutes-1:0] valid_i, + output logic [NumRoutes-1:0] ready_o, + input flit_t [NumRoutes-1:0] data_i, + /// Output port + output logic valid_o, + input logic ready_i, + output flit_t data_o +); + + flit_t reduce_data_out, unicast_data_out; + logic [NumRoutes-1:0] reduce_valid_in, unicast_valid_in, reduce_ready_out, unicast_ready_out; + logic reduce_valid_out, unicast_valid_out, reduce_ready_in, unicast_ready_in; + + logic [NumRoutes-1:0] reduce_mask; + + // Determine which input ports are to be reduced + for (genvar i = 0; i < NumRoutes; i++) begin : gen_reduce_mask + assign reduce_mask[i] = (data_i[i].hdr.commtype == ParallelReduction); + end + + // Arbitrate unicasts + assign unicast_valid_in = valid_i & ~reduce_mask; + + floo_wormhole_arbiter #( + .NumRoutes ( NumRoutes ), + .flit_t ( flit_t ) + ) i_wormhole_arbiter ( + .clk_i, + .rst_ni, + .data_i, + .valid_i ( unicast_valid_in ), + .ready_o ( unicast_ready_out ), + .valid_o ( unicast_valid_out ), + .ready_i ( unicast_ready_in ), + .data_o ( unicast_data_out ) + ); + + // Arbitrate reductions + assign reduce_valid_in = valid_i & reduce_mask; + + floo_reduction_arbiter #( + .NumRoutes ( NumRoutes ), + .flit_t ( flit_t ), + .payload_t ( payload_t ), + .id_t ( id_t ), + .NarrowRspMask ( NarrowRspMask ), + .WideRspMask ( WideRspMask ) + ) i_reduction_arbiter ( + .xy_id_i, + .data_i, + .valid_i ( reduce_valid_in ), + .ready_o ( reduce_ready_out ), + .valid_o ( reduce_valid_out ), + .ready_i ( reduce_ready_in ), + .data_o ( reduce_data_out ) + ); + + // Arbitrate between wormhole and reduction arbiter + // Reductions have higher priority than unicasts (index 0) + stream_arbiter #( + .N_INP (2), + .ARBITER("prio"), + .DATA_T (flit_t) + ) i_stream_arbiter ( + .clk_i, + .rst_ni, + .inp_data_i ({unicast_data_out, reduce_data_out}), + .inp_valid_i({unicast_valid_out, reduce_valid_out}), + .inp_ready_o({unicast_ready_in, reduce_ready_in}), + .oup_data_o (data_o), + .oup_valid_o(valid_o), + .oup_ready_i(ready_i) + ); + + assign ready_o = (reduce_valid_out)? reduce_ready_out : unicast_ready_out; + + // Cannot have an output valid without at least one input valid + `ASSERT(ValidOutInvalidIn, valid_o |-> |valid_i) + +endmodule diff --git a/hw/floo_pkg.sv b/hw/floo_pkg.sv index 44b74e395..17e2b94d9 100644 --- a/hw/floo_pkg.sv +++ b/hw/floo_pkg.sv @@ -83,6 +83,48 @@ package floo_pkg; NumAxiChannels = 3'd5 } axi_ch_e; + /// The types of collective communication + typedef enum logic [1:0] { + /// Normal communication + Unicast = 2'd0, + /// Multicast communication + Multicast = 2'd1, + /// Parallel reduction operations + ParallelReduction = 2'd2, + /// Offload Reduction + OffloadReduction = 2'd3 + } collect_comm_e; + + /// Different offloadable reduction + typedef enum logic [3:0] { + R_Select = 4'b0000, // Select the first incoming flit + F_Add = 4'b0100, // FP Addition + F_Mul = 4'b0101, // FP Multiplication + F_Min = 4'b0110, // FP Min + F_Max = 4'b0111, // FP Max + A_Add = 4'b1000, // Atomic Add (signed) + A_Mul = 4'b1001, // (Non-) Atomic (signed) + A_Min_S = 4'b1010, // Atomic Min (signed) + A_Min_U = 4'b1110, // Atomic Min (unsigned) + A_Max_S = 4'b1011, // Atomic Max (signed) + A_Max_U = 4'b1111 // Atomic Max (unsigned) + } reduction_offload_op_e; + + /// Different instantanous reduction + typedef enum logic [3:0] { + SelectAW = 4'b0000, // Select the first incoming flit + CollectB = 4'b0001, // Collect the B responses from an AXI transmission + LSBAnd = 4'b0010 // AND Connect the LSB of the payload (useful for barrier ops) + } reduction_parallel_op_e; + + /// Union for both Datatype(s) - because they need to have the same size for the chimney + /// The chimney needs this information as it does not know if we support an offload reduction + /// or an parallel reduction. + typedef union packed { + reduction_offload_op_e op_offload; + reduction_parallel_op_e op_parallel; + } reduction_op_t; + /// The types of AXI channels in narrow-wide AXI network interfaces typedef enum logic [3:0] { NarrowAw = 4'd0, @@ -145,6 +187,14 @@ package floo_pkg; /// The number of routes for every routing table, /// Only used if `RouteAlgo == SourceRouting` int unsigned NumRoutes; + /// Whether to enable the multicast feature in the NoC + bit EnMultiCast; + /// Whether to use the parallel reduction on the narrow req link + bit EnParallelReduction; + /// Whether to use the offload reduction on the narrow req link + bit EnNarrowOffloadReduction; + /// Whether to use the offload reduction on the wide link + bit EnWideOffloadReduction; } route_cfg_t; /// Configuration for the network interface (chimney) @@ -207,7 +257,11 @@ package floo_pkg; XYAddrOffsetY: 0, IdAddrOffset: 0, NumSamRules: 0, - NumRoutes: 0 + NumRoutes: 0, + EnMultiCast: 1'b0, + EnParallelReduction: 1'b0, + EnNarrowOffloadReduction: 1'b0, + EnWideOffloadReduction: 1'b0 }; /// The AXI channel to link mapping in a single-AXI network interface diff --git a/hw/floo_reduction_arbiter.sv b/hw/floo_reduction_arbiter.sv new file mode 100644 index 000000000..3bd11dfee --- /dev/null +++ b/hw/floo_reduction_arbiter.sv @@ -0,0 +1,94 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Chen Wu + +module floo_reduction_arbiter import floo_pkg::*; +#( + /// Number of input ports + parameter int unsigned NumRoutes = 1, + /// Type definitions + parameter type flit_t = logic, + parameter type payload_t = logic, + // Masks used to select which bits of the payload are part of the response, + // allowing extraction of relevant bits and detection of any participant errors. + parameter payload_t NarrowRspMask = '0, + parameter payload_t WideRspMask = '0, + parameter type id_t = logic +) ( + /// Current XY-coordinate of the router + input id_t xy_id_i, + /// Input ports + input logic [NumRoutes-1:0] valid_i, + output logic [NumRoutes-1:0] ready_o, + input flit_t [NumRoutes-1:0] data_i, + /// Output port + output logic valid_o, + input logic ready_i, + output flit_t data_o +); + + // calculated expected input source lists for each input flit + logic [NumRoutes-1:0] in_route_mask; + + typedef logic [cf_math_pkg::idx_width(NumRoutes)-1:0] arb_idx_t; + arb_idx_t input_sel; + + // Use a leading zero counter to find the first valid input to reduce + lzc #( + .WIDTH(NumRoutes) + ) i_lzc ( + .in_i ( valid_i ), + .cnt_o ( input_sel ), + .empty_o () + ); + + floo_reduction_sync #( + .NumRoutes ( NumRoutes ), + .arb_idx_t ( arb_idx_t ), + .flit_t ( flit_t ), + .id_t ( id_t ) + ) i_reduction_sync ( + .sel_i ( input_sel ), + .data_i ( data_i ), + .valid_i ( valid_i ), + .xy_id_i ( xy_id_i ), + .valid_o ( valid_o ), + .in_route_mask_o ( in_route_mask ) + ); + + payload_t ReduceMask; + assign ReduceMask = data_i[input_sel].hdr.axi_ch==NarrowB? NarrowRspMask : WideRspMask; + + logic [1:0] resp; + + // Reduction operation + always_comb begin : gen_reduced_B + data_o = data_i[input_sel]; + resp = '0; + // We check every input port from which we expect a response + for (int i = 0; i < NumRoutes; i++) begin + if(in_route_mask[i]) begin + // Select only the bits of the payload that are part of the response + // and check if at least one of the participants sent an error. + automatic int j = 0; + for (int k = 0; k < $bits(ReduceMask); k++) begin + if (ReduceMask[k]) begin + resp[j] = data_i[i].payload[k]; + j++; + end + end + // If one of the responses is an error, we return an error + // otherwise we return the first response + if(resp == axi_pkg::RESP_SLVERR) begin + data_o = data_i[i]; + break; + end + end + end + end + + assign ready_o = (ready_i & valid_o)? valid_i & in_route_mask : '0; + +endmodule diff --git a/hw/floo_reduction_sync.sv b/hw/floo_reduction_sync.sv new file mode 100644 index 000000000..0d7e2e5e8 --- /dev/null +++ b/hw/floo_reduction_sync.sv @@ -0,0 +1,58 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Chen Wu + +module floo_reduction_sync import floo_pkg::*; +#( + /// Number of input ports + parameter int unsigned NumRoutes = 1, + /// Type definitions + parameter type arb_idx_t = logic, + parameter type flit_t = logic, + parameter type id_t = logic +) ( + input arb_idx_t sel_i, + input flit_t [NumRoutes-1:0] data_i, + input logic [NumRoutes-1:0] valid_i, + input id_t xy_id_i, + output logic valid_o, + output logic [NumRoutes-1:0] in_route_mask_o +); + + logic [NumRoutes-1:0] compare_same, same_and_valid; + logic all_reduction_srcs_valid; + + // Compute the input mask based on the selected input port's destination and mask fields. + // This determines which input ports are expected to participate in the reduction. + floo_route_xymask #( + .NumRoutes ( NumRoutes ), + .flit_t ( flit_t ), + .id_t ( id_t ), + .FwdMode ( 0 ) // We enable the backward mode for reduction + ) i_route_xymask ( + .channel_i ( data_i[sel_i] ), + .xy_id_i ( xy_id_i ), + .route_sel_o ( in_route_mask_o ) + ); + + for (genvar in = 0; in < NumRoutes; in++) begin : gen_routes + // Compare whether the `mask` and `dst_id` are equal to the selected input port + assign compare_same[in] = ((data_i[in].hdr.mask == data_i[sel_i].hdr.mask) && + (data_i[in].hdr.dst_id == data_i[sel_i].hdr.dst_id)); + + // Determine if this input should be considered valid for the reduction: + // If we are at the dst node and the port is the local one, we don’t wait for a + // response/reduction since it will stay locally [NoLoopBack]. + assign same_and_valid[in] = (data_i[sel_i].hdr.dst_id == xy_id_i && in == Eject) || + (compare_same[in] & valid_i[in]); + end + + // Reduction is valid only if all expected inputs [in_route_mask_o] are valid. + // Inputs not involved in the reduction are ignored [~(in_route_mask_o)]. + assign all_reduction_srcs_valid = &(same_and_valid | ~in_route_mask_o); + + // To have a valid output at least one input must be valid. + assign valid_o = (in_route_mask_o == '0)? 1'b0 : (|valid_i & all_reduction_srcs_valid); +endmodule diff --git a/hw/floo_route_comp.sv b/hw/floo_route_comp.sv index 966f3c280..c2584b226 100644 --- a/hw/floo_route_comp.sv +++ b/hw/floo_route_comp.sv @@ -15,19 +15,25 @@ module floo_route_comp parameter type id_t = logic, /// The type of the address parameter type addr_t = logic, + parameter type mask_t = addr_t, /// The type of the route parameter type route_t = logic, /// The type of the address rules - parameter type addr_rule_t = logic + parameter type addr_rule_t = logic, + parameter type mask_rule_t = logic, + parameter type mask_sel_t = logic ) ( input logic clk_i, input logic rst_ni, input id_t id_i, input addr_t addr_i, + input mask_t mask_i, input addr_rule_t [RouteCfg.NumSamRules-1:0] addr_map_i, + input mask_rule_t [RouteCfg.NumSamRules-1:0] mask_map_i, input route_t [RouteCfg.NumRoutes-1:0] route_table_i, output route_t route_o, - output id_t id_o + output id_t id_o, + output id_t mask_o ); // Use an address decoder to map the address to a destination ID. @@ -36,12 +42,17 @@ module floo_route_comp // Further, the `rule_t` requires an additional field `id`, which can be used for the return route. // The reason for that is that a request destination is given by a physical address, while the // response destination is given by the ID of the source. + localparam int unsigned AddrWidth = $bits(addr_t); if (UseIdTable && ((RouteCfg.RouteAlgo == IdTable) || (RouteCfg.RouteAlgo == XYRouting) || (RouteCfg.RouteAlgo == SourceRouting))) begin : gen_table_routing logic dec_error; + logic mask_dec_error; + mask_sel_t x_mask_sel, y_mask_sel; + addr_t x_addr_mask, y_addr_mask; + // idx_t idx; // This is simply to pass the assertions in addr_decode // It is not used otherwise, since we specify `idx_t` @@ -62,12 +73,46 @@ module floo_route_comp .en_default_idx_i ( 1'b0 ), .default_idx_i ( '0 ) ); + if (RouteCfg.EnMultiCast && RouteCfg.UseIdTable && + (RouteCfg.RouteAlgo == floo_pkg::XYRouting)) + begin : gen_mcast_mask + floo_mask_decode #( + .NumMaskRules ( RouteCfg.NumSamRules ), + .mask_rule_t ( mask_rule_t ), + .id_t ( id_t ), + .mask_sel_t ( mask_sel_t ) + ) i_mask_decode ( + .id_i ( id_o ), + .mask_x_mask ( x_mask_sel ), + .mask_y_mask ( y_mask_sel ), + .mask_map_i ( mask_map_i ), + .dec_error_o ( mask_dec_error ) + ); + always_comb begin + x_addr_mask = (({AddrWidth{1'b1}} >> (AddrWidth - x_mask_sel.len)) << x_mask_sel.offset); + y_addr_mask = (({AddrWidth{1'b1}} >> (AddrWidth - y_mask_sel.len)) << y_mask_sel.offset); + end + assign mask_o.x = (mask_i & x_addr_mask) >> x_mask_sel.offset; + assign mask_o.y = (mask_i & y_addr_mask) >> y_mask_sel.offset; + assign mask_o.port_id = '0; + `ASSERT(MaskDecodeError, !mask_dec_error) + end + else begin : gen_no_mcast_mask + assign mask_o = '0; + end `ASSERT(DecodeError, !dec_error) end else if (RouteCfg.RouteAlgo == XYRouting) begin : gen_xy_bits_routing assign id_o.port_id = '0; assign id_o.x = addr_i[RouteCfg.XYAddrOffsetX +: $bits(id_o.x)]; assign id_o.y = addr_i[RouteCfg.XYAddrOffsetY +: $bits(id_o.y)]; + if(RouteCfg.EnMultiCast) begin : gen_mcast_mask + assign mask_o.x = mask_i[RouteCfg.XYAddrOffsetX +: $bits(id_o.x)]; + assign mask_o.y = mask_i[RouteCfg.XYAddrOffsetY +: $bits(id_o.y)]; + assign mask_o.port_id = '0; + end else begin : gen_no_mcast_mask + assign mask_o = '0; + end end else if (RouteCfg.RouteAlgo == IdTable) begin : gen_id_bits_routing assign id_o = addr_i[RouteCfg.IdAddrOffset +: $bits(id_o)]; end else if (RouteCfg.RouteAlgo == SourceRouting) begin : gen_source_routing diff --git a/hw/floo_route_select.sv b/hw/floo_route_select.sv index ddfb932e7..789dca663 100644 --- a/hw/floo_route_select.sv +++ b/hw/floo_route_select.sv @@ -9,18 +9,25 @@ module floo_route_select import floo_pkg::*; #( - parameter int unsigned NumRoutes = 0, - parameter type flit_t = logic, - parameter route_algo_e RouteAlgo = IdTable, - parameter bit LockRouting = 1'b1, - /// Used for ID-based and XY routing - parameter int unsigned IdWidth = 0, - /// Used for ID-based routing - parameter int unsigned NumAddrRules = 0, - parameter type addr_rule_t = logic, - parameter type id_t = logic[IdWidth-1:0], - /// Used for source-based routing - parameter int unsigned RouteSelWidth = $clog2(NumRoutes) + /// Number of output ports + parameter int unsigned NumRoutes = 0, + /// Routing algorithm + parameter route_algo_e RouteAlgo = IdTable, + /// Enable wormhole routing i.e. locking the direction + /// until the `last` flag is received + parameter bit LockRouting = 1'b1, + /// Id Width, only used for `XYRouting` and `IdTable` + parameter int unsigned IdWidth = 0, + /// Number of address rules, only used for `IdTable` + parameter int unsigned NumAddrRules = 0, + /// Width of port index, only used for `SrcRouting` + parameter int unsigned RouteSelWidth = $clog2(NumRoutes), + /// Enable multicast routing, currently only supported for `XYRouting` + parameter bit EnMultiCast = 1'b0, + /// Various types used in the routing algorithm + parameter type flit_t = logic, + parameter type addr_rule_t = logic, + parameter type id_t = logic[IdWidth-1:0] ) ( input logic clk_i, input logic rst_ni, @@ -33,14 +40,14 @@ module floo_route_select input logic valid_i, input logic ready_i, output flit_t channel_o, - output logic [NumRoutes-1:0] route_sel_o, // One-hot route + output logic [NumRoutes-1:0] route_sel_o, output logic [RouteSelWidth-1:0] route_sel_id_o ); logic [NumRoutes-1:0] route_sel; logic [RouteSelWidth-1:0] route_sel_id; -if (RouteAlgo == IdTable) begin : gen_id_table + if (RouteAlgo == IdTable) begin : gen_id_table // Routing based on an ID table passed into the router (TBD parameter or signal) // Assumes an ID field present in the flit_t @@ -95,28 +102,41 @@ if (RouteAlgo == IdTable) begin : gen_id_table // One-hot encoding of the decoded route - id_t id_in; - assign id_in = id_t'(channel_i.hdr.dst_id); - - always_comb begin : proc_route_sel - route_sel_id = East; - if (id_in.x == xy_id_i.x && id_in.y == xy_id_i.y) begin - route_sel_id = Eject + channel_i.hdr.dst_id.port_id; - end else if (id_in.x == xy_id_i.x) begin - if (id_in.y < xy_id_i.y) begin - route_sel_id = South; - end else begin - route_sel_id = North; - end - end else begin - if (id_in.x < xy_id_i.x) begin - route_sel_id = West; + if (EnMultiCast) begin : gen_mcast_route_sel + floo_route_xymask #( + .NumRoutes ( NumRoutes ), + .flit_t ( flit_t ), + .id_t ( id_t ), + .FwdMode ( 1 ) + ) i_route_xymask ( + .channel_i ( channel_i ), + .xy_id_i ( xy_id_i ), + .route_sel_o ( route_sel ) + ); + assign route_sel_id = '0; // Not defined in multicast + end else begin : gen_route_sel + id_t id_in; + assign id_in = id_t'(channel_i.hdr.dst_id); + always_comb begin + route_sel_id = East; + if (id_in.x == xy_id_i.x && id_in.y == xy_id_i.y) begin + route_sel_id = Eject + channel_i.hdr.dst_id.port_id; + end else if (id_in.x == xy_id_i.x) begin + if (id_in.y < xy_id_i.y) begin + route_sel_id = South; + end else begin + route_sel_id = North; + end end else begin - route_sel_id = East; + if (id_in.x < xy_id_i.x) begin + route_sel_id = West; + end else begin + route_sel_id = East; + end end + route_sel = '0; + route_sel[route_sel_id] = 1'b1; end - route_sel = '0; - route_sel[route_sel_id] = 1'b1; end assign channel_o = channel_i; diff --git a/hw/floo_route_xymask.sv b/hw/floo_route_xymask.sv new file mode 100644 index 000000000..ad0521bdf --- /dev/null +++ b/hw/floo_route_xymask.sv @@ -0,0 +1,118 @@ +// Copyright 2025 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Author: Chen Wu + +module floo_route_xymask + import floo_pkg::*; +#( + /// Number of output ports + parameter int unsigned NumRoutes = 0, + /// The type of mask to be computed + /// 1: Determine output directions of the forward path in Multicast + /// 0: Determine input directions of the backward path in Multicast i.e the reduction + parameter bit FwdMode = 1'b1, + /// Various types + parameter type flit_t = logic, + parameter type id_t = logic +) ( + // The input flit (only the header is used) + input flit_t channel_i, + // The current XY-coordinate of the router + input id_t xy_id_i, + // The calculated mask for the multicast/reduction + output logic [NumRoutes-1:0] route_sel_o +); + + logic [NumRoutes-1:0] route_sel; + + id_t dst_id, mask_in, src_id; + id_t dst_id_max, dst_id_min; + logic x_matched, y_matched; + + // In the forward path, we use the normal `dst_id` to compute the mask. + // In the backward path, we use the `src_id` which was the original + // `dst_id` in from the forward path. + assign dst_id = (FwdMode)? channel_i.hdr.dst_id : channel_i.hdr.src_id; + assign src_id = (FwdMode)? channel_i.hdr.src_id : channel_i.hdr.dst_id; + // TODO(fischeti): Clarify with Chen why `ParallelReduction` are excluded + assign mask_in = (FwdMode && channel_i.hdr.commtype==ParallelReduction)? + '0 : channel_i.hdr.mask; + + // We compute minimum and maximum destination IDs, to decide whether + // we need to send left and/or right resp. up and/or down. + assign dst_id_max.x = dst_id.x | mask_in.x; + assign dst_id_max.y = dst_id.y | mask_in.y; + assign dst_id_min.x = dst_id.x & (~mask_in.x); + assign dst_id_min.y = dst_id.y & (~mask_in.y); + + // `x/y_matched` means whether the current coordinate is a + // receiver of the the multicast. + assign x_matched = &(mask_in.x | ~(xy_id_i.x ^ dst_id.x)); + assign y_matched = &(mask_in.y | ~(xy_id_i.y ^ dst_id.y)); + + always_comb begin + route_sel = '0; + if (FwdMode) begin : gen_out_mask + // If both x and y are matched, we eject the flit + if (x_matched && y_matched) begin + route_sel[Eject] = 1; + end + // If the multicast was issued from an endpoint in the same row + // i.e. the same Y-coordinate, we forward it to `East` if: + // 1. The request is incoming from `West` or `Eject` and + // 2. There are more multicast destinations in the `East` direction + // The same applies to the `West` direction. + if (xy_id_i.y == src_id.y) begin + if (xy_id_i.x >= src_id.x && xy_id_i.x < dst_id_max.x) begin + route_sel[East] = 1; + end + if (xy_id_i.x <= src_id.x && xy_id_i.x > dst_id_min.x) begin + route_sel[West] = 1; + end + end + // If there are multicast destinations in the current column, + // We inject it to `North` if: + // 1. The request is incoming from `South` or `Eject` and + // 2. There are more multicast destinations in the `North` direction + // The same applies to the `South` direction. + if (x_matched) begin + if (xy_id_i.y >= src_id.y && xy_id_i.y < dst_id_max.y) begin + route_sel[North] = 1; + end + if (xy_id_i.y <= src_id.y && xy_id_i.y > dst_id_min.y) begin + route_sel[South] = 1; + end + end + end + + // TODO(fischeti): Clarify with Chen why `YXRouting` is used + // for the backward path + else begin : gen_in_mask + // If we previously ejected the flit, we expect one again + if (x_matched && y_matched) begin + route_sel[Eject] = 1; + end + // This is the same as the forward path, but we use the + // `YXRouting` algorithm to compute the mask. + if (xy_id_i.x == src_id.x) begin + if (xy_id_i.y >= src_id.y && xy_id_i.y < dst_id_max.y) begin + route_sel[North] = 1; + end + if (xy_id_i.y <= src_id.y && xy_id_i.y > dst_id_min.y) begin + route_sel[South] = 1; + end + end + if (y_matched) begin + if (xy_id_i.x >= src_id.x && xy_id_i.x < dst_id_max.x) begin + route_sel[East] = 1; + end + if (xy_id_i.x <= src_id.x && xy_id_i.x > dst_id_min.x) begin + route_sel[West] = 1; + end + end + end + end + assign route_sel_o = route_sel; +endmodule diff --git a/hw/floo_router.sv b/hw/floo_router.sv index 323b7be88..cea85e11f 100644 --- a/hw/floo_router.sv +++ b/hw/floo_router.sv @@ -3,45 +3,66 @@ // SPDX-License-Identifier: SHL-0.51 // // Michael Rogenmoser +// Lorenzo Leone `include "common_cells/assertions.svh" +`include "common_cells/registers.svh" /// A simple router with configurable number of ports, physical and virtual channels, and input/output buffers module floo_router import floo_pkg::*; #( + /// Number of ports parameter int unsigned NumRoutes = 0, + /// More fine-grained control over number of input ports + parameter int unsigned NumInput = NumRoutes, + /// More fine-grained control over number of output ports + parameter int unsigned NumOutput = NumRoutes, + /// Number of virtual channels parameter int unsigned NumVirtChannels = 0, + /// Number of physical channels parameter int unsigned NumPhysChannels = 1, - parameter type flit_t = logic, + /// Depth of input FIFOs parameter int unsigned InFifoDepth = 0, + /// Depth of output FIFOs parameter int unsigned OutFifoDepth = 0, + /// Routing algorithm parameter route_algo_e RouteAlgo = IdTable, - /// Used for ID-based and XY routing + /// Parameters, only used for ID-based and XY routing parameter int unsigned IdWidth = 0, parameter type id_t = logic[IdWidth-1:0], /// Used for ID-based routing parameter int unsigned NumAddrRules = 1, - parameter type addr_rule_t = logic, /// Configuration parameters for special network topologies - parameter int unsigned NumInput = NumRoutes, - parameter int unsigned NumOutput = NumRoutes, + /// Disables Y->X connections in XYRouting parameter bit XYRouteOpt = 1'b1, - parameter bit NoLoopback = 1'b1 + /// Disables loopback connections + parameter bit NoLoopback = 1'b1, + /// Enable Multicast feature + parameter bit EnMultiCast = 1'b0, + /// Enable reduction feature + parameter bit EnReduction = 1'b0, + /// Various types + parameter type addr_rule_t = logic, + parameter type flit_t = logic, + parameter type payload_t = logic, + parameter payload_t NarrowRspMask = '0, + parameter payload_t WideRspMask = '0 ) ( input logic clk_i, input logic rst_ni, input logic test_enable_i, - - input id_t xy_id_i, // if unused assign to '0 - input addr_rule_t [NumAddrRules-1:0] id_route_map_i, // if unused assign to '0 - - input logic [NumInput-1:0][NumVirtChannels-1:0] valid_i, // NOT AXI, requires ready first - output logic [NumInput-1:0][NumVirtChannels-1:0] ready_o, // NOT AXI, requires ready first + /// Only used for `XYRouting`, tie to '0 otherwise + input id_t xy_id_i, + /// Only used for `IdTable` routing, tie to '0 otherwise + input addr_rule_t [NumAddrRules-1:0] id_route_map_i, + /// Input channels + input logic [NumInput-1:0][NumVirtChannels-1:0] valid_i, + output logic [NumInput-1:0][NumVirtChannels-1:0] ready_o, input flit_t [NumInput-1:0][NumPhysChannels-1:0] data_i, - - output logic [NumOutput-1:0][NumVirtChannels-1:0] valid_o, // NOT AXI, requires ready first - input logic [NumOutput-1:0][NumVirtChannels-1:0] ready_i, // NOT AXI, requires ready first + /// Output channels + output logic [NumOutput-1:0][NumVirtChannels-1:0] valid_o, + input logic [NumOutput-1:0][NumVirtChannels-1:0] ready_i, output flit_t [NumOutput-1:0][NumPhysChannels-1:0] data_o ); @@ -53,14 +74,14 @@ module floo_router logic [NumInput-1:0][NumVirtChannels-1:0][NumOutput-1:0] route_mask; // Router input part - for (genvar in_route = 0; in_route < NumInput; in_route++) begin : gen_input - for (genvar v_chan = 0; v_chan < NumVirtChannels; v_chan++) begin : gen_virt_input + for (genvar in = 0; in < NumInput; in++) begin : gen_input + for (genvar v = 0; v < NumVirtChannels; v++) begin : gen_virt_input - logic [cf_math_pkg::idx_width(NumPhysChannels)-1:0] in_phys_channel; + logic [cf_math_pkg::idx_width(NumPhysChannels)-1:0] in_p; if (NumPhysChannels == 1) begin : gen_single_phys - assign in_phys_channel = '0; + assign in_p = '0; end else if (NumPhysChannels == NumVirtChannels) begin : gen_virt_eq_phys - assign in_phys_channel = v_chan; + assign in_p = v; end else begin : gen_odd_phys $fatal(1, "unimplemented"); end @@ -73,103 +94,150 @@ module floo_router .clk_i ( clk_i ), .rst_ni ( rst_ni ), .testmode_i ( test_enable_i ), - .flush_i ( 1'b0 ), - .usage_o ( ), - .data_i ( data_i [in_route][in_phys_channel] ), - .valid_i ( valid_i [in_route][v_chan] ), - .ready_o ( ready_o [in_route][v_chan] ), - .data_o ( in_data [in_route][v_chan] ), - .valid_o ( in_valid[in_route][v_chan] ), - .ready_i ( in_ready[in_route][v_chan] ) + .flush_i ( 1'b0 ), + .usage_o ( ), + .data_i ( data_i [in][in_p] ), + .valid_i ( valid_i [in][v] ), + .ready_o ( ready_o [in][v] ), + .data_o ( in_data [in][v] ), + .valid_o ( in_valid[in][v] ), + .ready_i ( in_ready[in][v] ) ); floo_route_select #( - .NumRoutes ( NumOutput ), - .flit_t ( flit_t ), - .RouteAlgo ( RouteAlgo ), - .IdWidth ( IdWidth ), - .id_t ( id_t ), - .NumAddrRules ( NumAddrRules ), - .addr_rule_t ( addr_rule_t ) + .NumRoutes ( NumOutput ), + .flit_t ( flit_t ), + .RouteAlgo ( RouteAlgo ), + .IdWidth ( IdWidth ), + .id_t ( id_t ), + .NumAddrRules ( NumAddrRules ), + .addr_rule_t ( addr_rule_t ), + .EnMultiCast ( EnMultiCast ) ) i_route_select ( .clk_i, .rst_ni, .test_enable_i, - .xy_id_i ( xy_id_i ), - .id_route_map_i ( id_route_map_i ), - .channel_i ( in_data [in_route][v_chan] ), - .valid_i ( in_valid [in_route][v_chan] ), - .ready_i ( in_ready [in_route][v_chan] ), - .channel_o ( in_routed_data[in_route][v_chan] ), - .route_sel_o ( route_mask [in_route][v_chan] ), - .route_sel_id_o ( ) + .xy_id_i ( xy_id_i ), + .id_route_map_i ( id_route_map_i ), + .channel_i ( in_data [in][v] ), + .valid_i ( in_valid [in][v] ), + .ready_i ( in_ready [in][v] ), + .channel_o ( in_routed_data[in][v] ), + .route_sel_o ( route_mask [in][v] ), + .route_sel_id_o ( ) ); end end - localparam int unsigned NumInputLimited = NoLoopback ? NumInput-1 : NumInput; - - logic [NumOutput-1:0][NumVirtChannels-1:0][NumInputLimited-1:0] masked_valid, masked_ready; - logic [NumInput-1:0][NumVirtChannels-1:0][NumOutput-1:0] masked_all_ready; - - flit_t [NumOutput-1:0][NumVirtChannels-1:0][NumInputLimited-1:0] masked_data; - - // TODO MICHAERO: reduce connections if (RouteAlgo == XYRouting) - for (genvar in_route = 0; in_route < NumInput; in_route++) begin : gen_hs_input - for (genvar v_chan = 0; v_chan < NumVirtChannels; v_chan++) begin : gen_hs_virt - for (genvar out_route = 0; out_route < NumOutput; out_route++) begin : gen_hs_output - localparam int unsigned ModInRoute = - in_route < out_route && NoLoopback ? in_route : in_route-1; - if (in_route == out_route && NoLoopback) begin : gen_inout_identical - assign masked_all_ready[in_route][v_chan][out_route] = '0; - // TODO MICHAERO: assert no loopback routing!!! - end else if ((RouteAlgo == XYRouting) && XYRouteOpt && - (in_route == South || in_route == North) && - (out_route == East || out_route == West)) begin : gen_xy_opt - assign masked_all_ready[in_route][v_chan][out_route] = '0; - assign masked_valid[out_route][v_chan][ModInRoute] = '0; - assign masked_data[out_route][v_chan][ModInRoute] = '0; - end else begin : gen_default - assign masked_all_ready[in_route][v_chan][out_route] = - masked_ready[out_route][v_chan][ModInRoute]; - assign masked_valid[out_route][v_chan][ModInRoute] = - in_valid[in_route][v_chan] & route_mask[in_route][v_chan][out_route]; - assign masked_data[out_route][v_chan][ModInRoute] = - in_routed_data[in_route][v_chan]; + + logic [NumOutput-1:0][NumVirtChannels-1:0][NumInput-1:0] masked_valid, masked_ready; + logic [NumInput-1:0][NumVirtChannels-1:0][NumOutput-1:0] masked_valid_transposed; + logic [NumInput-1:0][NumVirtChannels-1:0][NumOutput-1:0] masked_ready_transposed; + logic [NumInput-1:0][NumVirtChannels-1:0][NumOutput-1:0] past_handshakes_q, past_handshakes_d; + logic [NumInput-1:0][NumVirtChannels-1:0][NumOutput-1:0] current_handshakes, all_handshakes; + logic [NumInput-1:0][NumVirtChannels-1:0][NumOutput-1:0] ignore_routes, expected_handshakes; + + flit_t [NumOutput-1:0][NumVirtChannels-1:0][NumInput-1:0] masked_data; + + for (genvar in = 0; in < NumInput; in++) begin : gen_hs_input + for (genvar v = 0; v < NumVirtChannels; v++) begin : gen_hs_virt + for (genvar out = 0; out < NumOutput; out++) begin : gen_hs_output + // In case of loopback connections (to itself) and Y->X connections in XYRouting, + // we tie the handshake & data signals to 0, to optimize them away during synthesis + if((NoLoopback && (in == out)) || + ((RouteAlgo == XYRouting) && XYRouteOpt && + (in == South || in == North) && (out == East || out == West))) + begin : gen_no_conn + assign masked_ready_transposed[in][v][out] = '0; + assign masked_valid[out][v][in] = '0; + assign masked_data[out][v][in] = '0; + end else begin : gen_conn + assign masked_ready_transposed[in][v][out] = masked_ready[out][v][in]; + assign masked_valid[out][v][in] = in_valid[in][v] & route_mask[in][v][out] & + (!EnMultiCast || ~past_handshakes_q[in][v][out]); + assign masked_data[out][v][in] = in_routed_data[in][v]; end + assign masked_valid_transposed[in][v][out] = masked_valid[out][v][in]; + end + if (!EnMultiCast) begin : gen_unicast + assign in_ready[in][v] = |(masked_ready_transposed[in][v] & route_mask[in][v]); + end else begin : gen_multicast + // In the case of multicast transactions, each destination can assert the ready signal + // independently and potentially at different clock cycles. This logic ensures that + // the upstream sender is only acknowledged when all selected downstream destinations + // have successfully completed their handshake (valid & ready). + // + // Handshake received in current cycle + assign current_handshakes[in][v] = masked_valid_transposed[in][v] & + masked_ready_transposed[in][v]; + // Handhsake received in previous cycles + assign past_handshakes_d[in][v] = (in_ready[in][v] & in_valid[in][v]) ? '0 : + (past_handshakes_q[in][v] | current_handshakes[in][v]); + // History of handshake received (past + present) + assign all_handshakes[in][v] = past_handshakes_q[in][v] | current_handshakes[in][v]; + + // Handshake are excepeted on all selected routes except the loopback + assign ignore_routes[in][v] = NoLoopback ? (1 << in) : '0; + assign expected_handshakes[in][v] = route_mask[in][v] & ~ignore_routes[in][v]; + + // Send ready upstream only when all expected downstream handhsalkes have been received + assign in_ready[in][v] = &(all_handshakes[in][v] | ~expected_handshakes[in][v]); end - assign in_ready[in_route][v_chan] = - |(masked_all_ready[in_route][v_chan] & route_mask[in_route][v_chan]); end end + `FF(past_handshakes_q, past_handshakes_d, '0) flit_t [NumOutput-1:0][NumVirtChannels-1:0] out_data, out_buffered_data; logic [NumOutput-1:0][NumVirtChannels-1:0] out_valid, out_ready; logic [NumOutput-1:0][NumVirtChannels-1:0] out_buffered_valid, out_buffered_ready; - for (genvar out_route = 0; out_route < NumOutput; out_route++) begin : gen_output + for (genvar out = 0; out < NumOutput; out++) begin : gen_output // arbitrate input fifos per virtual channel - for (genvar v_chan = 0; v_chan < NumVirtChannels; v_chan++) begin : gen_virt_output - - floo_wormhole_arbiter #( - .NumRoutes ( NumInputLimited ), - .flit_t ( flit_t ) - ) i_wormhole_arbiter ( - .clk_i, - .rst_ni, - - .valid_i ( masked_valid[out_route][v_chan] ), - .ready_o ( masked_ready[out_route][v_chan] ), - .data_i ( masked_data [out_route][v_chan] ), - - .valid_o ( out_valid[out_route][v_chan] ), - .ready_i ( out_ready[out_route][v_chan] ), - .data_o ( out_data [out_route][v_chan] ) - ); + for (genvar v = 0; v < NumVirtChannels; v++) begin : gen_virt_output + if(!EnReduction) begin : gen_wh_arb + floo_wormhole_arbiter #( + .NumRoutes ( NumInput ), + .flit_t ( flit_t ) + ) i_wormhole_arbiter ( + .clk_i, + .rst_ni, + + .valid_i ( masked_valid[out][v] ), + .ready_o ( masked_ready[out][v] ), + .data_i ( masked_data [out][v] ), + + .valid_o ( out_valid[out][v] ), + .ready_i ( out_ready[out][v] ), + .data_o ( out_data [out][v] ) + ); + end else begin : gen_red_arb + // Arbiter to be instantiated for reduction operations. + // Repsonses from a multicast request are also treated as reductions. + floo_output_arbiter #( + .NumRoutes ( NumInput ), + .flit_t ( flit_t ), + .payload_t ( payload_t ), + .NarrowRspMask ( NarrowRspMask ), + .WideRspMask ( WideRspMask ), + .id_t ( id_t ) + ) i_output_arbiter ( + .clk_i, + .rst_ni, + + .valid_i ( masked_valid[out][v] ), + .ready_o ( masked_ready[out][v] ), + .data_i ( masked_data [out][v] ), + .xy_id_i ( xy_id_i ), + + .valid_o ( out_valid[out][v] ), + .ready_i ( out_ready[out][v] ), + .data_o ( out_data [out][v] ) + ); + end if (OutFifoDepth > 0) begin : gen_out_fifo (* ungroup *) @@ -180,19 +248,19 @@ module floo_router .clk_i ( clk_i ), .rst_ni ( rst_ni ), .testmode_i ( test_enable_i ), - .flush_i ( 1'b0 ), - .usage_o ( ), - .data_i ( out_data [out_route][v_chan] ), - .valid_i ( out_valid [out_route][v_chan] ), - .ready_o ( out_ready [out_route][v_chan] ), - .data_o ( out_buffered_data [out_route][v_chan] ), - .valid_o ( out_buffered_valid[out_route][v_chan] ), - .ready_i ( out_buffered_ready[out_route][v_chan] ) + .flush_i ( 1'b0 ), + .usage_o ( ), + .data_i ( out_data [out][v] ), + .valid_i ( out_valid [out][v] ), + .ready_o ( out_ready [out][v] ), + .data_o ( out_buffered_data [out][v] ), + .valid_o ( out_buffered_valid[out][v] ), + .ready_i ( out_buffered_ready[out][v] ) ); end else begin : gen_no_out_fifo - assign out_buffered_data [out_route][v_chan] = out_data [out_route][v_chan]; - assign out_buffered_valid[out_route][v_chan] = out_valid [out_route][v_chan]; - assign out_ready [out_route][v_chan] = out_buffered_ready[out_route][v_chan]; + assign out_buffered_data [out][v] = out_data [out][v]; + assign out_buffered_valid[out][v] = out_valid [out][v]; + assign out_ready [out][v] = out_buffered_ready[out][v]; end end @@ -205,13 +273,13 @@ module floo_router .clk_i, .rst_ni, - .valid_i ( out_buffered_valid[out_route] ), - .ready_o ( out_buffered_ready[out_route] ), - .data_i ( out_buffered_data [out_route] ), + .valid_i ( out_buffered_valid[out] ), + .ready_o ( out_buffered_ready[out] ), + .data_i ( out_buffered_data [out] ), - .ready_i ( ready_i [out_route] ), - .valid_o ( valid_o [out_route] ), - .data_o ( data_o [out_route] ) + .ready_i ( ready_i [out] ), + .valid_o ( valid_o [out] ), + .data_o ( data_o [out] ) ); end @@ -244,4 +312,17 @@ module floo_router end end + // If `NoLoopback` is enabled, assert that no loopback occurs + if (NoLoopback) begin: gen_no_loopback_assert + for (genvar in = 0; in < NumInput; in++) begin : gen_input + for (genvar v = 0; v < NumVirtChannels; v++) begin : gen_virt + `ASSERT(NoLoopback, !(in_valid[in][v] && route_mask[in][v][in] && + (in_data[in][v].hdr.commtype == Unicast))) + end + end + end + + // Multicast is currently only supported for `XYRouting` + `ASSERT_INIT(NoMultiCastSupport, !(EnMultiCast && RouteAlgo != XYRouting)) + endmodule diff --git a/hw/floo_wormhole_arbiter.sv b/hw/floo_wormhole_arbiter.sv index 2d264f1e0..6dee62b30 100644 --- a/hw/floo_wormhole_arbiter.sv +++ b/hw/floo_wormhole_arbiter.sv @@ -5,6 +5,7 @@ // Michael Rogenmoser `include "common_cells/registers.svh" +`include "common_cells/assertions.svh" /// A wormhole arbiter module floo_wormhole_arbiter import floo_pkg::*; @@ -59,7 +60,8 @@ module floo_wormhole_arbiter import floo_pkg::*; assign data_o = data_i [valid_selected_idx]; always_comb begin : proc_ready_o ready_o = '0; - ready_o[valid_selected_idx] = ready_i; + // when valid_i is invalid, there's no generated ready bit + ready_o[valid_selected_idx] = (|valid_i)? ready_i : '0; end assign last_out = data_o.hdr.last & valid_o; @@ -74,4 +76,6 @@ module floo_wormhole_arbiter import floo_pkg::*; `FF(valid_q, valid_d, '0) `FF(last_q, last_out & ready_i, '0) + `ASSERT(InvalidCreation, valid_o |-> |valid_i) + endmodule diff --git a/hw/include/floo_noc/typedef.svh b/hw/include/floo_noc/typedef.svh index c7ca0fb98..478315d9e 100644 --- a/hw/include/floo_noc/typedef.svh +++ b/hw/include/floo_noc/typedef.svh @@ -47,15 +47,18 @@ // // For `SourceRouting`: // `FLOO_TYPEDEF_HDR_T(hdr_t, route_t, id_t, floo_pkg::axi_ch_e, logic) -`define FLOO_TYPEDEF_HDR_T(hdr_t, dst_t, src_t, ch_t, rob_idx_t) \ +`define FLOO_TYPEDEF_HDR_T(hdr_t, dst_t, src_t, ch_t, rob_idx_t, mask_t = logic, collect_comm_t = logic, reduction_t = logic) \ typedef struct packed { \ logic rob_req; \ rob_idx_t rob_idx; \ dst_t dst_id; \ + mask_t mask; \ src_t src_id; \ logic last; \ logic atop; \ ch_t axi_ch; \ + collect_comm_t commtype; \ + reduction_t reduction_op; \ } hdr_t; //////////////////////////////////////////////////////////////////////////////////////////////////// diff --git a/hw/synth/floo_synth_axi_chimney.sv b/hw/synth/floo_synth_axi_chimney.sv new file mode 100644 index 000000000..c4175daa6 --- /dev/null +++ b/hw/synth/floo_synth_axi_chimney.sv @@ -0,0 +1,60 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer + +module floo_synth_axi_chimney + import floo_pkg::*; + import floo_synth_params_pkg::*; + import floo_synth_axi_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic test_enable_i, + input axi_in_req_t axi_in_req_i, + output axi_in_rsp_t axi_in_rsp_o, + output axi_out_req_t axi_out_req_o, + input axi_out_rsp_t axi_out_rsp_i, + input id_t id_i, + input route_t [RouteCfg.NumRoutes-1:0] route_table_i, + output floo_req_t floo_req_o, + output floo_rsp_t floo_rsp_o, + input floo_req_t floo_req_i, + input floo_rsp_t floo_rsp_i +); + + floo_axi_chimney #( + .AxiCfg ( AxiCfg ), + .ChimneyCfg ( ChimneyCfg ), + .RouteCfg ( RouteCfg ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .id_t ( id_t ), + .route_t ( route_t ), + .dst_t ( route_t ), + .hdr_t ( hdr_t ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ) + ) i_floo_axi_chimney ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .sram_cfg_i ( '0 ), + .axi_in_req_i ( axi_in_req_i ), + .axi_in_rsp_o ( axi_in_rsp_o ), + .axi_out_req_o ( axi_out_req_o ), + .axi_out_rsp_i ( axi_out_rsp_i ), + .id_i ( id_i ), + .route_table_i ( route_table_i ), + .floo_req_o ( floo_req_o ), + .floo_rsp_o ( floo_rsp_o ), + .floo_req_i ( floo_req_i ), + .floo_rsp_i ( floo_rsp_i ) + ); + +endmodule diff --git a/hw/synth/floo_synth_axi_router.sv b/hw/synth/floo_synth_axi_router.sv new file mode 100644 index 000000000..beb081565 --- /dev/null +++ b/hw/synth/floo_synth_axi_router.sv @@ -0,0 +1,49 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Michael Rogenmoser + +module floo_synth_axi_router + import floo_pkg::*; + import floo_synth_params_pkg::*; + import floo_synth_axi_pkg::*; +#( + parameter int unsigned NumPorts = int'(floo_pkg::NumDirections) +) ( + input logic clk_i, + input logic rst_ni, + input logic test_enable_i, + input id_t id_i, + input logic id_route_map_i, + input floo_req_t [NumPorts-1:0] floo_req_i, + input floo_rsp_t [NumPorts-1:0] floo_rsp_i, + output floo_req_t [NumPorts-1:0] floo_req_o, + output floo_rsp_t [NumPorts-1:0] floo_rsp_o +); + + floo_axi_router #( + .AxiCfg ( AxiCfg ), + .RouteAlgo ( RouteCfg.RouteAlgo ), + .NumRoutes ( NumPorts ), + .NumAddrRules ( 1 ), + .InFifoDepth ( InFifoDepth ), + .OutFifoDepth ( OutFifoDepth ), + .XYRouteOpt ( 1'b0 ), + .id_t ( id_t ), + .hdr_t ( hdr_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ) + ) i_floo_axi_router ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .id_i ( id_i ), + .id_route_map_i ( id_route_map_i ), + .floo_req_i ( floo_req_i ), + .floo_rsp_i ( floo_rsp_i ), + .floo_req_o ( floo_req_o ), + .floo_rsp_o ( floo_rsp_o ) + ); + +endmodule diff --git a/hw/synth/floo_synth_nw_chimney.sv b/hw/synth/floo_synth_nw_chimney.sv new file mode 100644 index 000000000..da3385c0f --- /dev/null +++ b/hw/synth/floo_synth_nw_chimney.sv @@ -0,0 +1,79 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer + +module floo_synth_nw_chimney + import floo_pkg::*; + import floo_synth_params_pkg::*; + import floo_synth_nw_pkg::*; +( + input logic clk_i, + input logic rst_ni, + input logic test_enable_i, + input axi_narrow_in_req_t axi_narrow_in_req_i, + output axi_narrow_in_rsp_t axi_narrow_in_rsp_o, + output axi_narrow_out_req_t axi_narrow_out_req_o, + input axi_narrow_out_rsp_t axi_narrow_out_rsp_i, + input axi_wide_in_req_t axi_wide_in_req_i, + output axi_wide_in_rsp_t axi_wide_in_rsp_o, + output axi_wide_out_req_t axi_wide_out_req_o, + input axi_wide_out_rsp_t axi_wide_out_rsp_i, + input id_t id_i, + input route_t [RouteCfg.NumRoutes-1:0] route_table_i, + output floo_req_t floo_req_o, + output floo_rsp_t floo_rsp_o, + input floo_req_t floo_req_i, + input floo_rsp_t floo_rsp_i, + output floo_wide_t floo_wide_o, + input floo_wide_t floo_wide_i +); + + floo_nw_chimney #( + .AxiCfgN ( AxiCfgN ), + .AxiCfgW ( AxiCfgW ), + .ChimneyCfgN ( ChimneyCfg ), + .ChimneyCfgW ( ChimneyCfg ), + .RouteCfg ( RouteCfg ), + .AtopSupport ( AtopSupport ), + .MaxAtomicTxns ( MaxAtomicTxns ), + .id_t ( id_t ), + .route_t ( route_t ), + .dst_t ( route_t ), + .hdr_t ( hdr_t ), + .axi_narrow_in_req_t ( axi_narrow_in_req_t ), + .axi_narrow_in_rsp_t ( axi_narrow_in_rsp_t ), + .axi_narrow_out_req_t ( axi_narrow_out_req_t ), + .axi_narrow_out_rsp_t ( axi_narrow_out_rsp_t ), + .axi_wide_in_req_t ( axi_wide_in_req_t ), + .axi_wide_in_rsp_t ( axi_wide_in_rsp_t ), + .axi_wide_out_req_t ( axi_wide_out_req_t ), + .axi_wide_out_rsp_t ( axi_wide_out_rsp_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) + ) i_floo_nw_chimney ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .sram_cfg_i ( '0 ), + .axi_narrow_in_req_i ( axi_narrow_in_req_i ), + .axi_narrow_in_rsp_o ( axi_narrow_in_rsp_o ), + .axi_narrow_out_req_o ( axi_narrow_out_req_o ), + .axi_narrow_out_rsp_i ( axi_narrow_out_rsp_i ), + .axi_wide_in_req_i ( axi_wide_in_req_i ), + .axi_wide_in_rsp_o ( axi_wide_in_rsp_o ), + .axi_wide_out_req_o ( axi_wide_out_req_o ), + .axi_wide_out_rsp_i ( axi_wide_out_rsp_i ), + .id_i ( id_i ), + .route_table_i ( route_table_i ), + .floo_req_o ( floo_req_o ), + .floo_rsp_o ( floo_rsp_o ), + .floo_wide_o ( floo_wide_o ), + .floo_req_i ( floo_req_i ), + .floo_rsp_i ( floo_rsp_i ), + .floo_wide_i ( floo_wide_i ) + ); + +endmodule diff --git a/hw/synth/floo_synth_nw_router.sv b/hw/synth/floo_synth_nw_router.sv new file mode 100644 index 000000000..0d11e1449 --- /dev/null +++ b/hw/synth/floo_synth_nw_router.sv @@ -0,0 +1,57 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer + +module floo_synth_nw_router + import floo_pkg::*; + import floo_synth_params_pkg::*; + import floo_synth_nw_pkg::*; +#( + parameter int unsigned NumPorts = int'(floo_pkg::NumDirections) +) ( + input logic clk_i, + input logic rst_ni, + input logic test_enable_i, + + input id_t id_i, + input logic id_route_map_i, + + input floo_req_t [NumPorts-1:0] floo_req_i, + input floo_rsp_t [NumPorts-1:0] floo_rsp_i, + output floo_req_t [NumPorts-1:0] floo_req_o, + output floo_rsp_t [NumPorts-1:0] floo_rsp_o, + input floo_wide_t [NumPorts-1:0] floo_wide_i, + output floo_wide_t [NumPorts-1:0] floo_wide_o +); + + floo_nw_router #( + .AxiCfgN ( AxiCfgN ), + .AxiCfgW ( AxiCfgW ), + .RouteAlgo ( RouteCfg.RouteAlgo ), + .NumRoutes ( NumPorts ), + .NumAddrRules ( 1 ), + .InFifoDepth ( InFifoDepth ), + .OutFifoDepth ( OutFifoDepth ), + .XYRouteOpt ( 1'b0 ), + .id_t ( id_t ), + .hdr_t ( hdr_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .floo_wide_t ( floo_wide_t ) + ) i_floo_nw_router ( + .clk_i ( clk_i ), + .rst_ni ( rst_ni ), + .test_enable_i ( test_enable_i ), + .id_i ( id_i ), + .id_route_map_i ( id_route_map_i ), + .floo_req_i ( floo_req_i ), + .floo_rsp_i ( floo_rsp_i ), + .floo_req_o ( floo_req_o ), + .floo_rsp_o ( floo_rsp_o ), + .floo_wide_i ( floo_wide_i ), + .floo_wide_o ( floo_wide_o ) + ); + +endmodule diff --git a/hw/synth/floo_synth_params_pkg.sv b/hw/synth/floo_synth_params_pkg.sv new file mode 100644 index 000000000..05cda8f08 --- /dev/null +++ b/hw/synth/floo_synth_params_pkg.sv @@ -0,0 +1,135 @@ +// Copyright 2024 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer + +`include "axi/typedef.svh" +`include "floo_noc/typedef.svh" + +package floo_synth_params_pkg; + + // Router parameters + localparam int unsigned InFifoDepth = 2; + localparam int unsigned OutFifoDepth = 2; + + // Default route config for testing + localparam floo_pkg::route_cfg_t RouteCfg = '{ + RouteAlgo: floo_pkg::XYRouting, + UseIdTable: 0, + XYAddrOffsetX: 16, + XYAddrOffsetY: 20, + default: '0 // Potentially enable Multicast features + }; + + // Common chimney parameters + localparam bit AtopSupport = 1'b1; + localparam int unsigned MaxAtomicTxns = 4; + + // Default chimney config for testing + localparam floo_pkg::chimney_cfg_t ChimneyCfg = '{ + EnSbrPort: 1'b1, + EnMgrPort: 1'b1, + MaxTxns: 32, + MaxUniqueIds: 1, + MaxTxnsPerId: 32, + BRoBType: floo_pkg::NoRoB, + BRoBSize: 0, + RRoBType: floo_pkg::NoRoB, + RRoBSize: 0, + CutAx: 1'b0, + CutRsp: 1'b0 + }; + + typedef logic [1:0] x_bits_t; + typedef logic [1:0] y_bits_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + + // Unused types + typedef logic route_t; + +endpackage + +package floo_synth_axi_pkg; + + import floo_synth_params_pkg::*; + + // Axi chimney parameters + localparam floo_pkg::axi_cfg_t AxiCfg = '{ + AddrWidth: 32, + DataWidth: 64, + UserWidth: 1, + InIdWidth: 3, + OutIdWidth: 3 + }; + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, logic) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi, AxiCfg) + `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_in, AxiCfg, hdr_t) + `FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) + +endpackage + +package floo_synth_nw_pkg; + + import floo_synth_params_pkg::*; + + localparam floo_pkg::axi_cfg_t AxiCfgN = '{ + AddrWidth: 48, + DataWidth: 64, + UserWidth: 5, + InIdWidth: 4, + OutIdWidth: 2 + }; + + // AXI nw_chimney parameters + localparam floo_pkg::axi_cfg_t AxiCfgW = '{ + AddrWidth: 48, + DataWidth: 512, + UserWidth: 1, + InIdWidth: 3, + OutIdWidth: 1 + }; + + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, AxiCfgN) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, AxiCfgW) + `FLOO_TYPEDEF_NW_CHAN_ALL(axi, req, rsp, wide, axi_narrow_in, axi_wide_in, + AxiCfgN, AxiCfgW, hdr_t) + `FLOO_TYPEDEF_NW_LINK_ALL(req, rsp, wide, req, rsp, wide) + +endpackage + + +package floo_synth_nw_vc_pkg; + + import floo_synth_params_pkg::*; + + localparam floo_pkg::axi_cfg_t AxiCfgN = '{ + AddrWidth: 48, + DataWidth: 64, + UserWidth: 5, + InIdWidth: 4, + OutIdWidth: 2 + }; + + // AXI nw_chimney parameters + localparam floo_pkg::axi_cfg_t AxiCfgW = '{ + AddrWidth: 48, + DataWidth: 512, + UserWidth: 1, + InIdWidth: 3, + OutIdWidth: 1 + }; + + localparam int NumVCWidth = 2; + localparam type vc_id_t = logic[NumVCWidth:0]; + + `FLOO_TYPEDEF_VC_HDR_T(vc_hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic, vc_id_t) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, AxiCfgN) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, AxiCfgW) + `FLOO_TYPEDEF_NW_CHAN_ALL(vc_axi, vc_req, vc_rsp, vc_wide, axi_narrow_in, axi_wide_in, + AxiCfgN, AxiCfgW, vc_hdr_t) + `FLOO_TYPEDEF_NW_LINK_ALL(vc_req, vc_rsp, vc_wide, vc_req, vc_rsp, vc_wide) + +endpackage diff --git a/hw/tb/tb_floo_nw_chimney.sv b/hw/tb/tb_floo_nw_chimney.sv index ffeed1dc5..9cb3f35dc 100644 --- a/hw/tb/tb_floo_nw_chimney.sv +++ b/hw/tb/tb_floo_nw_chimney.sv @@ -49,6 +49,7 @@ module tb_floo_nw_chimney; typedef logic [1:0] x_bits_t; typedef logic [1:0] y_bits_t; `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + // `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic) `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::nw_ch_e, logic) `FLOO_TYPEDEF_AXI_FROM_CFG(axi_narrow, floo_test_pkg::AxiCfgN) `FLOO_TYPEDEF_AXI_FROM_CFG(axi_wide, floo_test_pkg::AxiCfgW) diff --git a/hw/tb/tb_floo_rob.sv b/hw/tb/tb_floo_rob.sv index c9fcf0609..8497618df 100644 --- a/hw/tb/tb_floo_rob.sv +++ b/hw/tb/tb_floo_rob.sv @@ -40,7 +40,7 @@ module tb_floo_rob; typedef logic [1:0] x_bits_t; typedef logic [1:0] y_bits_t; `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) - `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, floo_pkg::axi_ch_e, rob_idx_t) + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t) `FLOO_TYPEDEF_AXI_FROM_CFG(axi, floo_test_pkg::AxiCfg) `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_in, floo_test_pkg::AxiCfg, hdr_t) `FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) @@ -190,7 +190,7 @@ module tb_floo_rob; .NumRoutes ( floo_pkg::NumDirections ), .NumVirtChannels ( 1 ), .flit_t ( floo_req_generic_flit_t ), - .InFifoDepth ( 2 ), + .InFifoDepth ( 2 ), .RouteAlgo ( floo_pkg::XYRouting ), .id_t ( id_t ) ) i_floo_req_router ( @@ -211,7 +211,7 @@ module tb_floo_rob; .NumRoutes ( floo_pkg::NumDirections ), .NumVirtChannels ( 1 ), .flit_t ( floo_rsp_generic_flit_t ), - .InFifoDepth ( 2 ), + .InFifoDepth ( 2 ), .RouteAlgo ( floo_pkg::XYRouting ), .id_t ( id_t ) ) i_floo_rsp_router ( diff --git a/hw/tb/tb_floo_rob_multicast.sv b/hw/tb/tb_floo_rob_multicast.sv new file mode 100644 index 000000000..ed8701240 --- /dev/null +++ b/hw/tb/tb_floo_rob_multicast.sv @@ -0,0 +1,404 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer + +`include "axi/typedef.svh" +`include "axi/assign.svh" +`include "floo_noc/typedef.svh" + +`define TARGET_SIMULATION + +module tb_floo_rob_multicast; + + import floo_pkg::*; + + localparam time CyclTime = 10ns; + localparam time ApplTime = 2ns; + localparam time TestTime = 8ns; + + localparam int unsigned NumReads = 5; + // Keep number of NumWrites lower than 10 to make it works. + // If NumWrites > 10 it'll stall. This is only a TB issue. + localparam int unsigned NumWrites = 5; + + localparam int unsigned NumSlaves = 4; + + logic clk, rst_n; + + // Function to generate a chimney config with a RoB + function automatic chimney_cfg_t gen_rob_chimney_cfg(); + chimney_cfg_t cfg = ChimneyDefaultCfg; + cfg.BRoBType = SimpleRoB; + cfg.BRoBSize = 64; + cfg.RRoBType = NoRoB; + cfg.RRoBSize = 64; + return cfg; + endfunction + + function automatic axi_cfg_t gen_axi_cfg(); + axi_cfg_t cfg = floo_test_pkg::AxiCfg; + cfg.UserWidth = cfg.AddrWidth; + return cfg; + endfunction + + // Default chimney config with RoB for testing + localparam chimney_cfg_t RoBChimneyCfg = gen_rob_chimney_cfg(); + localparam axi_cfg_t McastAxiCfg = gen_axi_cfg(); + typedef logic [$clog2(RoBChimneyCfg.BRoBSize)-1:0] rob_idx_t; + + typedef logic [1:0] x_bits_t; + typedef logic [1:0] y_bits_t; + `FLOO_TYPEDEF_XY_NODE_ID_T(id_t, x_bits_t, y_bits_t, logic) + `FLOO_TYPEDEF_HDR_T(hdr_t, id_t, id_t, axi_ch_e, rob_idx_t, id_t, collect_comm_e) + `FLOO_TYPEDEF_AXI_FROM_CFG(axi, McastAxiCfg) + `FLOO_TYPEDEF_AXI_CHAN_ALL(axi, req, rsp, axi_in, McastAxiCfg, hdr_t) + `FLOO_TYPEDEF_AXI_LINK_ALL(req, rsp, req, rsp) + typedef logic [McastAxiCfg.UserWidth-1:0] user_mask_t; + typedef struct packed { + user_mask_t mcast_mask; + } mcast_user_t; + + axi_in_req_t node_mst_req; + axi_in_rsp_t node_mst_rsp; + + axi_out_req_t [NumDirections-1:0] node_slv_req; + axi_out_rsp_t [NumDirections-1:0] node_slv_rsp; + axi_in_req_t [NumDirections-1:0] node_slv_req_id_mapped; + axi_in_rsp_t [NumDirections-1:0] node_slv_rsp_id_mapped; + + for (genvar i = 0; i < NumDirections; i++) begin : gen_dir + `AXI_ASSIGN_REQ_STRUCT(node_slv_req_id_mapped[i], node_slv_req[i]) + `AXI_ASSIGN_RESP_STRUCT(node_slv_rsp_id_mapped[i], node_slv_rsp[i]) + end + + floo_req_t [NumDirections-1:0] chimney_req_out, chimney_req_in; + floo_rsp_t [NumDirections-1:0] chimney_rsp_out, chimney_rsp_in; + floo_req_chan_t [NumDirections-1:0] chimney_req_out_chan, chimney_req_in_chan; + floo_rsp_chan_t [NumDirections-1:0] chimney_rsp_out_chan, chimney_rsp_in_chan; + + logic [NumDirections-1:0] chimney_req_out_valid, chimney_req_out_ready; + logic [NumDirections-1:0] chimney_rsp_out_valid, chimney_rsp_out_ready; + logic [NumDirections-1:0] chimney_req_in_valid, chimney_req_in_ready; + logic [NumDirections-1:0] chimney_rsp_in_valid, chimney_rsp_in_ready; + + for (genvar i = 0; i < floo_pkg::NumDirections; i++) begin : gen_directions + assign chimney_req_out_chan[i] = chimney_req_out[i].req; + assign chimney_rsp_out_chan[i] = chimney_rsp_out[i].rsp; + assign chimney_req_in[i].req = chimney_req_in_chan[i]; + assign chimney_rsp_in[i].rsp = chimney_rsp_in_chan[i]; + assign chimney_req_out_valid[i] = chimney_req_out[i].valid; + assign chimney_req_out_ready[i] = chimney_req_out[i].ready; + assign chimney_rsp_out_valid[i] = chimney_rsp_out[i].valid; + assign chimney_rsp_out_ready[i] = chimney_rsp_out[i].ready; + assign chimney_req_in[i].valid = chimney_req_in_valid[i]; + assign chimney_req_in[i].ready = chimney_req_in_ready[i]; + assign chimney_rsp_in[i].valid = chimney_rsp_in_valid[i]; + assign chimney_rsp_in[i].ready = chimney_rsp_in_ready[i]; + end + + logic [1:0] end_of_sim; + + clk_rst_gen #( + .ClkPeriod ( CyclTime ), + .RstClkCycles ( 5 ) + ) i_clk_gen ( + .clk_o ( clk ), + .rst_no ( rst_n ) + ); + + //////////////////// + // Local Master // + //////////////////// + + id_t [floo_pkg::NumDirections-1:0] xy_id; + assign xy_id[floo_pkg::Eject] = '{x: 2'd1, y: 2'd1, port_id: 1'd0}; + + typedef struct packed { + int unsigned idx; + axi_addr_t start_addr; + axi_addr_t end_addr; + } node_addr_region_t; + + typedef struct packed { + int unsigned idx; + axi_addr_t addr; + axi_addr_t mask; + } node_addr_mask_region_t; + + // TODO(lleone): There is a problem here with the regions ordering. + // The first entryy is the MSB. So the order should be from the top: + // West, South, East, North + localparam int unsigned NumAddrRegions = 4; + localparam node_addr_region_t [NumAddrRegions-1:0] AddrRegions = '{ + '{idx: North, start_addr: 32'h00210000, end_addr: 32'h0021FFFF}, // North + '{idx: East, start_addr: 32'h00120000, end_addr: 32'h0012FFFF}, // East + '{idx: South, start_addr: 32'h00010000, end_addr: 32'h0001FFFF}, // South + '{idx: West, start_addr: 32'h00100000, end_addr: 32'h0010FFFF} // West + }; + + localparam node_addr_mask_region_t [NumAddrRegions-1:0] MaskAddrRegions = '{ + '{idx: North, addr: 32'h00210000, mask: 32'hFFDCFFFF}, // North + '{idx: East, addr: 32'h00120000, mask: 32'hFFFDFFFF}, // East + '{idx: South, addr: 32'h00010000, mask: 32'hFFCCFFFF}, // South + '{idx: West, addr: 32'h00100000, mask: 32'hFFFCFFFF} // West + }; + + floo_axi_test_node #( + .AxiCfg ( McastAxiCfg ), + .mst_req_t ( axi_in_req_t ), + .mst_rsp_t ( axi_in_rsp_t ), + .slv_req_t ( axi_out_req_t ), + .slv_rsp_t ( axi_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .AxiMaxBurstLen ( 4 ), + .NumAddrRegions ( NumAddrRegions ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .NumReads ( NumReads ), + .NumWrites ( NumWrites ), + .EnMultiCast ( 1 ) + ) i_test_node_0 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mst_port_req_o ( node_mst_req ), + .mst_port_rsp_i ( node_mst_rsp ), + .slv_port_req_i ( node_slv_req[floo_pkg::Eject] ), + .slv_port_rsp_o ( node_slv_rsp[floo_pkg::Eject] ), + .end_of_sim ( end_of_sim[0] ) + ); + + axi_dumper #( + .BusName ( "MasterAxi" ), + .LogAW ( 1'b1 ), + .LogAR ( 1'b1 ), + .LogW ( 1'b1 ), + .LogB ( 1'b0 ), + .LogR ( 1'b0 ), + .axi_req_t ( axi_in_req_t ), + .axi_resp_t ( axi_in_rsp_t ) + ) i_axi_dumper ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( node_mst_req ), + .axi_resp_i ( node_mst_rsp ) + ); + + floo_axi_chimney #( + .AxiCfg ( McastAxiCfg ), + .ChimneyCfg ( RoBChimneyCfg ), // Needs RoB + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( floo_test_pkg::AtopSupport ), + .MaxAtomicTxns ( floo_test_pkg::MaxAtomicTxns ), + .EnMultiCast ( 1'b1 ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ), + .rob_idx_t ( rob_idx_t ), + .id_t ( id_t ), + .hdr_t ( hdr_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .user_struct_t ( mcast_user_t ) + ) i_floo_axi_chimney ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_in_req_i ( node_mst_req ), + .axi_in_rsp_o ( node_mst_rsp ), + .axi_out_req_o ( node_slv_req[floo_pkg::Eject] ), + .axi_out_rsp_i ( node_slv_rsp[floo_pkg::Eject] ), + .id_i ( xy_id[floo_pkg::Eject] ), + .route_table_i ( '0 ), + .floo_req_o ( chimney_req_out[floo_pkg::Eject] ), + .floo_rsp_o ( chimney_rsp_out[floo_pkg::Eject] ), + .floo_req_i ( chimney_req_in[floo_pkg::Eject] ), + .floo_rsp_i ( chimney_rsp_in[floo_pkg::Eject] ) + ); + + floo_router #( + .NumRoutes ( floo_pkg::NumDirections ), + .NumVirtChannels ( 1 ), + .flit_t ( floo_req_generic_flit_t ), + .InFifoDepth ( 2 ), + .RouteAlgo ( floo_pkg::XYRouting ), + .id_t ( id_t ), + .NoLoopback ( 1'b1 ), + .EnMultiCast ( 1'b1 ) + ) i_floo_req_router ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .xy_id_i ( xy_id[floo_pkg::Eject] ), + .id_route_map_i ( '0 ), + .valid_i ( chimney_req_out_valid ), + .ready_o ( chimney_req_in_ready ), + .data_i ( chimney_req_out_chan ), + .valid_o ( chimney_req_in_valid ), + .ready_i ( chimney_req_out_ready ), + .data_o ( chimney_req_in_chan ) + ); + + floo_router #( + .NumRoutes ( floo_pkg::NumDirections ), + .NumVirtChannels ( 1 ), + .flit_t ( floo_rsp_generic_flit_t ), + .InFifoDepth ( 2 ), + .RouteAlgo ( floo_pkg::XYRouting ), + .id_t ( id_t ), + .EnReduction ( 1 ) + ) i_floo_rsp_router ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .test_enable_i ( 1'b0 ), + .xy_id_i ( xy_id[floo_pkg::Eject] ), + .id_route_map_i ( '0 ), + .valid_i ( chimney_rsp_out_valid ), + .ready_o ( chimney_rsp_in_ready ), + .data_i ( chimney_rsp_out_chan ), + .valid_o ( chimney_rsp_in_valid ), + .ready_i ( chimney_rsp_out_ready ), + .data_o ( chimney_rsp_in_chan ) + ); + + // localparam floo_test_pkg::slave_type_e SlaveType[floo_pkg::NumDirections-1] = '{ + // floo_test_pkg::FastSlave, + // floo_test_pkg::FastSlave, + // floo_test_pkg::SlowSlave, + // floo_test_pkg::MixedSlave + // }; + + // localparam floo_test_pkg::slave_type_e SlaveType[floo_pkg::NumDirections-1] = '{ + // floo_test_pkg::SlowSlave, + // floo_test_pkg::SlowSlave, + // floo_test_pkg::SlowSlave, + // floo_test_pkg::SlowSlave + // }; + + localparam floo_test_pkg::slave_type_e SlaveType[floo_pkg::NumDirections-1] = '{ + floo_test_pkg::FastSlave, + floo_test_pkg::FastSlave, + floo_test_pkg::FastSlave, + floo_test_pkg::FastSlave + }; + + for (genvar i = North; i <= West; i++) begin : gen_slaves + + if (i == North) begin : gen_north + assign xy_id[i] = '{x: 2'd1, y: 2'd2, port_id: 1'd0}; + end else if (i == South) begin : gen_south + assign xy_id[i] = '{x: 2'd1, y: 2'd0, port_id: 1'd0}; + end else if (i == East) begin : gen_east + assign xy_id[i] = '{x: 2'd2, y: 2'd1, port_id: 1'd0}; + end else if (i == West) begin : gen_west + assign xy_id[i] = '{x: 2'd0, y: 2'd1, port_id: 1'd0}; + end + + floo_axi_chimney #( + .AxiCfg ( McastAxiCfg ), + .ChimneyCfg ( floo_test_pkg::ChimneyCfg ), // Does not need RoB + .RouteCfg ( floo_test_pkg::RouteCfg ), + .AtopSupport ( floo_test_pkg::AtopSupport ), + .MaxAtomicTxns ( floo_test_pkg::MaxAtomicTxns ), + .EnMultiCast ( 1'b1 ), + .axi_in_req_t ( axi_in_req_t ), + .axi_in_rsp_t ( axi_in_rsp_t ), + .axi_out_req_t ( axi_out_req_t ), + .axi_out_rsp_t ( axi_out_rsp_t ), + .rob_idx_t ( rob_idx_t ), + .id_t ( id_t ), + .hdr_t ( hdr_t ), + .floo_req_t ( floo_req_t ), + .floo_rsp_t ( floo_rsp_t ), + .user_struct_t ( mcast_user_t ) + ) i_floo_axi_chimney ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .sram_cfg_i ( '0 ), + .test_enable_i ( 1'b0 ), + .axi_in_req_i ( '0 ), + .axi_in_rsp_o ( ), + .axi_out_req_o ( node_slv_req[i] ), + .axi_out_rsp_i ( node_slv_rsp[i] ), + .id_i ( xy_id[i] ), + .route_table_i ( '0 ), + .floo_req_o ( chimney_req_out[i] ), + .floo_rsp_o ( chimney_rsp_out[i] ), + .floo_req_i ( chimney_req_in[i] ), + .floo_rsp_i ( chimney_rsp_in[i] ) + ); + + axi_dumper #( + .BusName ( $sformatf("Slave%0d", i)), + .LogAW ( 1'b0 ), + .LogAR ( 1'b0 ), + .LogW ( 1'b0 ), + .LogB ( 1'b1 ), + .LogR ( 1'b0 ), + .axi_req_t ( axi_in_req_t ), + .axi_resp_t ( axi_in_rsp_t ) + ) i_axi_dumper ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .axi_req_i ( node_slv_req[i] ), + .axi_resp_i ( node_slv_rsp[i] ) + ); + + floo_axi_rand_slave #( + .AxiCfg ( McastAxiCfg ), + .axi_req_t ( axi_out_req_t ), + .axi_rsp_t ( axi_out_rsp_t ), + .ApplTime ( ApplTime ), + .TestTime ( TestTime ), + .SlaveType ( SlaveType[i] ), + .DstStartAddr ( 32'h0000_0000 ), // TODO: make this configurable + .DstEndAddr ( 32'h0000_8000 ) + ) i_test_node_1 ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .slv_port_req_i ( node_slv_req[i] ), + .slv_port_rsp_o ( node_slv_rsp[i] ), + .mon_mst_port_req_o ( ), + .mon_mst_port_rsp_o ( ) + ); + + end + + axi_reorder_compare_multicast #( + .NumSlaves ( NumSlaves ), + .AxiIdWidth ( McastAxiCfg.InIdWidth ), + .NumAddrRegions ( NumAddrRegions ), + .addr_t ( axi_addr_t ), + .rule_t ( node_addr_region_t ), + .AddrRegions ( AddrRegions ), + .mask_rule_t ( node_addr_mask_region_t ), + .MaskAddrRegions( MaskAddrRegions ), + .aw_chan_t ( axi_in_aw_chan_t ), + .w_chan_t ( axi_in_w_chan_t ), + .b_chan_t ( axi_in_b_chan_t ), + .ar_chan_t ( axi_in_ar_chan_t ), + .r_chan_t ( axi_in_r_chan_t ), + .req_t ( axi_in_req_t ), + .rsp_t ( axi_in_rsp_t ), + .Verbose ( 1'b0 ) + ) i_axi_reorder_compare ( + .clk_i ( clk ), + .rst_ni ( rst_n ), + .mon_mst_req_i ( node_mst_req ), + .mon_mst_rsp_i ( node_mst_rsp ), + .mon_slv_req_i ( node_slv_req_id_mapped[West:North] ), + .mon_slv_rsp_i ( node_slv_rsp_id_mapped[West:North] ), + .end_of_sim_o ( end_of_sim[1] ) + ); + + initial begin + wait(&end_of_sim); + $stop; + end + + +endmodule diff --git a/hw/tb/wave/tb_floo_nw_chimney.wave.tcl b/hw/tb/wave/tb_floo_nw_chimney.wave.tcl index e1abe9e51..64cd20d89 100644 --- a/hw/tb/wave/tb_floo_nw_chimney.wave.tcl +++ b/hw/tb/wave/tb_floo_nw_chimney.wave.tcl @@ -8,7 +8,7 @@ floo_wave_init for {set i 0} {$i < 2} {incr i} { set name [list "Chimney $i"] - floo_nw_chimney_wave tb_floo_narrow_wide_chimney/i_floo_narrow_wide_chimney_${i} $name + floo_nw_chimney_wave tb_floo_nw_chimney/i_floo_nw_chimney_${i} $name } floo_wave_style diff --git a/hw/test/axi_reorder_compare_multicast.sv b/hw/test/axi_reorder_compare_multicast.sv new file mode 100644 index 000000000..5a8150a41 --- /dev/null +++ b/hw/test/axi_reorder_compare_multicast.sv @@ -0,0 +1,468 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Tim Fischer + +/// A AXI4 Bus Monitor for verifying the order of AXI transactions with the same ID +module axi_reorder_compare_multicast #( + parameter int unsigned NumSlaves = 4, + parameter int unsigned AxiIdWidth = 4, + parameter int unsigned NumAddrRegions = 1, + parameter type addr_t = logic, + parameter type rule_t = logic, + parameter rule_t [NumAddrRegions-1:0] AddrRegions = '0, + parameter type mask_rule_t = logic, + parameter rule_t [NumAddrRegions-1:0] MaskAddrRegions = '0, + parameter bit Verbose = 0, + parameter type aw_chan_t = logic, + parameter type w_chan_t = logic, + parameter type b_chan_t = logic, + parameter type ar_chan_t = logic, + parameter type r_chan_t = logic, + parameter type req_t = logic, + parameter type rsp_t = logic, + // Derived parameters, do not change + localparam type id_t = logic [AxiIdWidth-1:0], + localparam int unsigned NumAxiIds = 2**AxiIdWidth +) ( + input logic clk_i, + input logic rst_ni, + input req_t mon_mst_req_i, + input rsp_t mon_mst_rsp_i, + input req_t [NumSlaves-1:0] mon_slv_req_i, + input rsp_t [NumSlaves-1:0] mon_slv_rsp_i, + output logic end_of_sim_o +); + + function automatic void print_aw ( + input aw_chan_t aw_expected, + input aw_chan_t aw_received + ); + // verilog_lint: waive-start line-length + $display("AW | expected | received "); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + $display("id: | %64d | %64d", aw_expected.id, aw_received.id); + $display("addr: | %64x | %64x", aw_expected.addr, aw_received.addr); + $display("len: | %64d | %64d", aw_expected.len, aw_received.len); + $display("size: | %64d | %64d", aw_expected.size, aw_received.size); + $display("burst: | %64d | %64d", aw_expected.burst, aw_received.burst); + $display("lock: | %64d | %64d", aw_expected.lock, aw_received.lock); + $display("cache: | %64d | %64d", aw_expected.cache, aw_received.cache); + $display("prot: | %64d | %64d", aw_expected.prot, aw_received.prot); + $display("qos: | %64d | %64d", aw_expected.qos, aw_received.qos); + $display("region: | %64d | %64d", aw_expected.region, aw_received.region); + $display("user: | %64x | %64x", aw_expected.user, aw_received.user); + $display("atop: | %64d | %64d", aw_expected.atop, aw_received.atop); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + // verilog_lint: waive-stop line-length + endfunction + + function automatic void print_ar ( + input ar_chan_t ar_expected, + input ar_chan_t ar_received + ); + // verilog_lint: waive-start line-length + $display("AR | expected | received "); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + $display("id: | %64d | %64d", ar_expected.id, ar_received.id); + $display("addr: | %64x | %64x", ar_expected.addr, ar_received.addr); + $display("len: | %64d | %64d", ar_expected.len, ar_received.len); + $display("size: | %64d | %64d", ar_expected.size, ar_received.size); + $display("burst: | %64d | %64d", ar_expected.burst, ar_received.burst); + $display("lock: | %64d | %64d", ar_expected.lock, ar_received.lock); + $display("cache: | %64d | %64d", ar_expected.cache, ar_received.cache); + $display("prot: | %64d | %64d", ar_expected.prot, ar_received.prot); + $display("qos: | %64d | %64d", ar_expected.qos, ar_received.qos); + $display("region: | %64d | %64d", ar_expected.region, ar_received.region); + $display("user: | %64x | %64x", ar_expected.user, ar_received.user); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + // verilog_lint: waive-stop line-length + endfunction + + function automatic void print_w ( + input w_chan_t w_expected, + input w_chan_t w_received + ); + // verilog_lint: waive-start line-length + $display("W | expected | received "); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + $display("data: | %64x | %64x", w_expected.data, w_received.data); + $display("strb: | %64d | %64d", w_expected.strb, w_received.strb); + $display("last: | %64d | %64d", w_expected.last, w_received.last); + $display("user: | %64x | %64x", w_expected.user, w_received.user); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + // verilog_lint: waive-stop line-length + endfunction + + function automatic void print_b ( + input b_chan_t b_expected, + input b_chan_t b_received + ); + // verilog_lint: waive-start line-length + $display("B | expected | received "); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + $display("id: | %64d | %64d", b_expected.id, b_received.id); + $display("resp: | %64d | %64d", b_expected.resp, b_received.resp); + $display("user: | %64x | %64x", b_expected.user, b_received.user); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + // verilog_lint: waive-stop line-length + endfunction + + function automatic void print_r ( + input r_chan_t r_expected, + input r_chan_t r_received + ); + // verilog_lint: waive-start line-length + $display("R | expected | received "); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + $display("id: | %64d | %64d", r_expected.id, r_received.id); + $display("data: | %64x | %64x", r_expected.data, r_received.data); + $display("resp: | %64d | %64d", r_expected.resp, r_received.resp); + $display("last: | %64d | %64d", r_expected.last, r_received.last); + $display("user: | %64x | %64x", r_expected.user, r_received.user); + $display("--------|------------------------------------------------------------------|-----------------------------------------------------------------"); + // verilog_lint: waive-stop line-length + endfunction + + typedef struct packed { + int unsigned slv_id; + int unsigned num_rsp; + } out_rsp_t; + + aw_chan_t aw_queue [NumSlaves][$]; + w_chan_t w_queue [NumSlaves][$]; + ar_chan_t ar_queue [NumSlaves][$]; + b_chan_t b_queue [NumSlaves][NumAxiIds][$]; + r_chan_t r_queue [NumSlaves][NumAxiIds][$]; + + out_rsp_t r_out_rsp_queue[NumAxiIds][$]; + out_rsp_t b_out_rsp_queue[NumAxiIds][$]; + + id_t aw_id_queue [NumSlaves][$]; + id_t ar_id_queue [NumSlaves][$]; + + typedef logic [$clog2(NumSlaves)-1:0] slv_id_t; + slv_id_t w_slv_idx[$]; + slv_id_t aw_slv_idx, ar_slv_idx; + logic [NumAddrRegions-1:0] multiaddr_decode_sel; + + + addr_decode #( + .NoIndices ( NumAddrRegions ), + .NoRules ( NumAddrRegions ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) + ) i_aw_addr_decode ( + .addr_i ( mon_mst_req_i.aw.addr ), + .addr_map_i ( AddrRegions ), + .dec_error_o ( ), + .dec_valid_o ( ), + .default_idx_i ( '0 ), + .en_default_idx_i ( 1'b0 ), + .idx_o ( aw_slv_idx ) + ); + + multiaddr_decode #( + .NoIndices ( NumAddrRegions ), + .NoRules ( NumAddrRegions ), + .addr_t ( addr_t ), + .rule_t ( mask_rule_t ) + ) i_aw_multiaddr_decode ( + .addr_i ( mon_mst_req_i.aw.addr ), + .mask_i ( mon_mst_req_i.aw.user ), + .addr_map_i ( MaskAddrRegions ), + .select_o ( multiaddr_decode_sel ), + .addr_o (), + .mask_o (), + .dec_valid_o (), + .dec_error_o (), + .en_default_idx_i ( '0 ), + .default_idx_i ( '0 ) + ); + + addr_decode #( + .NoIndices ( NumAddrRegions ), + .NoRules ( NumAddrRegions ), + .addr_t ( addr_t ), + .rule_t ( rule_t ) + ) i_ar_addr_decode ( + .addr_i ( mon_mst_req_i.ar.addr ), + .addr_map_i ( AddrRegions ), + .dec_error_o ( ), + .dec_valid_o ( ), + .default_idx_i ( '0 ), + .en_default_idx_i ( 1'b0 ), + .idx_o ( ar_slv_idx ) + ); + + always_ff @(posedge clk_i) begin : step_1 + if (mon_mst_req_i.aw_valid && mon_mst_rsp_i.aw_ready) begin + // for (int i=0; i + +# This is a dummy Bender.yml file to avoid missing dependency warnings +# when `floo_noc` is used as a Bender dependency in other projects. +# It will be replaced by the actual `pd` repository during CI runs. + +package: + name: floo_noc_pd + authors: + - "Tim Fischer " diff --git a/pyproject.toml b/pyproject.toml index 214316762..4c30417a8 100644 --- a/pyproject.toml +++ b/pyproject.toml @@ -5,16 +5,15 @@ [project] name = "floogen" version = "0.6.1" -authors = [ - { name="Tim Fischer", email="fischeti@iis.ee.ethz.ch" }, -] description = "A Network Generator for FlooNoC" readme = "README.md" +license = { text = "Apache-2.0" } requires-python = ">=3.10" +authors = [{ name = "Tim Fischer", email = "fischeti@iis.ee.ethz.ch" }] classifiers = [ - "Programming Language :: Python :: 3.10", - "License :: OSI Approved :: Apache License", - "Operating System :: OS Independent", + "Programming Language :: Python :: 3.10", + "License :: OSI Approved :: Apache Software License", + "Operating System :: OS Independent", ] dependencies = [ @@ -23,34 +22,37 @@ dependencies = [ "matplotlib", "mako", "ruamel.yaml", - "hjson", - "jsonref", "click", - "pylint", - "pytest", "pygame" ] -[build-system] -requires = ["setuptools>=61.0"] -build-backend = "setuptools.build_meta" - [project.urls] Homepage = "https://github.com/pulp-platform/FlooNoC" [project.scripts] floogen = "floogen.cli:main" -[tool.setuptools] -packages = [ - "floogen", - "floogen.model", - "floogen.templates", - "floogen.tests", -] +[dependency-groups] +dev = ["pytest", "ruff", "pylint"] +viz = ["pygame"] +docs = [ + "mkdocs", + "mkdocs-material", + "mkdocstrings[python]", + "pillow", + "cairosvg", + "mkdocs-git-revision-date-localized-plugin", + "mkdocs-git-committers-plugin-2", + ] -[tool.setuptools.package-data] -"floogen.templates" = ["*.mako"] +[build-system] +requires = ["uv_build>=0.9.2,<0.10.0"] +build-backend = "uv_build" + +[tool.uv.build-backend] +module-name = "floogen" +module-root = "" +wheel-exclude = ["floogen/tests/**"] [tool.pytest.ini_options] testpaths = ["floogen/tests"] @@ -58,12 +60,7 @@ testpaths = ["floogen/tests"] [tool.pylint.format] max-line-length = 100 jobs = 4 -suggestion-mode = 'yes' - -[tool.pylint.disable] -disable = [ - "C0114", # Missing module docstring -] +suggestion-mode = "yes" -[tool.black] +[tool.ruff] line-length = 100 diff --git a/util/dma_experiments_result_analysis.ipynb b/util/dma_experiments_result_analysis.ipynb index ca55e9f5d..be5fb2bc2 100644 --- a/util/dma_experiments_result_analysis.ipynb +++ b/util/dma_experiments_result_analysis.ipynb @@ -20,7 +20,7 @@ }, { "cell_type": "code", - "execution_count": 3, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -51,10 +51,10 @@ " continue\n", " elif header_match:\n", " header_match = header_match.groups()\n", - " if not header_match[0] in traffic_types:\n", + " if header_match[0] not in traffic_types:\n", " traffic_types.append(header_match[0])\n", " traffic_type = header_match[0]\n", - " if not (int(header_match[1]), int(header_match[2]), int(header_match[3])) in parameter_combinations:\n", + " if (int(header_match[1]), int(header_match[2]), int(header_match[3])) not in parameter_combinations:\n", " parameter_combinations.append((int(header_match[1]), int(header_match[2]), int(header_match[3])))\n", " parameter_combination_index = parameter_combinations.index((int(header_match[1]), int(header_match[2]), int(header_match[3])))\n", " elif data_match:\n", @@ -63,7 +63,8 @@ " else:\n", " print(\"Error: line not matched: \", line)\n", " errors+=1\n", - " if(errors > 5): break\n", + " if(errors > 5):\n", + " break\n", " traffic_types.append(\"average (geo mean)\")\n", " parameter_combinations.append(\"average (geo mean)\")\n", "\n", @@ -96,7 +97,7 @@ }, { "cell_type": "code", - "execution_count": 4, + "execution_count": null, "metadata": {}, "outputs": [], "source": [ @@ -129,10 +130,12 @@ " explanation = \"Wide Bandwidth: $100*(BW_{single}-BW_{two})\\ /\\ BW_{two}$\" if bandwidth \\\n", " else \"Narrow Latency: $100*(Lat_{single}-Lat_{two})\\ /\\ Lat_{two}$\"\n", " ax.set_title(f\"Single vs two stage original router: {explanation}\")\n", - " else: ax.set_title(f\"{experiment_name}: {explanation}\")\n", + " else:\n", + " ax.set_title(f\"{experiment_name}: {explanation}\")\n", " fig.set_size_inches(8, 8)\n", " bw_string = \"bw\" if bandwidth else \"lat\"\n", - " if write_pdf: plt.savefig(f\"util/plots/{experiment_name}_{bw_string}.pdf\", bbox_inches='tight')\n", + " if write_pdf:\n", + " plt.savefig(f\"util/plots/{experiment_name}_{bw_string}.pdf\", bbox_inches='tight')\n", " plt.show()\n", "\n", "\n", @@ -195,14 +198,14 @@ " print(f\"File not found: output/dma_experiments_{experiment_name}.txt\")\n", " experiment_names.remove(experiment_name)\n", " continue\n", - " if traffic_types == None:\n", + " if traffic_types is None:\n", " traffic_types = traffic_types_exp\n", " else: # check same traffic types exist\n", " if traffic_types != traffic_types_exp:\n", " print(f\"Traffic types in {experiment_name} do not match previous experiments\")\n", " experiment_names.remove(experiment_name)\n", " continue\n", - " if type(parameter_combination) == list:\n", + " if isinstance(parameter_combination, list):\n", " not_all_p_found = False\n", " for p in parameter_combination:\n", " if p not in parameter_combinations_exp:\n", @@ -254,7 +257,8 @@ " ax.set_title(f\"{parameter_combination_explanation}: {explanation}\")\n", " fig.set_size_inches(8, 8)\n", " bw_string = \"bw\" if bandwidth else \"lat\"\n", - " if write_pdf: plt.savefig(f\"util/plots/{parameter_combination_explanation.lower().replace(',', '').replace(' ', '_')}_{bw_string}.pdf\", bbox_inches='tight')\n", + " if write_pdf:\n", + " plt.savefig(f\"util/plots/{parameter_combination_explanation.lower().replace(',', '').replace(' ', '_')}_{bw_string}.pdf\", bbox_inches='tight')\n", " plt.show()\n", "\n", "def plot_all_parameter_combinations(bandwidth = 1, slow = 0, single_stage=0):\n", diff --git a/util/gen_jobs.py b/util/gen_jobs.py index f3999ab66..fe6d441e2 100755 --- a/util/gen_jobs.py +++ b/util/gen_jobs.py @@ -198,7 +198,8 @@ def gen_mesh_traffic( num_destinations = NUM_X * NUM_Y if source < num_destinations // 2: ext = source * 2 - else: ext = (source * 2) - num_destinations + 1 + else: + ext = (source * 2) - num_destinations + 1 ext_addr = get_xy_base_addr(ext % NUM_X, ext // NUM_X) accesses = [(ext_addr, rw, wide_length)] elif traffic_type == "transpose": diff --git a/util/verible.waiver b/util/verible.waiver index 01c51875b..7d01a0b6f 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