[VERIF] cc/interco: add plusarg-gated write-ack + addr-watch probes #164
AquaticfullerAnnotations
46 warnings
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lint-license
Node.js 20 actions are deprecated. The following actions are running on Node.js 20 and may not work as expected: actions/checkout@v3, actions/setup-python@v2. Actions will be forced to run with Node.js 24 by default starting June 2nd, 2026. Node.js 20 will be removed from the runner on September 16th, 2026. Please check if updated versions of these actions are available that support Node.js 24. To opt into Node.js 24 now, set the FORCE_JAVASCRIPT_ACTIONS_TO_NODE24=true environment variable on the runner or in your workflow file. Once Node.js 24 becomes the default, you can temporarily opt out by setting ACTIONS_ALLOW_USE_UNSECURE_NODE_VERSION=true. For more information see: https://github.blog/changelog/2025-09-19-deprecation-of-node-20-on-github-actions-runners/
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lint-sv
Node.js 20 actions are deprecated. The following actions are running on Node.js 20 and may not work as expected: actions/checkout@v3, actions/upload-artifact@v4. Actions will be forced to run with Node.js 24 by default starting June 2nd, 2026. Node.js 20 will be removed from the runner on September 16th, 2026. Please check if updated versions of these actions are available that support Node.js 24. To opt into Node.js 24 now, set the FORCE_JAVASCRIPT_ACTIONS_TO_NODE24=true environment variable on the runner or in your workflow file. Once Node.js 24 becomes the default, you can temporarily opt out by setting ACTIONS_ALLOW_USE_UNSECURE_NODE_VERSION=true. For more information see: https://github.blog/changelog/2025-09-19-deprecation-of-node-20-on-github-actions-runners/
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L115:
hardware/src/cachepool_tile.sv#L115
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1145:
hardware/src/cachepool_tile.sv#L1145
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1146:
hardware/src/cachepool_tile.sv#L1146
Line length exceeds max: 100; is: 107 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1180:
hardware/src/cachepool_tile.sv#L1180
Line length exceeds max: 100; is: 116 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1188:
hardware/src/cachepool_tile.sv#L1188
Line length exceeds max: 100; is: 121 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1292:
hardware/src/cachepool_tile.sv#L1292
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1293:
hardware/src/cachepool_tile.sv#L1293
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1712:
hardware/src/cachepool_tile.sv#L1712
Line length exceeds max: 100; is: 112 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1813:
hardware/src/cachepool_tile.sv#L1813
Line length exceeds max: 100; is: 113 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1819:
hardware/src/cachepool_tile.sv#L1819
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1828:
hardware/src/cachepool_tile.sv#L1828
Line length exceeds max: 100; is: 118 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1846:
hardware/src/cachepool_tile.sv#L1846
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1851:
hardware/src/cachepool_tile.sv#L1851
Line length exceeds max: 100; is: 115 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_tile.sv#L1860:
hardware/src/cachepool_tile.sv#L1860
Line length exceeds max: 100; is: 106 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L509:
hardware/src/cachepool_cc.sv#L509
Do not use $test$plusargs to access plusargs, use $value$plusargs instead. [Style: plusarg-value-assignment] [plusarg-assignment]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L515:
hardware/src/cachepool_cc.sv#L515
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L520:
hardware/src/cachepool_cc.sv#L520
Line length exceeds max: 100; is: 161 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L541:
hardware/src/cachepool_cc.sv#L541
Line length exceeds max: 100; is: 120 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L554:
hardware/src/cachepool_cc.sv#L554
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L577:
hardware/src/cachepool_cc.sv#L577
Line length exceeds max: 100; is: 140 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L581:
hardware/src/cachepool_cc.sv#L581
Line length exceeds max: 100; is: 109 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L582:
hardware/src/cachepool_cc.sv#L582
Line length exceeds max: 100; is: 125 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L1186:
hardware/src/cachepool_cc.sv#L1186
Do not use $test$plusargs to access plusargs, use $value$plusargs instead. [Style: plusarg-value-assignment] [plusarg-assignment]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L1196:
hardware/src/cachepool_cc.sv#L1196
Line length exceeds max: 100; is: 126 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L1200:
hardware/src/cachepool_cc.sv#L1200
Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L1201:
hardware/src/cachepool_cc.sv#L1201
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L1203:
hardware/src/cachepool_cc.sv#L1203
Line length exceeds max: 100; is: 104 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L1228:
hardware/src/cachepool_cc.sv#L1228
Line length exceeds max: 100; is: 114 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cc.sv#L1252:
hardware/src/cachepool_cc.sv#L1252
Line length exceeds max: 100; is: 131 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L440:
hardware/src/tcdm_cache_interco.sv#L440
Do not use $test$plusargs to access plusargs, use $value$plusargs instead. [Style: plusarg-value-assignment] [plusarg-assignment]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L450:
hardware/src/tcdm_cache_interco.sv#L450
Line length exceeds max: 100; is: 111 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L454:
hardware/src/tcdm_cache_interco.sv#L454
Line length exceeds max: 100; is: 169 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L477:
hardware/src/tcdm_cache_interco.sv#L477
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L482:
hardware/src/tcdm_cache_interco.sv#L482
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L482:
hardware/src/tcdm_cache_interco.sv#L482
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L493:
hardware/src/tcdm_cache_interco.sv#L493
Line length exceeds max: 100; is: 135 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L494:
hardware/src/tcdm_cache_interco.sv#L494
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L497:
hardware/src/tcdm_cache_interco.sv#L497
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L497:
hardware/src/tcdm_cache_interco.sv#L497
Line length exceeds max: 100; is: 105 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L505:
hardware/src/tcdm_cache_interco.sv#L505
Use blocking assignments, at most, for locals inside 'always_ff' sequential blocks. [Style: sequential-logic] [always-ff-non-blocking]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L505:
hardware/src/tcdm_cache_interco.sv#L505
Line length exceeds max: 100; is: 110 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/tcdm_cache_interco.sv#L508:
hardware/src/tcdm_cache_interco.sv#L508
Line length exceeds max: 100; is: 108 [Style: line-length] [line-length]
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[verible-verilog-lint] hardware/src/cachepool_cluster.sv#L112:
hardware/src/cachepool_cluster.sv#L112
Line length exceeds max: 100; is: 101 [Style: line-length] [line-length]
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gitlab-ci
Node.js 20 actions are deprecated. The following actions are running on Node.js 20 and may not work as expected: actions/checkout@v3, actions/setup-python@v4. Actions will be forced to run with Node.js 24 by default starting June 2nd, 2026. Node.js 20 will be removed from the runner on September 16th, 2026. Please check if updated versions of these actions are available that support Node.js 24. To opt into Node.js 24 now, set the FORCE_JAVASCRIPT_ACTIONS_TO_NODE24=true environment variable on the runner or in your workflow file. Once Node.js 24 becomes the default, you can temporarily opt out by setting ACTIONS_ALLOW_USE_UNSECURE_NODE_VERSION=true. For more information see: https://github.blog/changelog/2025-09-19-deprecation-of-node-20-on-github-actions-runners/
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verible-linter
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2.26 KB |
sha256:ca2ffd56bd3e44fd591015db92ce3392861b8f03c00f35e18f9d5153f4da0a81
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