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1 parent d084c03 commit c946015Copy full SHA for c946015
1 file changed
hardware/src/cachepool_tile.sv
@@ -1108,7 +1108,7 @@ module cachepool_tile
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.CacheLineWidth (L1LineWidth ),
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.SetAssociativity (L1AssoPerCtrl ),
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.BankFactor (L1BankFactor ),
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- .LogDebug (0 ),
+ // .LogDebug (0 ),
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.RefillDataWidth (RefillDataWidth ),
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// Type
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.core_meta_t (tcdm_user_t ),
@@ -1481,7 +1481,7 @@ module cachepool_tile
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.FILL_DW ( AxiDataWidth ),
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.EARLY_LATCH ( 0 ),
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.L0_EARLY_TAG_WIDTH ( snitch_pkg::PAGE_SHIFT - $clog2(ICacheLineWidth/8) ),
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- .ISO_CROSSING ( 1'b0 ),
+ .ISO_CROSSING ( 1'b1 ),
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.axi_req_t ( axi_mst_tile_wide_req_t ),
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.axi_rsp_t ( axi_mst_tile_wide_resp_t ),
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.sram_cfg_data_t ( impl_in_t ),
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