From b7e7497da7d89d0f77278ae6af3e62515b2a7ee1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kaan=20Ar=C4=B1?= Date: Tue, 7 Jan 2025 13:53:02 +0100 Subject: [PATCH 1/3] Fix clk_rst_gen parameter discrepancy --- test/tb_apb_regs.sv | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/test/tb_apb_regs.sv b/test/tb_apb_regs.sv index f356f12..e33ffa9 100644 --- a/test/tb_apb_regs.sv +++ b/test/tb_apb_regs.sv @@ -63,8 +63,8 @@ module tb_apb_regs; // Clock generator //----------------------------------- clk_rst_gen #( - .CLK_PERIOD ( CyclTime ), - .RST_CLK_CYCLES( 5 ) + .ClkPeriod ( CyclTime ), + .RstClkCycles( 5 ) ) i_clk_gen ( .clk_o (clk), .rst_no(rst_n) From df5d344aec3f1a5e0ebcaaf8bbf73db608f4cc31 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kaan=20Ar=C4=B1?= Date: Tue, 7 Jan 2025 13:54:00 +0100 Subject: [PATCH 2/3] Fix register golden model for non read only registers --- test/tb_apb_regs.sv | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/test/tb_apb_regs.sv b/test/tb_apb_regs.sv index e33ffa9..83d09af 100644 --- a/test/tb_apb_regs.sv +++ b/test/tb_apb_regs.sv @@ -86,7 +86,7 @@ module tb_apb_regs; automatic reg_data_t init_val; // initialize reset values and golden model for (int unsigned i = 0; i < NoApbRegs; i++) begin - init_val = reg_data_t'($urandom()); + init_val = ReadOnly[i] ? reg_data_t'($urandom()) : 32'd0; reg_init[i] = init_val; reg_compare[i] = init_val; end From 319ee3d571439e2a6b4ae75fdfed9e09687826d1 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Kaan=20Ar=C4=B1?= Date: Tue, 7 Jan 2025 13:57:11 +0100 Subject: [PATCH 3/3] Fix for apb write request with strobe --- src/apb_regs.sv | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-) diff --git a/src/apb_regs.sv b/src/apb_regs.sv index 00a7785..3a3987f 100644 --- a/src/apb_regs.sv +++ b/src/apb_regs.sv @@ -86,10 +86,6 @@ module apb_regs #( apb_addr_t end_addr; } rule_t; - logic has_reset_d, has_reset_q; - `FFARN(has_reset_q, has_reset_q, 1'b0, pclk_i, preset_ni) - assign has_reset_d = 1'b1; - // signal declarations rule_t [NoApbRegs-1:0] addr_map; idx_t reg_idx; @@ -109,7 +105,7 @@ module apb_regs #( always_comb begin // default assignments - reg_d = has_reset_q ? reg_q : reg_init_i; + reg_d = reg_q; reg_update = '0; resp_o = '{ pready: req_i.psel & req_i.penable,