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collucacolluca
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Implement unicast XBAR IPs from multicast IPs
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11 files changed

+583
-2204
lines changed

11 files changed

+583
-2204
lines changed

‎Bender.yml‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,7 @@ package:
55
- "Thomas Benz <[email protected]>" # current maintainer
66
- "Michael Rogenmoser <[email protected]>" # current maintainer
77
- "Matheus Cavalcante <[email protected]>"
8+
- "Luca Colagrande <[email protected]>"
89
- "Tim Fischer <[email protected]>"
910
- "Noah Huetter <[email protected]>"
1011
- "Cyril Koenig <[email protected]>"
@@ -33,6 +34,7 @@ sources:
3334
# Level 0
3435
- src/axi_pkg.sv
3536
# Level 1
37+
- src/axi_demux_id_counters.sv
3638
- src/axi_intf.sv
3739
# Level 2
3840
- src/axi_atop_filter.sv
@@ -121,7 +123,6 @@ sources:
121123
files:
122124
# Level 0
123125
- test/tb_axi_dw_pkg.sv
124-
- test/tb_axi_mcast_xbar_pkg.sv
125126
- test/tb_axi_xbar_pkg.sv
126127
# Level 1
127128
- test/tb_axi_addr_test.sv

‎src/axi_demux.sv‎

Lines changed: 60 additions & 134 deletions
Original file line numberDiff line numberDiff line change
@@ -42,6 +42,7 @@
4242
module axi_demux #(
4343
parameter int unsigned AxiIdWidth = 32'd0,
4444
parameter bit AtopSupport = 1'b1,
45+
parameter type aw_addr_t = logic,
4546
parameter type aw_chan_t = logic,
4647
parameter type w_chan_t = logic,
4748
parameter type b_chan_t = logic,
@@ -58,154 +59,67 @@ module axi_demux #(
5859
parameter bit SpillB = 1'b0,
5960
parameter bit SpillAr = 1'b1,
6061
parameter bit SpillR = 1'b0,
62+
parameter bit [NoMstPorts-1:0] Connectivity = '1,
63+
parameter type rule_t = logic,
64+
parameter int unsigned NoAddrRules = 32'd0,
6165
// Dependent parameters, DO NOT OVERRIDE!
6266
parameter int unsigned SelectWidth = (NoMstPorts > 32'd1) ? $clog2(NoMstPorts) : 32'd1,
6367
parameter type select_t = logic [SelectWidth-1:0]
6468
) (
6569
input logic clk_i,
6670
input logic rst_ni,
6771
input logic test_i,
72+
// Addressing rules
73+
input rule_t [NoAddrRules-1:0] addr_map_i,
74+
input logic en_default_mst_port_i,
75+
input rule_t default_mst_port_i,
6876
// Slave Port
6977
input axi_req_t slv_req_i,
70-
input select_t slv_aw_select_i,
7178
input select_t slv_ar_select_i,
7279
output axi_resp_t slv_resp_o,
7380
// Master Ports
7481
output axi_req_t [NoMstPorts-1:0] mst_reqs_o,
7582
input axi_resp_t [NoMstPorts-1:0] mst_resps_i
7683
);
7784

78-
axi_req_t slv_req_cut;
79-
axi_resp_t slv_resp_cut;
80-
81-
logic slv_aw_ready_chan, slv_aw_ready_sel;
82-
logic slv_aw_valid_chan, slv_aw_valid_sel;
83-
84-
logic slv_ar_ready_chan, slv_ar_ready_sel;
85-
logic slv_ar_valid_chan, slv_ar_valid_sel;
86-
87-
select_t slv_aw_select, slv_ar_select;
88-
89-
spill_register #(
90-
.T ( aw_chan_t ),
91-
.Bypass ( ~SpillAw )
92-
) i_aw_spill_reg (
93-
.clk_i,
94-
.rst_ni,
95-
.valid_i ( slv_req_i.aw_valid ),
96-
.ready_o ( slv_aw_ready_chan ),
97-
.data_i ( slv_req_i.aw ),
98-
.valid_o ( slv_aw_valid_chan ),
99-
.ready_i ( slv_resp_cut.aw_ready ),
100-
.data_o ( slv_req_cut.aw )
101-
);
102-
spill_register #(
103-
.T ( select_t ),
104-
.Bypass ( ~SpillAw )
105-
) i_aw_select_spill_reg (
106-
.clk_i,
107-
.rst_ni,
108-
.valid_i ( slv_req_i.aw_valid ),
109-
.ready_o ( slv_aw_ready_sel ),
110-
.data_i ( slv_aw_select_i ),
111-
.valid_o ( slv_aw_valid_sel ),
112-
.ready_i ( slv_resp_cut.aw_ready ),
113-
.data_o ( slv_aw_select )
114-
);
115-
116-
assign slv_resp_o.aw_ready = slv_aw_ready_chan & slv_aw_ready_sel;
117-
assign slv_req_cut.aw_valid = slv_aw_valid_chan & slv_aw_valid_sel;
118-
119-
spill_register #(
120-
.T ( w_chan_t ),
121-
.Bypass ( ~SpillW )
122-
) i_w_spill_reg (
123-
.clk_i,
124-
.rst_ni,
125-
.valid_i ( slv_req_i.w_valid ),
126-
.ready_o ( slv_resp_o.w_ready ),
127-
.data_i ( slv_req_i.w ),
128-
.valid_o ( slv_req_cut.w_valid ),
129-
.ready_i ( slv_resp_cut.w_ready ),
130-
.data_o ( slv_req_cut.w )
131-
);
132-
spill_register #(
133-
.T ( ar_chan_t ),
134-
.Bypass ( ~SpillAr )
135-
) i_ar_spill_reg (
136-
.clk_i,
137-
.rst_ni,
138-
.valid_i ( slv_req_i.ar_valid ),
139-
.ready_o ( slv_ar_ready_chan ),
140-
.data_i ( slv_req_i.ar ),
141-
.valid_o ( slv_ar_valid_chan ),
142-
.ready_i ( slv_resp_cut.ar_ready ),
143-
.data_o ( slv_req_cut.ar )
144-
);
145-
spill_register #(
146-
.T ( select_t ),
147-
.Bypass ( ~SpillAr )
148-
) i_ar_sel_spill_reg (
149-
.clk_i,
150-
.rst_ni,
151-
.valid_i ( slv_req_i.ar_valid ),
152-
.ready_o ( slv_ar_ready_sel ),
153-
.data_i ( slv_ar_select_i ),
154-
.valid_o ( slv_ar_valid_sel ),
155-
.ready_i ( slv_resp_cut.ar_ready ),
156-
.data_o ( slv_ar_select )
157-
);
158-
159-
assign slv_resp_o.ar_ready = slv_ar_ready_chan & slv_ar_ready_sel;
160-
assign slv_req_cut.ar_valid = slv_ar_valid_chan & slv_ar_valid_sel;
161-
162-
spill_register #(
163-
.T ( b_chan_t ),
164-
.Bypass ( ~SpillB )
165-
) i_b_spill_reg (
166-
.clk_i,
167-
.rst_ni,
168-
.valid_i ( slv_resp_cut.b_valid ),
169-
.ready_o ( slv_req_cut.b_ready ),
170-
.data_i ( slv_resp_cut.b ),
171-
.valid_o ( slv_resp_o.b_valid ),
172-
.ready_i ( slv_req_i.b_ready ),
173-
.data_o ( slv_resp_o.b )
174-
);
175-
spill_register #(
176-
.T ( r_chan_t ),
177-
.Bypass ( ~SpillR )
178-
) i_r_spill_reg (
179-
.clk_i,
180-
.rst_ni,
181-
.valid_i ( slv_resp_cut.r_valid ),
182-
.ready_o ( slv_req_cut.r_ready ),
183-
.data_i ( slv_resp_cut.r ),
184-
.valid_o ( slv_resp_o.r_valid ),
185-
.ready_i ( slv_req_i.r_ready ),
186-
.data_o ( slv_resp_o.r )
187-
);
188-
189-
axi_demux_simple #(
190-
.AxiIdWidth ( AxiIdWidth ),
191-
.AtopSupport( AtopSupport ),
192-
.axi_req_t ( axi_req_t ),
193-
.axi_resp_t ( axi_resp_t ),
194-
.NoMstPorts ( NoMstPorts ),
195-
.MaxTrans ( MaxTrans ),
196-
.AxiLookBits( AxiLookBits ),
197-
.UniqueIds ( UniqueIds )
198-
) i_demux_simple (
199-
.clk_i,
200-
.rst_ni,
201-
.test_i,
202-
203-
.slv_req_i ( slv_req_cut ),
204-
.slv_aw_select_i ( slv_aw_select ),
205-
.slv_ar_select_i ( slv_ar_select ),
206-
.slv_resp_o ( slv_resp_cut ),
207-
.mst_reqs_o ( mst_reqs_o ),
208-
.mst_resps_i ( mst_resps_i )
85+
axi_mcast_demux #(
86+
.AxiIdWidth (AxiIdWidth),
87+
.AtopSupport (AtopSupport),
88+
.aw_addr_t (aw_addr_t),
89+
.aw_chan_t (aw_chan_t),
90+
.w_chan_t (w_chan_t),
91+
.b_chan_t (b_chan_t),
92+
.ar_chan_t (ar_chan_t),
93+
.r_chan_t (r_chan_t),
94+
.axi_req_t (axi_req_t),
95+
.axi_resp_t (axi_resp_t),
96+
.NoMstPorts (NoMstPorts),
97+
.MaxTrans (MaxTrans),
98+
.AxiLookBits (AxiLookBits),
99+
.UniqueIds (UniqueIds),
100+
.SpillAw (SpillAw),
101+
.SpillW (SpillW),
102+
.SpillB (SpillB),
103+
.SpillAr (SpillAr),
104+
.SpillR (SpillR),
105+
.Connectivity (Connectivity),
106+
.rule_t (rule_t),
107+
.NoAddrRules (NoAddrRules),
108+
.NoMulticastRules (0),
109+
.NoMulticastPorts (0),
110+
.MaxMcastTrans (1)
111+
) i_mcast_demux (
112+
.clk_i (clk_i),
113+
.rst_ni (rst_ni),
114+
.test_i (test_i),
115+
.addr_map_i (addr_map_i),
116+
.en_default_mst_port_i(en_default_mst_port_i),
117+
.default_mst_port_i (default_mst_port_i),
118+
.slv_req_i (slv_req_i),
119+
.slv_ar_select_i (slv_ar_select_i),
120+
.slv_resp_o (slv_resp_o),
121+
.mst_reqs_o (mst_reqs_o),
122+
.mst_resps_i (mst_resps_i)
209123
);
210124

211125
endmodule
@@ -228,14 +142,19 @@ module axi_demux_intf #(
228142
parameter bit SPILL_B = 1'b0,
229143
parameter bit SPILL_AR = 1'b1,
230144
parameter bit SPILL_R = 1'b0,
145+
parameter bit [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] CONNECTIVITY = '1,
146+
parameter type rule_t = axi_pkg::xbar_rule_64_t,
147+
parameter int unsigned NO_ADDR_RULES = '1,
231148
// Dependent parameters, DO NOT OVERRIDE!
232149
parameter int unsigned SELECT_WIDTH = (NO_MST_PORTS > 32'd1) ? $clog2(NO_MST_PORTS) : 32'd1,
233150
parameter type select_t = logic [SELECT_WIDTH-1:0] // MST port select type
234151
) (
235152
input logic clk_i, // Clock
236153
input logic rst_ni, // Asynchronous reset active low
237154
input logic test_i, // Testmode enable
238-
input select_t slv_aw_select_i, // has to be stable, when aw_valid
155+
input rule_t [NO_ADDR_RULES-1:0] addr_map_i,
156+
input logic en_default_mst_port_i,
157+
input rule_t default_mst_port_i,
239158
input select_t slv_ar_select_i, // has to be stable, when ar_valid
240159
AXI_BUS.Slave slv, // slave port
241160
AXI_BUS.Master mst [NO_MST_PORTS-1:0] // master ports
@@ -270,6 +189,7 @@ module axi_demux_intf #(
270189
axi_demux #(
271190
.AxiIdWidth ( AXI_ID_WIDTH ), // ID Width
272191
.AtopSupport ( ATOP_SUPPORT ),
192+
.aw_addr_t ( addr_t ),
273193
.aw_chan_t ( aw_chan_t ), // AW Channel Type
274194
.w_chan_t ( w_chan_t ), // W Channel Type
275195
.b_chan_t ( b_chan_t ), // B Channel Type
@@ -285,11 +205,17 @@ module axi_demux_intf #(
285205
.SpillW ( SPILL_W ),
286206
.SpillB ( SPILL_B ),
287207
.SpillAr ( SPILL_AR ),
288-
.SpillR ( SPILL_R )
208+
.SpillR ( SPILL_R ),
209+
.Connectivity ( CONNECTIVITY ),
210+
.rule_t ( rule_t ),
211+
.NoAddrRules ( NO_ADDR_RULES )
289212
) i_axi_demux (
290213
.clk_i, // Clock
291214
.rst_ni, // Asynchronous reset active low
292215
.test_i, // Testmode enable
216+
.addr_map_i (addr_map_i),
217+
.en_default_mst_port_i(en_default_mst_port_i),
218+
.default_mst_port_i (default_mst_port_i),
293219
// slave port
294220
.slv_req_i ( slv_req ),
295221
.slv_aw_select_i ( slv_aw_select_i ),

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