Minor cleanup

Author: colluca

.ci/Memora.yml

@@ -345,6 +345,6 @@ artifacts:
       - src/axi_mcast_mux.sv
       - src/axi_mcast_xbar.sv
       - test/tb_axi_mcast_xbar.sv
-      - test/tb_axi_mcast_xbar_pkg.sv
+      - test/tb_axi_xbar_pkg.sv
     outputs:
       - build/axi_mcast_xbar-%.tested

Bender.yml

@@ -108,10 +108,6 @@ sources:
     files:
       - test/axi_synth_bench.sv
 
-  - target: gf12
-    files:
-      - test/axi_synth_bench.sv
-
   - target: simulation
     files:
       - src/axi_chan_compare.sv

src/axi_mcast_xbar_unmuxed.sv

@@ -81,6 +81,8 @@ import cf_math_pkg::idx_width;
   input  rule_t [Cfg.NoSlvPorts-1:0]                     default_mst_port_i
 );
 
+  localparam bit EnableMulticast = (Cfg.NoMulticastPorts > 0) || (Cfg.NoMulticastRules > 0);
+
   // signals from the axi_demuxes
   req_t  [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] slv_reqs;
   resp_t [Cfg.NoSlvPorts-1:0][Cfg.NoMstPorts-1:0] slv_resps;
@@ -225,7 +227,7 @@ import cf_math_pkg::idx_width;
       $fatal(1, $sformatf("Slv_req and aw_addr width not equal."));
     addr_mst_req_ports: assert ($bits(mst_ports_req_o[0][0].aw.addr) == Cfg.AxiAddrWidth) else
       $fatal(1, $sformatf("Mst_req and aw_addr width not equal."));
-    no_cuts_if_mcast: assert (!Cfg.EnableMulticast || (Cfg.PipelineStages == 0)) else
+    no_cuts_if_mcast: assert (!EnableMulticast || (Cfg.PipelineStages == 0)) else
       $fatal(1, $sformatf("Multicast XBAR currently does not support pipeline stages."));
   end
   `endif

src/axi_pkg.sv

@@ -515,12 +515,10 @@ package axi_pkg;
     int unsigned   AxiAddrWidth;
     /// AXI4+ATOP data field width.
     int unsigned   AxiDataWidth;
-    /// The number of address rules defined for routing of the AR transactions.
+    /// The number of address rules defined for routing of the transactions.
     /// Each master port can have multiple rules, should have however at least one.
     /// If a transaction can not be routed the xbar will answer with an `axi_pkg::RESP_DECERR`.
     int unsigned   NoAddrRules;
-    /// When asserted, the XBAR is configured to support multicast.
-    bit            EnableMulticast;
     /// The number of address rules to be considered for multicasting,
     /// assumed to be at the start of `addr_map_i`.
     int unsigned   NoMulticastRules;
@@ -536,25 +534,13 @@ package axi_pkg;
     logic [63:0] end_addr;
   } xbar_rule_64_t;
 
-  /// Commonly used rule types for `axi_xbar` (64-bit addresses).
-  typedef struct packed {
-    logic [63:0] addr;
-    logic [63:0] mask;
-  } xbar_mask_rule_64_t;
-
   /// Commonly used rule types for `axi_xbar` (32-bit addresses).
   typedef struct packed {
     int unsigned idx;
     logic [31:0] start_addr;
     logic [31:0] end_addr;
   } xbar_rule_32_t;
 
-  /// Commonly used rule types for `axi_xbar` (32-bit addresses).
-  typedef struct packed {
-    logic [31:0] addr;
-    logic [31:0] mask;
-  } xbar_mask_rule_32_t;
-
   // Return either the argument minus 1 or 0 if 0; useful for IO vector width declaration
   function automatic integer unsigned iomsb (input integer unsigned width);
       return (width != 32'd0) ? unsigned'(width-1) : 32'd0;

test/tb_axi_mcast_xbar.sv

@@ -79,7 +79,6 @@ module tb_axi_mcast_xbar #(
     AxiAddrWidth:       TbAxiAddrWidth,
     AxiDataWidth:       TbAxiDataWidth,
     NoAddrRules:        TbNumMcastSlaves * 2 + 1,
-    EnableMulticast:    1,
     NoMulticastRules:   TbNumMcastSlaves * 2,
     NoMulticastPorts:   TbNumMcastSlaves
   };

test/tb_axi_xbar.sv

@@ -77,7 +77,6 @@ module tb_axi_xbar #(
     AxiAddrWidth:       TbAxiAddrWidth,
     AxiDataWidth:       TbAxiDataWidth,
     NoAddrRules:        TbNumSlaves,
-    EnableMulticast:    1'b0,
     NoMulticastRules:   0,
     NoMulticastPorts:   0
   };