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CyrilKoeCyrilKoe
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fpga: Adding pads in vanilla
1 parent a3b96bd commit 44fb3e4

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+146
-12
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3 files changed

+146
-12
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‎target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc‎

Lines changed: 4 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,7 +5,11 @@
55
# Cyril Koenig <[email protected]>
66

77
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O}]
8+
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]
89

10+
############
11+
# Hyperbus #
12+
############
913

1014
#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
1115
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71

‎target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc‎

Lines changed: 42 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -5,6 +5,48 @@
55
# Cyril Koenig <[email protected]>
66

77
set_property CLOCK_DEDICATED_ROUTE FALSE [get_ports pad_hyper_rwds[0]]
8+
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]
9+
10+
11+
set period_hyperbus 100
12+
13+
create_clock -period [expr $period_hyperbus] -name hyper_rwds_clk [get_ports pad_hyper_rwds[0]]
14+
15+
create_generated_clock -name hyper_clk_phy -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -divide_by 2 [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk0_o_reg/Q]
16+
create_generated_clock -name hyper_clk_phy_90 -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -edges {2 4 6} [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk90_o_reg/Q]
17+
18+
set clk_rwds_delayed_pin [get_pins -of_objects [get_cells i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_delay_rx_rwds_90/i_delay] -filter {DIRECTION =~ OUT}]
19+
set clk_rwds_delayed_inv_pin [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_rx_rwds_cdc_fifo/CLK]
20+
21+
set clk_rx_shift [expr $period_hyperbus/10]
22+
set rwds_input_delay [expr $period_hyperbus/4]
23+
create_generated_clock -name hyper_clk_rwds_delayed0 -edges {1 2 3} -edge_shift "$clk_rx_shift $clk_rx_shift $clk_rx_shift" \
24+
-source [get_ports pad_hyper_rwds[0]] $clk_rwds_delayed_pin
25+
set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_delayed0
26+
27+
create_generated_clock -name hyper_clk_rwds_sample0 -invert -divide_by 1 -source $clk_rwds_delayed_pin $clk_rwds_delayed_inv_pin
28+
set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_sample0
29+
30+
set_false_path -from [get_ports pad_hyper_rwds[0]] -to [get_ports pad_hyper_rwds[0]]
31+
# these are for clock domain crossing
32+
set_false_path -from [get_clocks hyper_rwds_clk] -to [get_clocks hyper_clk_phy]
33+
set_false_path -from [get_clocks hyper_clk_phy] -to [get_clocks hyper_rwds_clk]
34+
set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_clk_phy]
35+
set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_rwds_clk]
36+
37+
# Todo correct build correct input / output constraints
38+
39+
set hyper_output_ports [get_ports pad_hyper_dq*]
40+
set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max
41+
set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -add_delay
42+
set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max -clock_fall -add_delay
43+
set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -clock_fall -add_delay
44+
45+
set hyper_input_ports [get_ports -regexp pad_hyper_dq.*]
46+
set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports]
47+
set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay
48+
set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall
49+
set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall
850

951
#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
1052
#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71

‎target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv‎

Lines changed: 100 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -121,7 +121,7 @@ module carfield_top_xilinx
121121
`elsif USE_RESETN
122122
logic cpu_reset;
123123
assign cpu_reset = ~cpu_resetn;
124-
`endif
124+
`endif // USE_RESET
125125
logic sys_rst;
126126

127127
wire clk_100, clk_50, clk_20;
@@ -140,17 +140,17 @@ module carfield_top_xilinx
140140
assign testmode_i = '0;
141141
assign boot_mode_i = 2'b00;
142142
assign boot_mode_safety_i = 2'b00;
143-
`endif
143+
`endif // USE_SWITCHES
144144

145145
// Give VDD and GND to JTAG
146146
`ifdef USE_JTAG_VDDGND
147147
assign jtag_vdd_o = '1;
148148
assign jtag_gnd_o = '0;
149-
`endif
149+
`endif // USE_JTAG_VDDGND
150150
`ifndef USE_JTAG_TRSTN
151151
logic jtag_trst_ni;
152152
assign jtag_trst_ni = '1;
153-
`endif
153+
`endif // USE_JTAG_TRSTN
154154
`ifndef USE_JTAG
155155
logic jtag_tck_i;
156156
logic jtag_tms_i;
@@ -159,7 +159,7 @@ module carfield_top_xilinx
159159
assign jtag_tck_i = '0;
160160
assign jtag_tms_i = '0;
161161
assign jtag_tdi_i = '0;
162-
`endif
162+
`endif // USE_JTAG
163163

164164
//////////////////
165165
// Clock Wizard //
@@ -227,11 +227,11 @@ module carfield_top_xilinx
227227
assign sys_rst = cpu_reset | vio_reset;
228228
assign boot_mode = boot_mode_i | vio_boot_mode;
229229
assign boot_mode_safety = boot_mode_safety_i | vio_boot_mode_safety;
230-
`else
230+
`else // USE_VIO
231231
assign sys_rst = cpu_reset;
232232
assign boot_mode = boot_mode_i;
233233
assign boot_mode_safety = boot_mode_safety_i;
234-
`endif
234+
`endif // USE_VIO
235235

236236
//////////////////
237237
// I2C Adaption //
@@ -275,7 +275,7 @@ module carfield_top_xilinx
275275
.I ( i2c_sda_soc_out ),
276276
.T ( ~i2c_sda_en )
277277
);
278-
`endif
278+
`endif // USE_I2C
279279

280280

281281
//////////////////
@@ -403,7 +403,7 @@ module carfield_top_xilinx
403403
.pwm_setting_i ( fan_sw ),
404404
.fan_pwm_o ( fan_pwm )
405405
);
406-
`endif
406+
`endif // USE_FAN
407407

408408
//////////////////
409409
// Carfield Cfg //
@@ -417,6 +417,7 @@ module carfield_top_xilinx
417417
///////////////////
418418

419419
`ifdef GEN_NO_HYPERBUS // bender-xilinx.mk
420+
420421
localparam axi_in_t AxiIn = gen_axi_in(Cfg);
421422
localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth+$clog2(AxiIn.num_in)+Cfg.LlcNotBypass;
422423
localparam int unsigned LlcArWidth = (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,LlcIdWidth,Cfg.AxiUserWidth);
@@ -475,6 +476,82 @@ module carfield_top_xilinx
475476
.dst_req_o ( llc_req ),
476477
.dst_resp_i ( llc_rsp )
477478
);
479+
`endif // GEN_NO_HYPERBUS
480+
481+
///////////////////
482+
// Hyperram PADS //
483+
///////////////////
484+
485+
`ifndef GEN_NO_HYPERBUS
486+
487+
logic [`HypNumPhys-1:0][`HypNumChips-1:0] hyper_cs_no;
488+
logic [`HypNumPhys-1:0] hyper_ck_o;
489+
logic [`HypNumPhys-1:0] hyper_ck_no;
490+
logic [`HypNumPhys-1:0] hyper_rwds_o;
491+
logic [`HypNumPhys-1:0] hyper_rwds_i;
492+
logic [`HypNumPhys-1:0] hyper_rwds_oe_o;
493+
logic [`HypNumPhys-1:0][7:0] hyper_dq_i;
494+
logic [`HypNumPhys-1:0][7:0] hyper_dq_o;
495+
logic [`HypNumPhys-1:0] hyper_dq_oe_o;
496+
logic [`HypNumPhys-1:0] hyper_reset_no;
497+
498+
for (genvar i = 0 ; i < `HypNumPhys; i++) begin : gen_hyper_phy
499+
500+
for (genvar j = 0; j < `HypNumChips; j++) begin : gen_hyper_cs
501+
pad_functional_pd padinst_hyper_csno (
502+
.OEN ( 1'b0 ),
503+
.I ( hyper_cs_no[i][j] ),
504+
.O ( ),
505+
.PEN ( ),
506+
.PAD ( pad_hyper_csn[i][j] )
507+
);
508+
end // gen_hyper_cs
509+
510+
pad_functional_pd padinst_hyper_ck (
511+
.OEN ( 1'b0 ),
512+
.I ( hyper_ck_o[i] ),
513+
.O ( ),
514+
.PEN ( ),
515+
.PAD ( pad_hyper_ck[i] )
516+
);
517+
pad_functional_pd padinst_hyper_ckno (
518+
.OEN ( 1'b0 ),
519+
.I ( hyper_ck_no[i] ),
520+
.O ( ),
521+
.PEN ( ),
522+
.PAD ( pad_hyper_ckn[i] )
523+
);
524+
pad_functional_pd padinst_hyper_rwds0 (
525+
.OEN ( ~hyper_rwds_oe_o[i] ),
526+
.I ( hyper_rwds_o[i] ),
527+
.O ( hyper_rwds_i[i] ),
528+
.PEN ( ),
529+
.PAD ( pad_hyper_rwds[i] )
530+
);
531+
532+
for (genvar j = 0; j < 8; j++) begin : gen_hyper_dq
533+
pad_functional_pd padinst_hyper_dqio0 (
534+
.OEN ( ~hyper_dq_oe_o[i] ),
535+
.I ( hyper_dq_o[i][j] ),
536+
.O ( hyper_dq_i[i][j] ),
537+
.PEN ( ),
538+
.PAD ( pad_hyper_dq[i][j] )
539+
);
540+
end // gen_hyper_dq
541+
542+
end // gen_hyper_phy
543+
544+
`ila(ila_hyper_cs_n , hyper_cs_no )
545+
`ila(ila_hyper_ck , hyper_ck_o )
546+
`ila(ila_hyper_ck_n , hyper_ck_no )
547+
`ila(ila_hyper_rwds_o , hyper_rwds_o )
548+
`ila(ila_hyper_rwds_i , hyper_rwds_i )
549+
`ila(ila_hyper_rwds_oe_o , hyper_rwds_oe_o )
550+
`ila(ila_hyper_dq_i , hyper_dq_i )
551+
`ila(ila_hyper_dq_o , hyper_dq_o )
552+
`ila(ila_hyper_dq_oe , hyper_dq_oe_o )
553+
`ila(ila_hyper_reset_n , hyper_reset_no )
554+
478555
`endif // GEN_NO_HYPERBUS
479556

480557
//////////////////
@@ -494,7 +571,7 @@ module carfield_top_xilinx
494571
.LlcBWidth ( LlcBWidth ),
495572
.LlcRWidth ( LlcRWidth ),
496573
.LlcWWidth ( LlcWWidth ),
497-
`endif
574+
`endif // GEN_NO_HYPERBUS
498575
.HypNumPhys (`HypNumPhys),
499576
.HypNumChips (`HypNumChips)
500577
) i_carfield (
@@ -576,7 +653,18 @@ module carfield_top_xilinx
576653
.llc_w_data,
577654
.llc_w_wptr,
578655
.llc_w_rptr,
579-
`endif
656+
`else // GEN_NO_HYPERBUS
657+
.hyper_cs_no,
658+
.hyper_ck_o,
659+
.hyper_ck_no,
660+
.hyper_rwds_o,
661+
.hyper_rwds_i,
662+
.hyper_rwds_oe_o,
663+
.hyper_dq_i,
664+
.hyper_dq_o,
665+
.hyper_dq_oe_o,
666+
.hyper_reset_no,
667+
`endif // GEN_NO_HYPERBUS
580668
// Serial link interface
581669
.slink_rcv_clk_i (),
582670
.slink_rcv_clk_o (),
@@ -610,6 +698,6 @@ module carfield_top_xilinx
610698
// Phy
611699
.*
612700
);
613-
`endif
701+
`endif // USE_DDR
614702

615703
endmodule

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