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CyrilKoeCyrilKoe
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fpga: Testing hyperram in block design
fpga: Testing hyperram in vanilla fpga: Adding pads in vanilla
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‎target/xilinx/flavor_bd/constraints/vcu128_hyperbus.xdc‎

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# Copyright 2020 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#
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# Cyril Koenig <[email protected]>
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets {design_1_i/carfield_xilinx_ip_0/inst/i_carfield_xilinx/gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O}]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]
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############
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# Hyperbus #
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############
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#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
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#set_property PACKAGE_PIN A20 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA20_N) Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA20_N) Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71
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#set_property PACKAGE_PIN A21 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71
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#set_property PACKAGE_PIN D20 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71
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set_property PACKAGE_PIN A24 [get_ports {pad_hyper_csn[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_csn[1]}]
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set_property PACKAGE_PIN A25 [get_ports {pad_hyper_csn[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_csn[0]}]
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set_property PACKAGE_PIN C23 [get_ports pad_hyper_rwds]
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set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_rwds]
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set_property PACKAGE_PIN D26 [get_ports {pad_hyper_dq[2]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[2]}]
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set_property PACKAGE_PIN A23 [get_ports {pad_hyper_dq[3]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[3]}]
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set_property PACKAGE_PIN B23 [get_ports {pad_hyper_dq[0]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[0]}]
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set_property PACKAGE_PIN E26 [get_ports {pad_hyper_dq[4]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[4]}]
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set_property PACKAGE_PIN D22 [get_ports {pad_hyper_dq[7]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[7]}]
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set_property PACKAGE_PIN E22 [get_ports {pad_hyper_dq[1]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[1]}]
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set_property PACKAGE_PIN F25 [get_ports pad_hyper_ckn]
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set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_ckn]
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set_property PACKAGE_PIN F26 [get_ports pad_hyper_ck]
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set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_ck]
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set_property PACKAGE_PIN G27 [get_ports {pad_hyper_dq[5]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[5]}]
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set_property PACKAGE_PIN H27 [get_ports {pad_hyper_dq[6]}]
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set_property IOSTANDARD LVCMOS18 [get_ports {pad_hyper_dq[6]}]
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#set_property PACKAGE_PIN L23 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72
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#set_property PACKAGE_PIN K23 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72
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#set_property PACKAGE_PIN K24 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72
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‎target/xilinx/flavor_bd/scripts/carfield_bd_hyperbus.tcl‎

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# Copyright 2020 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#
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# Cyril Koenig <[email protected]>
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set pad_hyper_ck [ create_bd_port -dir IO pad_hyper_ck ]
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set pad_hyper_ckn [ create_bd_port -dir IO pad_hyper_ckn ]
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set pad_hyper_csn [ create_bd_port -dir IO -from 1 -to 0 pad_hyper_csn ]
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set pad_hyper_dq [ create_bd_port -dir IO -from 7 -to 0 pad_hyper_dq ]
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set pad_hyper_rwds [ create_bd_port -dir IO pad_hyper_rwds ]
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connect_bd_net [get_bd_ports pad_hyper_csn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_csn]
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connect_bd_net [get_bd_ports pad_hyper_ck] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ck]
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connect_bd_net [get_bd_ports pad_hyper_ckn] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_ckn]
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connect_bd_net [get_bd_ports pad_hyper_rwds] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_rwds]
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connect_bd_net [get_bd_ports pad_hyper_dq] [get_bd_pins carfield_xilinx_ip_0/pad_hyper_dq]

‎target/xilinx/flavor_bd/scripts/run.tcl‎

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@@ -32,6 +32,12 @@ if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} {
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import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc
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}
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# Add the hyperbus pins to block design
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if {![info exists ::env(GEN_NO_HYPERBUS)] || ($::env(GEN_NO_HYPERBUS)==0)} {
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source scripts/carfield_bd_hyperbus.tcl
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import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_hyperbus.xdc
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}
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make_wrapper -files [get_files $project/$project.srcs/sources_1/bd/design_1/design_1.bd] -top
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add_files -norecurse $project/$project.gen/sources_1/bd/design_1/hdl/design_1_wrapper.v
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‎target/xilinx/flavor_vanilla/constraints/vcu128_hyperbus.xdc‎

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# Copyright 2020 ETH Zurich and University of Bologna.
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# Solderpad Hardware License, Version 0.51, see LICENSE for details.
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# SPDX-License-Identifier: SHL-0.51
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#
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# Cyril Koenig <[email protected]>
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_ports pad_hyper_rwds[0]]
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set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets gen_hyper_phy[0].padinst_hyper_rwds0/iobuf_i/O]
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set period_hyperbus 100
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create_clock -period [expr $period_hyperbus] -name hyper_rwds_clk [get_ports pad_hyper_rwds[0]]
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create_generated_clock -name hyper_clk_phy -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -divide_by 2 [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk0_o_reg/Q]
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create_generated_clock -name hyper_clk_phy_90 -source [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/CLK] -edges {2 4 6} [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/clock_generator.ddr_clk/r_clk90_o_reg/Q]
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set clk_rwds_delayed_pin [get_pins -of_objects [get_cells i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_delay_rx_rwds_90/i_delay] -filter {DIRECTION =~ OUT}]
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set clk_rwds_delayed_inv_pin [get_pins i_carfield/i_hyperbus_wrap/i_hyperbus/i_phy/i_phy/i_trx/i_rx_rwds_cdc_fifo/CLK]
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set clk_rx_shift [expr $period_hyperbus/10]
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set rwds_input_delay [expr $period_hyperbus/4]
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create_generated_clock -name hyper_clk_rwds_delayed0 -edges {1 2 3} -edge_shift "$clk_rx_shift $clk_rx_shift $clk_rx_shift" \
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-source [get_ports pad_hyper_rwds[0]] $clk_rwds_delayed_pin
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set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_delayed0
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create_generated_clock -name hyper_clk_rwds_sample0 -invert -divide_by 1 -source $clk_rwds_delayed_pin $clk_rwds_delayed_inv_pin
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set_clock_latency [expr ${rwds_input_delay}] hyper_clk_rwds_sample0
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set_false_path -from [get_ports pad_hyper_rwds[0]] -to [get_ports pad_hyper_rwds[0]]
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# these are for clock domain crossing
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set_false_path -from [get_clocks hyper_rwds_clk] -to [get_clocks hyper_clk_phy]
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set_false_path -from [get_clocks hyper_clk_phy] -to [get_clocks hyper_rwds_clk]
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set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_clk_phy]
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set_false_path -from [get_clocks hyper_clk_phy_90] -to [get_clocks hyper_rwds_clk]
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# Todo correct build correct input / output constraints
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set hyper_output_ports [get_ports pad_hyper_dq*]
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set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max
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set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -add_delay
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set_output_delay [expr $period_hyperbus/2 ] -clock hyper_clk_phy [get_ports $hyper_output_ports] -max -clock_fall -add_delay
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set_output_delay [expr $period_hyperbus/-2] -clock hyper_clk_phy [get_ports $hyper_output_ports] -min -clock_fall -add_delay
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set hyper_input_ports [get_ports -regexp pad_hyper_dq.*]
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set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports]
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set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay
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set_input_delay -max [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall
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set_input_delay -min [expr $period_hyperbus/2] -clock hyper_clk_phy [get_ports $hyper_input_ports] -add_delay -clock_fall
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#set_property PACKAGE_PIN A16 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0]"] ;# (FMCP_HSPC_LA22_N) Bank 71 VCCO - VADJ - IO_L24N_T3U_N11_71
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#set_property PACKAGE_PIN A20 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA20_N) Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[7]"] ;# (FMCP_HSPC_LA20_N) Bank 71 VCCO - VADJ - IO_L22N_T3U_N7_DBC_AD0N_71
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#set_property PACKAGE_PIN A21 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[6]"] ;# (FMCP_HSPC_LA20_P) Bank 71 VCCO - VADJ - IO_L22P_T3U_N6_DBC_AD0P_71
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#set_property PACKAGE_PIN D20 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_reset[0]"] ;# (FMCP_HSPC_LA25_P) Bank 71 VCCO - VADJ - IO_L18P_T2U_N10_AD2P_71
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set_property PACKAGE_PIN A24 [get_ports "pad_hyper_csn[0][1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][1]"] ;# (FMCP_HSPC_LA13_N) Bank 72 VCCO - VADJ - IO_L24N_T3U_N11_72
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set_property PACKAGE_PIN A25 [get_ports "pad_hyper_csn[0][0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[0][0]"] ;# (FMCP_HSPC_LA13_P) Bank 72 VCCO - VADJ - IO_L24P_T3U_N10_72
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set_property PACKAGE_PIN C23 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_rwds[0]"] ;# (FMCP_HSPC_LA14_P) Bank 72 VCCO - VADJ - IO_L19P_T3L_N0_DBC_AD9P_72
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set_property PACKAGE_PIN D26 [get_ports "pad_hyper_dq[0][2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][2] "] ;# (FMCP_HSPC_LA09_N) Bank 72 VCCO - VADJ - IO_L17N_T2U_N9_AD10N_72
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set_property PACKAGE_PIN A23 [get_ports pad_hyper_dq[0][3]] ;# (FMCP_HSPC_LA10_N)
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set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[0][3]] ;# (FMCP_HSPC_LA10_N)
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set_property PACKAGE_PIN B23 [get_ports pad_hyper_dq[0][0]] ;# (FMCP_HSPC_LA10_P)
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set_property IOSTANDARD LVCMOS18 [get_ports pad_hyper_dq[0][0]] ;# (FMCP_HSPC_LA10_P)
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set_property PACKAGE_PIN E26 [get_ports "pad_hyper_dq[0][4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][4]"] ;# (FMCP_HSPC_LA09_P) Bank 72 VCCO - VADJ - IO_L17P_T2U_N8_AD10P_72
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set_property PACKAGE_PIN D22 [get_ports "pad_hyper_dq[0][7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][7]"] ;# (FMCP_HSPC_LA06_N) Bank 72 VCCO - VADJ - IO_L15N_T2L_N5_AD11N_72
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set_property PACKAGE_PIN E22 [get_ports "pad_hyper_dq[0][1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][1]"] ;# (FMCP_HSPC_LA06_P) Bank 72 VCCO - VADJ - IO_L15P_T2L_N4_AD11P_72
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set_property PACKAGE_PIN F25 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ckn[0]"] ;# (FMCP_HSPC_LA01_CC_N) Bank 72 VCCO - VADJ - IO_L14N_T2L_N3_GC_72
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set_property PACKAGE_PIN F26 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_ck[0]"] ;# (FMCP_HSPC_LA01_CC_P) Bank 72 VCCO - VADJ - IO_L14P_T2L_N2_GC_72
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set_property PACKAGE_PIN G27 [get_ports "pad_hyper_dq[0][5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][5]"] ;# (FMCP_HSPC_LA05_N) Bank 72 VCCO - VADJ - IO_L9N_T1L_N5_AD12N_72
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set_property PACKAGE_PIN H27 [get_ports "pad_hyper_dq[0][6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72
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set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][6]"] ;# (FMCP_HSPC_LA05_P) Bank 72 VCCO - VADJ - IO_L9P_T1L_N4_AD12P_72
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#set_property PACKAGE_PIN L23 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_csn[1]"] ;# (FMCP_HSPC_LA02_P) Bank 72 VCCO - VADJ - IO_L4P_T0U_N6_DBC_AD7P_72
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#set_property PACKAGE_PIN K23 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[5]"] ;# (FMCP_HSPC_LA16_N) Bank 72 VCCO - VADJ - IO_L3N_T0L_N5_AD15N_72
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#set_property PACKAGE_PIN K24 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72
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#set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[4]"] ;# (FMCP_HSPC_LA16_P) Bank 72 VCCO - VADJ - IO_L3P_T0L_N4_AD15P_72

‎target/xilinx/flavor_vanilla/scripts/run.tcl‎

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@@ -20,6 +20,9 @@ switch $::env(XILINX_BOARD) {
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if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} {
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import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_ext_jtag.xdc
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}
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if {![info exists ::env(GEN_NO_HYPERBUS)] || ($::env(GEN_NO_HYPERBUS)==0)} {
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import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD)_hyperbus.xdc
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}
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# Vanilla specific
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import_files -fileset constrs_1 -norecurse constraints/carfield_top_xilinx.xdc

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