VCU128: ECC-protected DRAM generates unchecked SLVERR responses

[ricted98]

The VCU128 uses the following DRAM interface:

cheshire/target/xilinx/scripts/impl_ip.tcl

Line 147 in 2d0b8f8

CONFIG.C0_DDR4_BOARD_INTERFACE {ddr4_sdram} \

Through Vivado IP Catalog, it includes ECC protection:

cheshire/target/xilinx/scripts/impl_ip.tcl

Line 155 in 2d0b8f8

CONFIG.C0.DDR4_Ecc {true} \

Uninitialized memory location will return data, but can possibly generate SLVERR in RRESP due to ECC protection.
The current Write Back cache subsystem does not check on RRESP being different from 0, so it basically masks the SLVERR and allocate a cache line nevertheless.
As the CVA6 project is adopting the HPDCache, in the WB case SLVERR is noted and any refill is discarded. This results in the core always failing to get data from the memory as it is never initialized.

Write-through policy should be fine since a write is always visible to the memory.

While this issue does not affect the main branch of Cheshire, it can easily cause unexpected, hard-to-debug issues whenever the HPDCache is adopted, like me and @alex96295 are working on.
This issue has the aim to keep track of this problem and to discuss possible solutions in anticipation of future bumps of CVA6.