From bb8dc7fac78671d5835e1a1f8511c1b792843036 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 19 Jun 2025 10:06:10 +0200
Subject: [PATCH 01/39] deps: Update common_cells to v1.38.0

---
 Bender.lock | 36 ++++++++++++++++++------------------
 Bender.yml  |  2 +-
 2 files changed, 19 insertions(+), 19 deletions(-)

diff --git a/Bender.lock b/Bender.lock
index 1a9a5c98..6bf3ab46 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -15,8 +15,8 @@ packages:
     - apb
     - register_interface
   axi:
-    revision: 39f5f2d51c5e524f6fc5cf8b6e901f7dcc5622d7
-    version: 0.39.6
+    revision: f07498d53ecd5518b277c7d213ec3b71ca4df93c
+    version: 0.39.7
     source:
       Git: https://github.com/pulp-platform/axi.git
     dependencies:
@@ -24,8 +24,8 @@ packages:
     - common_verification
     - tech_cells_generic
   axi_llc:
-    revision: 559bcbd09a5a884dbe31e2d72fd95d024e357f39
-    version: 0.2.1
+    revision: 59bb8a681347e1133f11a82190fbf4bc11900d9e
+    version: 0.2.2
     source:
       Git: https://github.com/pulp-platform/axi_llc.git
     dependencies:
@@ -60,8 +60,8 @@ packages:
     dependencies:
     - common_cells
   axi_vga:
-    revision: 3718b9930f94a9eaad8ee50b4bccc71df0403084
-    version: 0.1.3
+    revision: 4d3e70d4f47bb74edc1ab68d99ffc02382e0fb9e
+    version: 0.1.4
     source:
       Git: https://github.com/pulp-platform/axi_vga.git
     dependencies:
@@ -85,16 +85,16 @@ packages:
     - common_cells
     - register_interface
   common_cells:
-    revision: 13f28aa0021fc22c0d01a12d618fda58d2c93239
-    version: 1.33.0
+    revision: 9afda9abb565971649c2aa0985639c096f351171
+    version: 1.38.0
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
     - common_verification
     - tech_cells_generic
   common_verification:
-    revision: 9c07fa860593b2caabd9b5681740c25fac04b878
-    version: 0.2.3
+    revision: fb1885f48ea46164a10568aeff51884389f67ae3
+    version: 0.2.5
     source:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
@@ -131,8 +131,8 @@ packages:
     dependencies:
     - common_cells
   idma:
-    revision: c12caf59bb482fe44b27361f6924ad346b2d22fe
-    version: 0.6.3
+    revision: ff5d56fffb3767814db88d6bf8f381974ea33aa5
+    version: 0.6.4
     source:
       Git: https://github.com/pulp-platform/iDMA.git
     dependencies:
@@ -152,8 +152,8 @@ packages:
     - common_cells
     - register_interface
   obi:
-    revision: 5321106817e177d6c16ecc4daa922b96b1bc946b
-    version: 0.1.5
+    revision: 0155fc34e900c7c884e081c0a1114a247937ff69
+    version: 0.1.7
     source:
       Git: https://github.com/pulp-platform/obi.git
     dependencies:
@@ -169,8 +169,8 @@ packages:
     - register_interface
     - tech_cells_generic
   register_interface:
-    revision: ae616e5a1ec2b41e72d200e5ab09c65e94aebd3d
-    version: 0.4.4
+    revision: 5daa85d164cf6b54ad061ea1e4c6f3624556e467
+    version: 0.4.5
     source:
       Git: https://github.com/pulp-platform/register_interface.git
     dependencies:
@@ -187,8 +187,8 @@ packages:
     - common_cells
     - tech_cells_generic
   serial_link:
-    revision: 5a25f5a71074f1ebb6de7b5280f2b16924bcc666
-    version: 1.1.1
+    revision: c55df03a1da06b00e567cf968b1b1a5f40c9f802
+    version: 1.1.2
     source:
       Git: https://github.com/pulp-platform/serial_link.git
     dependencies:
diff --git a/Bender.yml b/Bender.yml
index 677449d5..212053f5 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -20,7 +20,7 @@ dependencies:
   axi_vga:                  { git: "https://github.com/pulp-platform/axi_vga.git",                version: 0.1.3  }
   clic:                     { git: "https://github.com/pulp-platform/clic.git",                   version: 2.0.0  }
   clint:                    { git: "https://github.com/pulp-platform/clint.git",                  version: 0.2.0  }
-  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.33.0 }
+  common_cells:             { git: "https://github.com/pulp-platform/common_cells.git",           version: 1.38.0 }
   common_verification:      { git: "https://github.com/pulp-platform/common_verification.git",    version: 0.2.0  }
   cva6:                     { git: "https://github.com/pulp-platform/cva6.git",                   rev: pulp-v1.0.0 }
   iDMA:                     { git: "https://github.com/pulp-platform/iDMA.git",                   version: 0.6.3  }

From 850970f1b87ac96ddba119366411e30b2d7fc277 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 19 Jun 2025 10:08:03 +0200
Subject: [PATCH 02/39] target/sim/verilator: Initial verilator support

---
 .gitignore                                    |   8 +
 Bender.yml                                    |   4 +
 cheshire.mk                                   |   2 +
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 174 ++++++++++++++++++
 target/sim/verilator/src/sim_main.cpp         | 118 ++++++++++++
 target/sim/verilator/verilator.mk             |  35 ++++
 6 files changed, 341 insertions(+)
 create mode 100644 target/sim/verilator/src/cheshire_soc_wrapper.sv
 create mode 100644 target/sim/verilator/src/sim_main.cpp
 create mode 100644 target/sim/verilator/verilator.mk

diff --git a/.gitignore b/.gitignore
index 4c8e9b87..8ea089b3 100644
--- a/.gitignore
+++ b/.gitignore
@@ -48,6 +48,14 @@ target/sim/vcs/ucli.key
 target/sim/vcs/work*
 target/sim/vcs/vc_hdrs.h
 
+# Verilator generated files
+target/sim/verilator/obj_dir/
+target/sim/verilator/*.flist
+target/sim/verilator/*.vlt
+target/sim/verilator/*.vcd
+target/sim/verilator/logs/
+target/sim/verilator/trace_hart_*.dasm
+
 # Xilinx generated files
 target/xilinx/build
 target/xilinx/out
diff --git a/Bender.yml b/Bender.yml
index 212053f5..00c7acce 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -54,6 +54,10 @@ sources:
       - target/sim/src/fixture_cheshire_soc.sv
       - target/sim/src/tb_cheshire_soc.sv
 
+  - target: any(verilator)
+    files:
+      - target/sim/verilator/src/cheshire_soc_wrapper.sv
+
   - target: all(fpga, xilinx)
     files:
       - target/xilinx/src/phy_definitions.svh
diff --git a/cheshire.mk b/cheshire.mk
index f838911b..799833d9 100644
--- a/cheshire.mk
+++ b/cheshire.mk
@@ -175,6 +175,8 @@ CHS_SIM_ALL += $(CHS_ROOT)/target/sim/models/24FC1025.v
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vsim/compile.cheshire_soc.tcl
 CHS_SIM_ALL += $(CHS_ROOT)/target/sim/vcs/compile.cheshire_soc.sh
 
+include $(CHS_ROOT)/target/sim/verilator/verilator.mk
+
 ###########
 # DRAMSys #
 ###########
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
new file mode 100644
index 00000000..badc2ff4
--- /dev/null
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -0,0 +1,174 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Max Wipfli <mwipfli@student.ethz.ch>
+
+module cheshire_soc_wrapper #(
+  parameter time ClkPeriodSys         = 5ns,
+  parameter time ClkPeriodRtc         = 30518ns,
+  parameter int unsigned RstClkCycles = 5
+) (
+  output logic clk_o,
+  output logic rst_no
+);
+
+  `include "cheshire/typedef.svh"
+
+  import cheshire_pkg::*;
+
+  localparam cheshire_cfg_t DutCfg = DefaultCfg;
+
+  `CHESHIRE_TYPEDEF_ALL(, DutCfg)
+
+  ///////////
+  //  DUT  //
+  ///////////
+
+  logic       clk;
+  logic       rst_n;
+  logic       test_mode;
+  logic [1:0] boot_mode;
+  logic       rtc;
+
+  axi_llc_req_t axi_llc_mst_req;
+  axi_llc_rsp_t axi_llc_mst_rsp;
+
+  logic jtag_tck;
+  logic jtag_trst_n;
+  logic jtag_tms;
+  logic jtag_tdi;
+  logic jtag_tdo;
+
+  logic uart_tx;
+  logic uart_rx;
+
+  logic i2c_sda_o;
+  logic i2c_sda_i;
+  logic i2c_sda_en;
+  logic i2c_scl_o;
+  logic i2c_scl_i;
+  logic i2c_scl_en;
+
+  logic                 spih_sck_o;
+  logic                 spih_sck_en;
+  logic [SpihNumCs-1:0] spih_csb_o;
+  logic [SpihNumCs-1:0] spih_csb_en;
+  logic [ 3:0]          spih_sd_o;
+  logic [ 3:0]          spih_sd_i;
+  logic [ 3:0]          spih_sd_en;
+
+  logic [SlinkNumChan-1:0]                    slink_rcv_clk_i;
+  logic [SlinkNumChan-1:0]                    slink_rcv_clk_o;
+  logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i;
+  logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o;
+
+  cheshire_soc #(
+    .Cfg                ( DutCfg ),
+    .ExtHartinfo        ( '0 ),
+    .axi_ext_llc_req_t  ( axi_llc_req_t ),
+    .axi_ext_llc_rsp_t  ( axi_llc_rsp_t ),
+    .axi_ext_mst_req_t  ( axi_mst_req_t ),
+    .axi_ext_mst_rsp_t  ( axi_mst_rsp_t ),
+    .axi_ext_slv_req_t  ( axi_slv_req_t ),
+    .axi_ext_slv_rsp_t  ( axi_slv_rsp_t ),
+    .reg_ext_req_t      ( reg_req_t ),
+    .reg_ext_rsp_t      ( reg_rsp_t )
+  ) dut (
+    .clk_i              ( clk       ),
+    .rst_ni             ( rst_n     ),
+    .test_mode_i        ( test_mode ),
+    .boot_mode_i        ( boot_mode ),
+    .rtc_i              ( rtc       ),
+    .axi_llc_mst_req_o  ( axi_llc_mst_req ),
+    .axi_llc_mst_rsp_i  ( axi_llc_mst_rsp ),
+    .axi_ext_mst_req_i  ( '0 ),
+    .axi_ext_mst_rsp_o  ( ),
+    .axi_ext_slv_req_o  ( ),
+    .axi_ext_slv_rsp_i  ( '0 ),
+    .reg_ext_slv_req_o  ( ),
+    .reg_ext_slv_rsp_i  ( '0 ),
+    .intr_ext_i         ( '0 ),
+    .intr_ext_o         ( ),
+    .xeip_ext_o         ( ),
+    .mtip_ext_o         ( ),
+    .msip_ext_o         ( ),
+    .dbg_active_o       ( ),
+    .dbg_ext_req_o      ( ),
+    .dbg_ext_unavail_i  ( '0 ),
+    .jtag_tck_i         ( jtag_tck    ),
+    .jtag_trst_ni       ( jtag_trst_n ),
+    .jtag_tms_i         ( jtag_tms    ),
+    .jtag_tdi_i         ( jtag_tdi    ),
+    .jtag_tdo_o         ( jtag_tdo    ),
+    .jtag_tdo_oe_o      ( ),
+    .uart_tx_o          ( uart_tx ),
+    .uart_rx_i          ( uart_rx ),
+    .uart_rts_no        ( ),
+    .uart_dtr_no        ( ),
+    .uart_cts_ni        ( 1'b0 ),
+    .uart_dsr_ni        ( 1'b0 ),
+    .uart_dcd_ni        ( 1'b0 ),
+    .uart_rin_ni        ( 1'b0 ),
+    .i2c_sda_o          ( i2c_sda_o  ),
+    .i2c_sda_i          ( i2c_sda_i  ),
+    .i2c_sda_en_o       ( i2c_sda_en ),
+    .i2c_scl_o          ( i2c_scl_o  ),
+    .i2c_scl_i          ( i2c_scl_i  ),
+    .i2c_scl_en_o       ( i2c_scl_en ),
+    .spih_sck_o         ( spih_sck_o  ),
+    .spih_sck_en_o      ( spih_sck_en ),
+    .spih_csb_o         ( spih_csb_o  ),
+    .spih_csb_en_o      ( spih_csb_en ),
+    .spih_sd_o          ( spih_sd_o   ),
+    .spih_sd_en_o       ( spih_sd_en  ),
+    .spih_sd_i          ( spih_sd_i   ),
+    .gpio_i             ( '0 ),
+    .gpio_o             ( ),
+    .gpio_en_o          ( ),
+    .slink_rcv_clk_i    ( slink_rcv_clk_i ),
+    .slink_rcv_clk_o    ( slink_rcv_clk_o ),
+    .slink_i            ( slink_i ),
+    .slink_o            ( slink_o ),
+    .vga_hsync_o        ( ),
+    .vga_vsync_o        ( ),
+    .vga_red_o          ( ),
+    .vga_green_o        ( ),
+    .vga_blue_o         ( ),
+    .usb_clk_i          ( 1'b0 ),
+    .usb_rst_ni         ( 1'b1 ),
+    .usb_dm_i           ( '0 ),
+    .usb_dm_o           ( ),
+    .usb_dm_oe_o        ( ),
+    .usb_dp_i           ( '0 ),
+    .usb_dp_o           ( ),
+    .usb_dp_oe_o        ( )
+  );
+
+  /////////////////////////////
+  //  Clock/Reset Generation //
+  /////////////////////////////
+  clk_rst_gen #(
+    .ClkPeriod    ( ClkPeriodSys ),
+    .RstClkCycles ( RstClkCycles )
+  ) i_clk_rst_sys (
+    .clk_o  ( clk   ),
+    .rst_no ( rst_n )
+  );
+
+  clk_rst_gen #(
+    .ClkPeriod    ( ClkPeriodRtc ),
+    .RstClkCycles ( RstClkCycles )
+  ) i_clk_rst_rtc (
+    .clk_o  ( rtc ),
+    .rst_no ( )
+  );
+
+  /////////////////
+  //  I/O to C++ //
+  /////////////////
+
+  assign clk_o = clk;
+  assign rst_no = rst_n;
+
+endmodule
diff --git a/target/sim/verilator/src/sim_main.cpp b/target/sim/verilator/src/sim_main.cpp
new file mode 100644
index 00000000..c8290b5a
--- /dev/null
+++ b/target/sim/verilator/src/sim_main.cpp
@@ -0,0 +1,118 @@
+#include <memory> // std::unique_ptr
+
+#include <verilated.h> // common Verilator routines
+#include <verilated_vcd_c.h> // trace to VCD
+
+#include "Vcheshire_soc_wrapper.h" // Verilated model
+
+#define TRACE
+
+int main(int argc, char** argv) {
+    // This is a more complicated example, please also see the simpler examples/make_hello_c.
+
+    // Create logs/ directory in case we have traces to put under it
+    Verilated::mkdir("logs");
+
+    // Construct a VerilatedContext to hold simulation time, etc.
+    // Multiple modules (made later below with Vtop) may share the same
+    // context to share time, or modules may have different contexts if
+    // they should be independent from each other.
+
+    // Using unique_ptr is similar to
+    // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
+    const auto contextp = std::make_unique<VerilatedContext>();
+    // const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
+    // Do not instead make Vtop as a file-scope static variable, as the
+    // "C++ static initialization order fiasco" may cause a crash
+
+    // Set debug level, 0 is off, 9 is highest presently used
+    // May be overridden by commandArgs argument parsing
+    contextp->debug(0);
+
+    // Randomization reset policy
+    // May be overridden by commandArgs argument parsing
+    contextp->randReset(2);
+
+    // Verilator must compute traced signals
+    contextp->traceEverOn(true);
+
+    // Pass arguments so Verilated code can see them, e.g. $value$plusargs
+    // This needs to be called before you create any model
+    contextp->commandArgs(argc, argv);
+
+    // "WRAPPER" will be the hierarchical name of the module
+    const auto top = std::make_unique<Vcheshire_soc_wrapper>(contextp.get(), "TOP");
+
+#ifdef TRACE
+    Verilated::traceEverOn(true);
+    const auto trace = std::make_unique<VerilatedVcdC>();
+    top->trace(trace.get(), 2);
+    trace->open("dump.vcd");
+#endif
+
+    // Set Vtop's input signals
+    // top->reset_l = !0;
+    // top->clk = 0;
+    // top->in_small = 1;
+    // top->in_quad = 0x1234;
+    // top->in_wide[0] = 0x11111111;
+    // top->in_wide[1] = 0x22222222;
+    // top->in_wide[2] = 0x3;
+
+    // Simulate until $finish
+    while (!contextp->gotFinish()) {
+        contextp->timeInc(1);  // 1 timeprecision period passes...
+
+        // VL_PRINTF("toggle...\n");
+
+        // Toggle control signals on an edge that doesn't correspond
+        // to where the controls are sampled; in this example we do
+        // this only on a negedge of clk, because we know
+        // reset is not sampled there.
+        // if (!top->clk) {
+        //     if (contextp->time() > 1 && contextp->time() < 10) {
+        //         top->reset_l = !1;  // Assert reset
+        //     } else {
+        //         top->reset_l = !0;  // Deassert reset
+        //     }
+        //     // Assign some other inputs
+        //     top->in_quad += 0x12;
+        // }
+
+        // Evaluate model
+        // (If you have multiple models being simulated in the same
+        // timestep then instead of eval(), call eval_step() on each, then
+        // eval_end_step() on each. See the manual.)
+        top->eval();
+
+#ifdef TRACE
+        trace->dump(contextp->time());
+#endif
+
+        // // Read outputs
+        // VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64
+        //           " owide=%x_%08x_%08x\n",
+        //           contextp->time(), top->clk, top->reset_l, top->in_quad, top->out_quad,
+        //           top->out_wide[2], top->out_wide[1], top->out_wide[0]);
+    }
+
+    // Final model cleanup
+    top->final();
+
+#ifdef TRACE
+      trace->close();
+#endif
+
+    // Coverage analysis (calling write only after the test is known to pass)
+#if VM_COVERAGE
+    Verilated::mkdir("logs");
+    contextp->coveragep()->write("logs/coverage.dat");
+#endif
+
+    // Final simulation summary
+    contextp->statsPrintSummary();
+
+    // Return good completion status
+    // Don't use exit() or destructor won't get called
+    return 0;
+}
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
new file mode 100644
index 00000000..2b0f5bc6
--- /dev/null
+++ b/target/sim/verilator/verilator.mk
@@ -0,0 +1,35 @@
+# Copyright 2025 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# Max Wipfli <mwipfli@student.ethz.ch>
+# Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+CHS_VERILATOR_DIR ?= $(CHS_ROOT)/target/sim/verilator
+
+VERILATOR = oseda verilator
+
+VERILATOR_CFLAGS  = -O3
+VERILATOR_OPT     = -march=native -mtune=native -Wno-deprecated-experimental-coroutine
+# Silly Verilator warnings: these are perfectly valid and should not be warnings
+VERILATOR_WNO   = -Wno-fatal -Wno-style -Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-ASCRANGE
+VERILATOR_FIX   = --unroll-count 51 --unroll-stmts 1
+VERILATOR_ARGS  ?= -j 0 -Wall --timing -timescale 1ns/1ns $(VERILATOR_WNO) $(VERILATOR_FIX) -O3 \
+									 --trace --trace-depth 2
+
+VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/src/sim_main.cpp
+
+$(CHS_VERILATOR_DIR)/cheshire_soc.flist: $(CHS_ROOT)/Bender.yml
+	$(BENDER) script verilator $(CHS_BENDER_RTL_FLAGS) > $@
+
+$(CHS_ROOT)/target/sim/verilator/obj_dir/cheshire_soc_wrapper: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist $(VERILATOR_CXX_SRCS)
+	+cd $(dir $@) && $(VERILATOR) $(VERILATOR_ARGS) -DASSERTS_OFF -f $< $(VERILATOR_CXX_SRCS) \
+		--cc --exe --build --top-module cheshire_soc_wrapper
+
+$(CHS_ROOT)/target/sim/verilator/cheshire_soc.vlt: $(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper
+	@echo "#!/bin/sh" > $@
+	@echo 'set -eu' >> $@
+	@echo 'cd $$(dirname "$$0")' >> $@
+	@echo 'oseda ./obj_dir/Vcheshire_soc_wrapper' >> $@
+	@chmod +x $@
+

From 9dd2c19269f0e3ff30c57e30dd86d0605ff95f35 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 19 Jun 2025 18:10:24 +0200
Subject: [PATCH 03/39] target/sim/verilator: Add JTAG support using OpenOCD
 remote_bitbang

---
 .gitignore                                    |  1 +
 .../{src/sim_main.cpp => sim/main.cpp}        | 37 +++++++++++++++++--
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 29 ++++++++++-----
 target/sim/verilator/verilator.mk             | 15 +++++---
 util/openocd.verilator.tcl                    | 15 ++++++++
 5 files changed, 78 insertions(+), 19 deletions(-)
 rename target/sim/verilator/{src/sim_main.cpp => sim/main.cpp} (81%)
 create mode 100644 util/openocd.verilator.tcl

diff --git a/.gitignore b/.gitignore
index 8ea089b3..80ef51f9 100644
--- a/.gitignore
+++ b/.gitignore
@@ -51,6 +51,7 @@ target/sim/vcs/vc_hdrs.h
 # Verilator generated files
 target/sim/verilator/obj_dir/
 target/sim/verilator/*.flist
+target/sim/verilator/*.fst
 target/sim/verilator/*.vlt
 target/sim/verilator/*.vcd
 target/sim/verilator/logs/
diff --git a/target/sim/verilator/src/sim_main.cpp b/target/sim/verilator/sim/main.cpp
similarity index 81%
rename from target/sim/verilator/src/sim_main.cpp
rename to target/sim/verilator/sim/main.cpp
index c8290b5a..2fb09a33 100644
--- a/target/sim/verilator/src/sim_main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -1,12 +1,35 @@
 #include <memory> // std::unique_ptr
 
 #include <verilated.h> // common Verilator routines
-#include <verilated_vcd_c.h> // trace to VCD
+#include <verilated_fst_c.h> // trace to VCD
 
 #include "Vcheshire_soc_wrapper.h" // Verilated model
 
 #define TRACE
 
+extern int jtag_tick(int port, unsigned char *jtag_TCK, unsigned char *jtag_TMS,
+    unsigned char *jtag_TDI, unsigned char *jtag_TRSTn, unsigned char jtag_TDO);
+
+
+static void jtag_tick_io(Vcheshire_soc_wrapper& top) {
+  static int count = 0;
+  if (count < 5) {
+    count++;
+    return;
+  }
+  count = 0;
+
+  unsigned char tck, tms, tdi, trst_n;
+  int ret = jtag_tick(3335, &tck, &tms, &tdi, &trst_n, top.jtag_tdo_o);
+  if (ret)
+    VL_PRINTF("ret = 0x%08x\n", ret);
+  top.jtag_tck_i   = tck;
+  top.jtag_tms_i   = tms;
+  top.jtag_tdi_i   = tdi;
+  top.jtag_trst_ni = trst_n;
+}
+
+
 int main(int argc, char** argv) {
     // This is a more complicated example, please also see the simpler examples/make_hello_c.
 
@@ -45,9 +68,9 @@ int main(int argc, char** argv) {
 
 #ifdef TRACE
     Verilated::traceEverOn(true);
-    const auto trace = std::make_unique<VerilatedVcdC>();
-    top->trace(trace.get(), 2);
-    trace->open("dump.vcd");
+    const auto trace = std::make_unique<VerilatedFstC>();
+    top->trace(trace.get(), 5);
+    trace->open("dump.fst");
 #endif
 
     // Set Vtop's input signals
@@ -61,6 +84,8 @@ int main(int argc, char** argv) {
 
     // Simulate until $finish
     while (!contextp->gotFinish()) {
+        unsigned char clk_prev = top->clk_o;
+
         contextp->timeInc(1);  // 1 timeprecision period passes...
 
         // VL_PRINTF("toggle...\n");
@@ -89,6 +114,10 @@ int main(int argc, char** argv) {
         trace->dump(contextp->time());
 #endif
 
+        if (top->rst_no && !top->clk_o && clk_prev) {
+          jtag_tick_io(*top);
+        }
+
         // // Read outputs
         // VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64
         //           " owide=%x_%08x_%08x\n",
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index badc2ff4..d528bb5e 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -7,10 +7,20 @@
 module cheshire_soc_wrapper #(
   parameter time ClkPeriodSys         = 5ns,
   parameter time ClkPeriodRtc         = 30518ns,
-  parameter int unsigned RstClkCycles = 5
+  parameter int unsigned RstClkCycles = 5,
+
+  parameter int unsigned RemoteBitbangPort = 3335
 ) (
   output logic clk_o,
-  output logic rst_no
+  output logic rst_no,
+
+  // JTAG
+  input  logic jtag_tck_i,
+  input  logic jtag_trst_ni,
+  input  logic jtag_tms_i,
+  input  logic jtag_tdi_i,
+  output logic jtag_tdo_o,
+  output logic jtag_tdo_oe_o
 );
 
   `include "cheshire/typedef.svh"
@@ -39,6 +49,7 @@ module cheshire_soc_wrapper #(
   logic jtag_tms;
   logic jtag_tdi;
   logic jtag_tdo;
+  logic jtag_tdo_oe;
 
   logic uart_tx;
   logic uart_rx;
@@ -74,7 +85,7 @@ module cheshire_soc_wrapper #(
     .axi_ext_slv_rsp_t  ( axi_slv_rsp_t ),
     .reg_ext_req_t      ( reg_req_t ),
     .reg_ext_rsp_t      ( reg_rsp_t )
-  ) dut (
+  ) i_dut (
     .clk_i              ( clk       ),
     .rst_ni             ( rst_n     ),
     .test_mode_i        ( test_mode ),
@@ -96,12 +107,12 @@ module cheshire_soc_wrapper #(
     .dbg_active_o       ( ),
     .dbg_ext_req_o      ( ),
     .dbg_ext_unavail_i  ( '0 ),
-    .jtag_tck_i         ( jtag_tck    ),
-    .jtag_trst_ni       ( jtag_trst_n ),
-    .jtag_tms_i         ( jtag_tms    ),
-    .jtag_tdi_i         ( jtag_tdi    ),
-    .jtag_tdo_o         ( jtag_tdo    ),
-    .jtag_tdo_oe_o      ( ),
+    .jtag_tck_i         ( jtag_tck_i    ),
+    .jtag_trst_ni       ( jtag_trst_ni  ),
+    .jtag_tms_i         ( jtag_tms_i    ),
+    .jtag_tdi_i         ( jtag_tdi_i    ),
+    .jtag_tdo_o         ( jtag_tdo_o    ),
+    .jtag_tdo_oe_o      ( jtag_tdo_oe_o ),
     .uart_tx_o          ( uart_tx ),
     .uart_rx_i          ( uart_rx ),
     .uart_rts_no        ( ),
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 2b0f5bc6..3bf72818 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -6,24 +6,27 @@
 # Paul Scheffler <paulsc@iis.ee.ethz.ch>
 
 CHS_VERILATOR_DIR ?= $(CHS_ROOT)/target/sim/verilator
+RISCV_DBG_DIR = $(shell bender path riscv-dbg)
 
 VERILATOR = oseda verilator
 
-VERILATOR_CFLAGS  = -O3
 VERILATOR_OPT     = -march=native -mtune=native -Wno-deprecated-experimental-coroutine
 # Silly Verilator warnings: these are perfectly valid and should not be warnings
-VERILATOR_WNO   = -Wno-fatal -Wno-style -Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-ASCRANGE
+VERILATOR_WNO   = -Wno-fatal -Wno-style \
+									-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
 VERILATOR_FIX   = --unroll-count 51 --unroll-stmts 1
 VERILATOR_ARGS  ?= -j 0 -Wall --timing -timescale 1ns/1ns $(VERILATOR_WNO) $(VERILATOR_FIX) -O3 \
-									 --trace --trace-depth 2
+									 --trace-fst --trace-structs --trace-threads 1 --no-trace-top --trace-depth 5
 
-VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/src/sim_main.cpp
+VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/sim/main.cpp \
+										 $(RISCV_DBG_DIR)/tb/remote_bitbang/remote_bitbang.c \
+										 $(RISCV_DBG_DIR)/tb/remote_bitbang/sim_jtag.c
 
 $(CHS_VERILATOR_DIR)/cheshire_soc.flist: $(CHS_ROOT)/Bender.yml
 	$(BENDER) script verilator $(CHS_BENDER_RTL_FLAGS) > $@
 
-$(CHS_ROOT)/target/sim/verilator/obj_dir/cheshire_soc_wrapper: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist $(VERILATOR_CXX_SRCS)
-	+cd $(dir $@) && $(VERILATOR) $(VERILATOR_ARGS) -DASSERTS_OFF -f $< $(VERILATOR_CXX_SRCS) \
+$(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist $(VERILATOR_CXX_SRCS)
+	+cd $(CHS_VERILATOR_DIR) && $(VERILATOR) $(VERILATOR_ARGS) -DASSERTS_OFF -f $< $(VERILATOR_CXX_SRCS) \
 		--cc --exe --build --top-module cheshire_soc_wrapper
 
 $(CHS_ROOT)/target/sim/verilator/cheshire_soc.vlt: $(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper
diff --git a/util/openocd.verilator.tcl b/util/openocd.verilator.tcl
new file mode 100644
index 00000000..105af840
--- /dev/null
+++ b/util/openocd.verilator.tcl
@@ -0,0 +1,15 @@
+# Copyright 2024 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+#
+# OpenOCD script for Cheshire on Verilator (using remote_bitbang).
+
+adapter_khz 8000
+
+interface remote_bitbang
+remote_bitbang_host localhost
+remote_bitbang_port 3335
+
+set irlen 5
+
+source [file dirname [info script]]/openocd.common.tcl

From 3aeb6e0c719fe59ed597981443689fd499b5eb40 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 19 Jun 2025 18:11:50 +0200
Subject: [PATCH 04/39] target/sim/verilator: Tie off unused signals

---
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 22 ++++++++++++++-----
 1 file changed, 16 insertions(+), 6 deletions(-)

diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index d528bb5e..1f819020 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -37,10 +37,14 @@ module cheshire_soc_wrapper #(
 
   logic       clk;
   logic       rst_n;
+
   logic       test_mode;
   logic [1:0] boot_mode;
   logic       rtc;
 
+  assign test_mode = 1'b0;
+  assign boot_mode = 2'b00; // passive
+
   axi_llc_req_t axi_llc_mst_req;
   axi_llc_rsp_t axi_llc_mst_rsp;
 
@@ -60,6 +64,8 @@ module cheshire_soc_wrapper #(
   logic i2c_scl_o;
   logic i2c_scl_i;
   logic i2c_scl_en;
+  assign i2c_sda_i = 1'b0;
+  assign i2c_scl_i = 1'b0;
 
   logic                 spih_sck_o;
   logic                 spih_sck_en;
@@ -68,11 +74,14 @@ module cheshire_soc_wrapper #(
   logic [ 3:0]          spih_sd_o;
   logic [ 3:0]          spih_sd_i;
   logic [ 3:0]          spih_sd_en;
+  assign spih_sd_i = 1'b0;
 
   logic [SlinkNumChan-1:0]                    slink_rcv_clk_i;
   logic [SlinkNumChan-1:0]                    slink_rcv_clk_o;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o;
+  assign slink_rcv_clk_i = '0;
+  assign slink_i         = '0;
 
   cheshire_soc #(
     .Cfg                ( DutCfg ),
@@ -156,9 +165,10 @@ module cheshire_soc_wrapper #(
     .usb_dp_oe_o        ( )
   );
 
-  /////////////////////////////
-  //  Clock/Reset Generation //
-  /////////////////////////////
+  //////////////////////////////
+  //  Clock/Reset Generation  //
+  //////////////////////////////
+
   clk_rst_gen #(
     .ClkPeriod    ( ClkPeriodSys ),
     .RstClkCycles ( RstClkCycles )
@@ -175,9 +185,9 @@ module cheshire_soc_wrapper #(
     .rst_no ( )
   );
 
-  /////////////////
-  //  I/O to C++ //
-  /////////////////
+  //////////////////
+  //  I/O to C++  //
+  //////////////////
 
   assign clk_o = clk;
   assign rst_no = rst_n;

From a3f961111a2d7da65f056f886ea9c6950cc18e5b Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 19 Jun 2025 20:35:51 +0200
Subject: [PATCH 05/39] target/sim/verilator: Disable serial link

---
 target/sim/verilator/src/cheshire_soc_wrapper.sv | 16 +++++++++++-----
 1 file changed, 11 insertions(+), 5 deletions(-)

diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 1f819020..29f11ac3 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -27,7 +27,13 @@ module cheshire_soc_wrapper #(
 
   import cheshire_pkg::*;
 
-  localparam cheshire_cfg_t DutCfg = DefaultCfg;
+  function automatic cheshire_pkg::cheshire_cfg_t gen_cheshire_cfg();
+    cheshire_pkg::cheshire_cfg_t ret = cheshire_pkg::DefaultCfg;
+    ret.SerialLink = 1'b0;
+    return ret;
+  endfunction
+
+  localparam cheshire_cfg_t DutCfg = gen_cheshire_cfg();
 
   `CHESHIRE_TYPEDEF_ALL(, DutCfg)
 
@@ -64,8 +70,8 @@ module cheshire_soc_wrapper #(
   logic i2c_scl_o;
   logic i2c_scl_i;
   logic i2c_scl_en;
-  assign i2c_sda_i = 1'b0;
-  assign i2c_scl_i = 1'b0;
+  assign i2c_sda_i = 1'b1;
+  assign i2c_scl_i = 1'b1;
 
   logic                 spih_sck_o;
   logic                 spih_sck_en;
@@ -80,8 +86,8 @@ module cheshire_soc_wrapper #(
   logic [SlinkNumChan-1:0]                    slink_rcv_clk_o;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o;
-  assign slink_rcv_clk_i = '0;
-  assign slink_i         = '0;
+  assign slink_rcv_clk_i = '1;
+  assign slink_i         = '1;
 
   cheshire_soc #(
     .Cfg                ( DutCfg ),

From 2c8c87b8b3fe62957d40cc67a8251e0c8be0b460 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 19 Jun 2025 20:37:25 +0200
Subject: [PATCH 06/39] target/sim/verilator: Add simulated DRAM memory

We have to be careful where to place this, as its reset logic is very
flaky with respect to event order. This should be fixed within
axi_sim_mem itself.
---
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 36 +++++++++++++++++++
 target/sim/verilator/verilator.mk             |  2 ++
 2 files changed, 38 insertions(+)

diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 29f11ac3..09f57fba 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -191,6 +191,42 @@ module cheshire_soc_wrapper #(
     .rst_no ( )
   );
 
+  ////////////
+  //  DRAM  //
+  ////////////
+
+  axi_sim_mem #(
+    .AddrWidth          ( DutCfg.AddrWidth    ),
+    .DataWidth          ( DutCfg.AxiDataWidth ),
+    .IdWidth            ( $bits(axi_llc_id_t) ),
+    .UserWidth          ( DutCfg.AxiUserWidth ),
+    .axi_req_t          ( axi_llc_req_t ),
+    .axi_rsp_t          ( axi_llc_rsp_t ),
+    .WarnUninitialized  ( 0 ),
+    .ClearErrOnAccess   ( 1 ),
+    .ApplDelay          ( 0ps ),
+    .AcqDelay           ( 0ps )
+  ) i_dram_sim_mem (
+    .clk_i              ( clk   ),
+    .rst_ni             ( rst_n ),
+    .axi_req_i          ( axi_llc_mst_req ),
+    .axi_rsp_o          ( axi_llc_mst_rsp ),
+    .mon_w_valid_o      ( ),
+    .mon_w_addr_o       ( ),
+    .mon_w_data_o       ( ),
+    .mon_w_id_o         ( ),
+    .mon_w_user_o       ( ),
+    .mon_w_beat_count_o ( ),
+    .mon_w_last_o       ( ),
+    .mon_r_valid_o      ( ),
+    .mon_r_addr_o       ( ),
+    .mon_r_data_o       ( ),
+    .mon_r_id_o         ( ),
+    .mon_r_user_o       ( ),
+    .mon_r_beat_count_o ( ),
+    .mon_r_last_o       ( )
+  );
+
   //////////////////
   //  I/O to C++  //
   //////////////////
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 3bf72818..e526d4a3 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -24,6 +24,8 @@ VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/sim/main.cpp \
 
 $(CHS_VERILATOR_DIR)/cheshire_soc.flist: $(CHS_ROOT)/Bender.yml
 	$(BENDER) script verilator $(CHS_BENDER_RTL_FLAGS) > $@
+	# TODO: Add verilator target for these upstream to avoid patch-in
+	echo '$(shell $(BENDER) path axi)/src/axi_sim_mem.sv' >> $@
 
 $(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist $(VERILATOR_CXX_SRCS)
 	+cd $(CHS_VERILATOR_DIR) && $(VERILATOR) $(VERILATOR_ARGS) -DASSERTS_OFF -f $< $(VERILATOR_CXX_SRCS) \

From 0bf844836f9d79afae0627343ea9f11e152645d4 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Fri, 20 Jun 2025 11:53:48 +0200
Subject: [PATCH 07/39] target/sim/verilator: Exit when JTAG client disconnects

---
 target/sim/verilator/sim/main.cpp | 21 ++++++++++-----------
 1 file changed, 10 insertions(+), 11 deletions(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index 2fb09a33..9ce9498e 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -5,24 +5,23 @@
 
 #include "Vcheshire_soc_wrapper.h" // Verilated model
 
-#define TRACE
+
+bool do_exit = false;
+int  exit_code = 0;
 
 extern int jtag_tick(int port, unsigned char *jtag_TCK, unsigned char *jtag_TMS,
     unsigned char *jtag_TDI, unsigned char *jtag_TRSTn, unsigned char jtag_TDO);
 
 
 static void jtag_tick_io(Vcheshire_soc_wrapper& top) {
-  static int count = 0;
-  if (count < 5) {
-    count++;
+  unsigned char tck, tms, tdi, trst_n;
+  int ret = jtag_tick(3335, &tck, &tms, &tdi, &trst_n, top.jtag_tdo_o);
+  if (ret) {
+    do_exit = true;
+    exit_code = ret >> 1;
     return;
   }
-  count = 0;
 
-  unsigned char tck, tms, tdi, trst_n;
-  int ret = jtag_tick(3335, &tck, &tms, &tdi, &trst_n, top.jtag_tdo_o);
-  if (ret)
-    VL_PRINTF("ret = 0x%08x\n", ret);
   top.jtag_tck_i   = tck;
   top.jtag_tms_i   = tms;
   top.jtag_tdi_i   = tdi;
@@ -83,7 +82,7 @@ int main(int argc, char** argv) {
     // top->in_wide[2] = 0x3;
 
     // Simulate until $finish
-    while (!contextp->gotFinish()) {
+    while (!contextp->gotFinish() && !do_exit) {
         unsigned char clk_prev = top->clk_o;
 
         contextp->timeInc(1);  // 1 timeprecision period passes...
@@ -143,5 +142,5 @@ int main(int argc, char** argv) {
 
     // Return good completion status
     // Don't use exit() or destructor won't get called
-    return 0;
+    return exit_code;
 }

From c59d9bff581e5c37b84cddab3183ed679a5c9449 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Fri, 20 Jun 2025 12:39:32 +0200
Subject: [PATCH 08/39] target/sim/verilator: Disable tracing

---
 target/sim/verilator/sim/main.cpp | 1 +
 target/sim/verilator/verilator.mk | 2 +-
 2 files changed, 2 insertions(+), 1 deletion(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index 9ce9498e..b8587db1 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -5,6 +5,7 @@
 
 #include "Vcheshire_soc_wrapper.h" // Verilated model
 
+// #define TRACE
 
 bool do_exit = false;
 int  exit_code = 0;
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index e526d4a3..6b7529f8 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -16,7 +16,7 @@ VERILATOR_WNO   = -Wno-fatal -Wno-style \
 									-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
 VERILATOR_FIX   = --unroll-count 51 --unroll-stmts 1
 VERILATOR_ARGS  ?= -j 0 -Wall --timing -timescale 1ns/1ns $(VERILATOR_WNO) $(VERILATOR_FIX) -O3 \
-									 --trace-fst --trace-structs --trace-threads 1 --no-trace-top --trace-depth 5
+									 # --trace --trace-structs --no-trace-top --trace-depth 5
 
 VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/sim/main.cpp \
 										 $(RISCV_DBG_DIR)/tb/remote_bitbang/remote_bitbang.c \

From a19e7681663f211ce9e0ded442f38111637bb55e Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Fri, 20 Jun 2025 12:42:48 +0200
Subject: [PATCH 09/39] target/sim/verilator: Track simulation rate regularly

---
 target/sim/verilator/sim/main.cpp | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index b8587db1..39a0cc38 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -1,3 +1,4 @@
+#include <chrono> // timers
 #include <memory> // std::unique_ptr
 
 #include <verilated.h> // common Verilator routines
@@ -5,6 +6,8 @@
 
 #include "Vcheshire_soc_wrapper.h" // Verilated model
 
+#define SIMULATION_RATE_CHUNK 1024
+
 // #define TRACE
 
 bool do_exit = false;
@@ -82,7 +85,11 @@ int main(int argc, char** argv) {
     // top->in_wide[1] = 0x22222222;
     // top->in_wide[2] = 0x3;
 
+
     // Simulate until $finish
+    auto start = std::chrono::high_resolution_clock::now();
+    auto last = start;
+    uint64_t cycle = 0;
     while (!contextp->gotFinish() && !do_exit) {
         unsigned char clk_prev = top->clk_o;
 
@@ -118,6 +125,21 @@ int main(int argc, char** argv) {
           jtag_tick_io(*top);
         }
 
+        if (!clk_prev && top->clk_o) {
+          // posedge clk
+          cycle++;
+          if (cycle % SIMULATION_RATE_CHUNK == 0) {
+            auto current = std::chrono::high_resolution_clock::now();
+            auto total_elapsed_us = std::chrono::duration_cast<std::chrono::microseconds>(current - start).count();
+            auto last_elapsed_us = std::chrono::duration_cast<std::chrono::microseconds>(current - last).count();
+            last = current;
+            auto total_cycles_per_sec = 1000000.0 * cycle / total_elapsed_us;
+            auto last_cycles_per_sec = 1000000.0 * SIMULATION_RATE_CHUNK / last_elapsed_us;
+            VL_PRINTF("elapsed: %lu us, %.1f cycles/sec (total), %.1f cycles/sec (last)\n",
+                total_elapsed_us, total_cycles_per_sec, last_cycles_per_sec);
+          }
+        }
+
         // // Read outputs
         // VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64
         //           " owide=%x_%08x_%08x\n",

From 64d8a3804ffd76bc54b426e23f61da21713e9c49 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Fri, 20 Jun 2025 14:11:42 +0200
Subject: [PATCH 10/39] target/sim/verilator: Drive clock/reset from C++

---
 target/sim/verilator/sim/main.cpp             |  89 +++++++-------
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 110 ++++++------------
 2 files changed, 81 insertions(+), 118 deletions(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index 39a0cc38..76a24e7a 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -6,6 +6,13 @@
 
 #include "Vcheshire_soc_wrapper.h" // Verilated model
 
+// clock periods and time step in pico seconds
+#define CLK_PERIOD_PS     5000
+#define RTC_PERIOD_PS 30520000
+#define TIME_STEP_PS      2500
+
+#define RST_CYCLES 5
+
 #define SIMULATION_RATE_CHUNK 1024
 
 // #define TRACE
@@ -66,7 +73,7 @@ int main(int argc, char** argv) {
     // This needs to be called before you create any model
     contextp->commandArgs(argc, argv);
 
-    // "WRAPPER" will be the hierarchical name of the module
+    // "TOP" will be the hierarchical name of the module
     const auto top = std::make_unique<Vcheshire_soc_wrapper>(contextp.get(), "TOP");
 
 #ifdef TRACE
@@ -76,58 +83,52 @@ int main(int argc, char** argv) {
     trace->open("dump.fst");
 #endif
 
-    // Set Vtop's input signals
-    // top->reset_l = !0;
-    // top->clk = 0;
-    // top->in_small = 1;
-    // top->in_quad = 0x1234;
-    // top->in_wide[0] = 0x11111111;
-    // top->in_wide[1] = 0x22222222;
-    // top->in_wide[2] = 0x3;
-
+    // Initial Inputs
+    top->clk_i  = 1;
+    top->rtc_i  = 1;
+    top->rst_ni = 0;
 
-    // Simulate until $finish
     auto start = std::chrono::high_resolution_clock::now();
     auto last = start;
     uint64_t cycle = 0;
+    uint64_t next_rtc_toggle_ps = 0;
+
+    // Simulate until $finish
     while (!contextp->gotFinish() && !do_exit) {
-        unsigned char clk_prev = top->clk_o;
-
-        contextp->timeInc(1);  // 1 timeprecision period passes...
-
-        // VL_PRINTF("toggle...\n");
-
-        // Toggle control signals on an edge that doesn't correspond
-        // to where the controls are sampled; in this example we do
-        // this only on a negedge of clk, because we know
-        // reset is not sampled there.
-        // if (!top->clk) {
-        //     if (contextp->time() > 1 && contextp->time() < 10) {
-        //         top->reset_l = !1;  // Assert reset
-        //     } else {
-        //         top->reset_l = !0;  // Deassert reset
-        //     }
-        //     // Assign some other inputs
-        //     top->in_quad += 0x12;
-        // }
+        // Toggle Clock
+        top->clk_i = !top->clk_i;
+
+        // Apply Inputs (negedge clk_i)
+        if (!top->clk_i) {
+          cycle++;
+
+          // Release Reset
+          if (cycle == RST_CYCLES)
+            top->rst_ni = 1;
+
+          // Toggle Real Time Clock
+          if (contextp->time() < next_rtc_toggle_ps) {
+            top->rtc_i = !top->rtc_i;
+            next_rtc_toggle_ps += RTC_PERIOD_PS / 2;
+          }
+
+          // JTAG I/O
+          if (top->rst_ni) {
+            jtag_tick_io(*top);
+          }
+        }
+
+        contextp->timeInc(TIME_STEP_PS);
 
         // Evaluate model
-        // (If you have multiple models being simulated in the same
-        // timestep then instead of eval(), call eval_step() on each, then
-        // eval_end_step() on each. See the manual.)
         top->eval();
 
 #ifdef TRACE
         trace->dump(contextp->time());
 #endif
 
-        if (top->rst_no && !top->clk_o && clk_prev) {
-          jtag_tick_io(*top);
-        }
-
-        if (!clk_prev && top->clk_o) {
-          // posedge clk
-          cycle++;
+        // Monitoring (posedge clk_i)
+        if (top->clk_i) {
           if (cycle % SIMULATION_RATE_CHUNK == 0) {
             auto current = std::chrono::high_resolution_clock::now();
             auto total_elapsed_us = std::chrono::duration_cast<std::chrono::microseconds>(current - start).count();
@@ -138,13 +139,9 @@ int main(int argc, char** argv) {
             VL_PRINTF("elapsed: %lu us, %.1f cycles/sec (total), %.1f cycles/sec (last)\n",
                 total_elapsed_us, total_cycles_per_sec, last_cycles_per_sec);
           }
+          if (cycle == 100000)
+            break;
         }
-
-        // // Read outputs
-        // VL_PRINTF("[%" PRId64 "] clk=%x rstl=%x iquad=%" PRIx64 " -> oquad=%" PRIx64
-        //           " owide=%x_%08x_%08x\n",
-        //           contextp->time(), top->clk, top->reset_l, top->in_quad, top->out_quad,
-        //           top->out_wide[2], top->out_wide[1], top->out_wide[0]);
     }
 
     // Final model cleanup
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 09f57fba..9c2a217e 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -4,15 +4,10 @@
 //
 // Max Wipfli <mwipfli@student.ethz.ch>
 
-module cheshire_soc_wrapper #(
-  parameter time ClkPeriodSys         = 5ns,
-  parameter time ClkPeriodRtc         = 30518ns,
-  parameter int unsigned RstClkCycles = 5,
-
-  parameter int unsigned RemoteBitbangPort = 3335
-) (
-  output logic clk_o,
-  output logic rst_no,
+module cheshire_soc_wrapper (
+  input logic clk_i,
+  input logic rtc_i,
+  input logic rst_ni,
 
   // JTAG
   input  logic jtag_tck_i,
@@ -41,9 +36,6 @@ module cheshire_soc_wrapper #(
   //  DUT  //
   ///////////
 
-  logic       clk;
-  logic       rst_n;
-
   logic       test_mode;
   logic [1:0] boot_mode;
   logic       rtc;
@@ -101,8 +93,8 @@ module cheshire_soc_wrapper #(
     .reg_ext_req_t      ( reg_req_t ),
     .reg_ext_rsp_t      ( reg_rsp_t )
   ) i_dut (
-    .clk_i              ( clk       ),
-    .rst_ni             ( rst_n     ),
+    .clk_i              ( clk_i     ),
+    .rst_ni             ( rst_ni    ),
     .test_mode_i        ( test_mode ),
     .boot_mode_i        ( boot_mode ),
     .rtc_i              ( rtc       ),
@@ -171,67 +163,41 @@ module cheshire_soc_wrapper #(
     .usb_dp_oe_o        ( )
   );
 
-  //////////////////////////////
-  //  Clock/Reset Generation  //
-  //////////////////////////////
-
-  clk_rst_gen #(
-    .ClkPeriod    ( ClkPeriodSys ),
-    .RstClkCycles ( RstClkCycles )
-  ) i_clk_rst_sys (
-    .clk_o  ( clk   ),
-    .rst_no ( rst_n )
-  );
-
-  clk_rst_gen #(
-    .ClkPeriod    ( ClkPeriodRtc ),
-    .RstClkCycles ( RstClkCycles )
-  ) i_clk_rst_rtc (
-    .clk_o  ( rtc ),
-    .rst_no ( )
-  );
-
   ////////////
   //  DRAM  //
   ////////////
 
-  axi_sim_mem #(
-    .AddrWidth          ( DutCfg.AddrWidth    ),
-    .DataWidth          ( DutCfg.AxiDataWidth ),
-    .IdWidth            ( $bits(axi_llc_id_t) ),
-    .UserWidth          ( DutCfg.AxiUserWidth ),
-    .axi_req_t          ( axi_llc_req_t ),
-    .axi_rsp_t          ( axi_llc_rsp_t ),
-    .WarnUninitialized  ( 0 ),
-    .ClearErrOnAccess   ( 1 ),
-    .ApplDelay          ( 0ps ),
-    .AcqDelay           ( 0ps )
-  ) i_dram_sim_mem (
-    .clk_i              ( clk   ),
-    .rst_ni             ( rst_n ),
-    .axi_req_i          ( axi_llc_mst_req ),
-    .axi_rsp_o          ( axi_llc_mst_rsp ),
-    .mon_w_valid_o      ( ),
-    .mon_w_addr_o       ( ),
-    .mon_w_data_o       ( ),
-    .mon_w_id_o         ( ),
-    .mon_w_user_o       ( ),
-    .mon_w_beat_count_o ( ),
-    .mon_w_last_o       ( ),
-    .mon_r_valid_o      ( ),
-    .mon_r_addr_o       ( ),
-    .mon_r_data_o       ( ),
-    .mon_r_id_o         ( ),
-    .mon_r_user_o       ( ),
-    .mon_r_beat_count_o ( ),
-    .mon_r_last_o       ( )
-  );
-
-  //////////////////
-  //  I/O to C++  //
-  //////////////////
-
-  assign clk_o = clk;
-  assign rst_no = rst_n;
+  // axi_sim_mem #(
+  //   .AddrWidth          ( DutCfg.AddrWidth    ),
+  //   .DataWidth          ( DutCfg.AxiDataWidth ),
+  //   .IdWidth            ( $bits(axi_llc_id_t) ),
+  //   .UserWidth          ( DutCfg.AxiUserWidth ),
+  //   .axi_req_t          ( axi_llc_req_t ),
+  //   .axi_rsp_t          ( axi_llc_rsp_t ),
+  //   .WarnUninitialized  ( 0 ),
+  //   .ClearErrOnAccess   ( 1 ),
+  //   .ApplDelay          ( 0ps ),
+  //   .AcqDelay           ( 0ps )
+  // ) i_dram_sim_mem (
+  //   .clk_i              ( clk_i  ),
+  //   .rst_ni             ( rst_ni ),
+  //   .axi_req_i          ( axi_llc_mst_req ),
+  //   .axi_rsp_o          ( axi_llc_mst_rsp ),
+  //   .mon_w_valid_o      ( ),
+  //   .mon_w_addr_o       ( ),
+  //   .mon_w_data_o       ( ),
+  //   .mon_w_id_o         ( ),
+  //   .mon_w_user_o       ( ),
+  //   .mon_w_beat_count_o ( ),
+  //   .mon_w_last_o       ( ),
+  //   .mon_r_valid_o      ( ),
+  //   .mon_r_addr_o       ( ),
+  //   .mon_r_data_o       ( ),
+  //   .mon_r_id_o         ( ),
+  //   .mon_r_user_o       ( ),
+  //   .mon_r_beat_count_o ( ),
+  //   .mon_r_last_o       ( )
+  // );
+  assign axi_llc_mst_rsp = '0;
 
 endmodule

From 27aba0ac4bed59c8b39ad774939d0c57ed5794f2 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Sat, 21 Jun 2025 12:47:31 +0200
Subject: [PATCH 11/39] target/sim/verilator: Clean up Makefile and
 sim/main.cpp

---
 target/sim/verilator/sim/main.cpp             | 18 ++++++----
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 10 +-----
 target/sim/verilator/verilator.mk             | 36 +++++++++++++------
 3 files changed, 38 insertions(+), 26 deletions(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index 76a24e7a..c64d12ce 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -2,7 +2,7 @@
 #include <memory> // std::unique_ptr
 
 #include <verilated.h> // common Verilator routines
-#include <verilated_fst_c.h> // trace to VCD
+#include <verilated_vcd_c.h> // trace to VCD
 
 #include "Vcheshire_soc_wrapper.h" // Verilated model
 
@@ -15,7 +15,7 @@
 
 #define SIMULATION_RATE_CHUNK 1024
 
-// #define TRACE
+// #define BENCHMARK
 
 bool do_exit = false;
 int  exit_code = 0;
@@ -76,11 +76,11 @@ int main(int argc, char** argv) {
     // "TOP" will be the hierarchical name of the module
     const auto top = std::make_unique<Vcheshire_soc_wrapper>(contextp.get(), "TOP");
 
-#ifdef TRACE
+#if CHS_TRACE_VCD
     Verilated::traceEverOn(true);
-    const auto trace = std::make_unique<VerilatedFstC>();
+    const auto trace = std::make_unique<VerilatedVcdC>();
     top->trace(trace.get(), 5);
-    trace->open("dump.fst");
+    trace->open("dump.vcd");
 #endif
 
     // Initial Inputs
@@ -107,14 +107,16 @@ int main(int argc, char** argv) {
             top->rst_ni = 1;
 
           // Toggle Real Time Clock
-          if (contextp->time() < next_rtc_toggle_ps) {
+          if (contextp->time() >= next_rtc_toggle_ps) {
             top->rtc_i = !top->rtc_i;
             next_rtc_toggle_ps += RTC_PERIOD_PS / 2;
           }
 
           // JTAG I/O
           if (top->rst_ni) {
+#ifndef BENCHMARK
             jtag_tick_io(*top);
+#endif
           }
         }
 
@@ -123,7 +125,7 @@ int main(int argc, char** argv) {
         // Evaluate model
         top->eval();
 
-#ifdef TRACE
+#if CHS_TRACE_VCD
         trace->dump(contextp->time());
 #endif
 
@@ -139,8 +141,10 @@ int main(int argc, char** argv) {
             VL_PRINTF("elapsed: %lu us, %.1f cycles/sec (total), %.1f cycles/sec (last)\n",
                 total_elapsed_us, total_cycles_per_sec, last_cycles_per_sec);
           }
+#ifdef BENCHMARK
           if (cycle == 100000)
             break;
+#endif
         }
     }
 
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 9c2a217e..4ca712d9 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -38,7 +38,6 @@ module cheshire_soc_wrapper (
 
   logic       test_mode;
   logic [1:0] boot_mode;
-  logic       rtc;
 
   assign test_mode = 1'b0;
   assign boot_mode = 2'b00; // passive
@@ -46,13 +45,6 @@ module cheshire_soc_wrapper (
   axi_llc_req_t axi_llc_mst_req;
   axi_llc_rsp_t axi_llc_mst_rsp;
 
-  logic jtag_tck;
-  logic jtag_trst_n;
-  logic jtag_tms;
-  logic jtag_tdi;
-  logic jtag_tdo;
-  logic jtag_tdo_oe;
-
   logic uart_tx;
   logic uart_rx;
 
@@ -97,7 +89,7 @@ module cheshire_soc_wrapper (
     .rst_ni             ( rst_ni    ),
     .test_mode_i        ( test_mode ),
     .boot_mode_i        ( boot_mode ),
-    .rtc_i              ( rtc       ),
+    .rtc_i              ( rtc_i     ),
     .axi_llc_mst_req_o  ( axi_llc_mst_req ),
     .axi_llc_mst_rsp_i  ( axi_llc_mst_rsp ),
     .axi_ext_mst_req_i  ( '0 ),
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 6b7529f8..0ea7ddf0 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -8,19 +8,34 @@
 CHS_VERILATOR_DIR ?= $(CHS_ROOT)/target/sim/verilator
 RISCV_DBG_DIR = $(shell bender path riscv-dbg)
 
-VERILATOR = oseda verilator
+VERILATOR_PREFIX ?= oseda
+VERILATOR        ?= verilator
 
-VERILATOR_OPT     = -march=native -mtune=native -Wno-deprecated-experimental-coroutine
 # Silly Verilator warnings: these are perfectly valid and should not be warnings
 VERILATOR_WNO   = -Wno-fatal -Wno-style \
-									-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
-VERILATOR_FIX   = --unroll-count 51 --unroll-stmts 1
-VERILATOR_ARGS  ?= -j 0 -Wall --timing -timescale 1ns/1ns $(VERILATOR_WNO) $(VERILATOR_FIX) -O3 \
-									 # --trace --trace-structs --no-trace-top --trace-depth 5
+	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
+VERILATOR_ARGS  ?= -j 0 -Wall $(VERILATOR_WNO) -timescale 1ns/1ps
+# Verilation optimizations
+VERILATOR_ARGS += -O3 --x-assign fast --x-initial fast --noassert
+# Disable common_cells assertions
+VERILATOR_ARGS += -DASSERTS_OFF
+# C++ Compiler Optimization
+
+# VERILATOR_ARGS += -CFLAGS "-march=native"
+# VERILATOR_ARGS += -CFLAGS "-mtune=native"
+# VERILATOR_ARGS += -CFLAGS "-O2"
+
+# Profiling
+# generates `gmon.out` that can be processed by `gprof` and then `verilator_profcfunc`
+# VERILATOR_ARGS += --prof-cfuncs --report-unoptflat
+
+# Tracing
+# enables VCD tracing of the topmost 5 layers
+VERILATOR_ARGS += --trace --trace-structs --no-trace-top --trace-depth 5 -CFLAGS "-DCHS_TRACE_VCD=1"
 
 VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/sim/main.cpp \
-										 $(RISCV_DBG_DIR)/tb/remote_bitbang/remote_bitbang.c \
-										 $(RISCV_DBG_DIR)/tb/remote_bitbang/sim_jtag.c
+	$(RISCV_DBG_DIR)/tb/remote_bitbang/remote_bitbang.c \
+	$(RISCV_DBG_DIR)/tb/remote_bitbang/sim_jtag.c
 
 $(CHS_VERILATOR_DIR)/cheshire_soc.flist: $(CHS_ROOT)/Bender.yml
 	$(BENDER) script verilator $(CHS_BENDER_RTL_FLAGS) > $@
@@ -28,13 +43,14 @@ $(CHS_VERILATOR_DIR)/cheshire_soc.flist: $(CHS_ROOT)/Bender.yml
 	echo '$(shell $(BENDER) path axi)/src/axi_sim_mem.sv' >> $@
 
 $(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist $(VERILATOR_CXX_SRCS)
-	+cd $(CHS_VERILATOR_DIR) && $(VERILATOR) $(VERILATOR_ARGS) -DASSERTS_OFF -f $< $(VERILATOR_CXX_SRCS) \
+	+cd $(CHS_VERILATOR_DIR) && $(VERILATOR_PREFIX) $(VERILATOR) $(VERILATOR_ARGS) \
+		-DASSERTS_OFF -f $< $(VERILATOR_CXX_SRCS) \
 		--cc --exe --build --top-module cheshire_soc_wrapper
 
 $(CHS_ROOT)/target/sim/verilator/cheshire_soc.vlt: $(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper
 	@echo "#!/bin/sh" > $@
 	@echo 'set -eu' >> $@
 	@echo 'cd $$(dirname "$$0")' >> $@
-	@echo 'oseda ./obj_dir/Vcheshire_soc_wrapper' >> $@
+	@echo '$(VERILATOR_PREFIX) ./obj_dir/Vcheshire_soc_wrapper' >> $@
 	@chmod +x $@
 

From c31c1e2ff21f7323f73be8be8ffccbd4f96aec87 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Sat, 21 Jun 2025 13:44:15 +0200
Subject: [PATCH 12/39] target/sim/verilator: Add UART receiver

---
 Bender.yml                                    |   1 +
 target/sim/verilator/sim/main.cpp             |  17 ++-
 .../sim/verilator/src/cheshire_soc_wrapper.sv |  23 +++-
 target/sim/verilator/src/verilator_uart_rx.sv | 122 ++++++++++++++++++
 target/sim/verilator/verilator.mk             |   2 +-
 5 files changed, 161 insertions(+), 4 deletions(-)
 create mode 100644 target/sim/verilator/src/verilator_uart_rx.sv

diff --git a/Bender.yml b/Bender.yml
index 00c7acce..fd5bf3f0 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -56,6 +56,7 @@ sources:
 
   - target: any(verilator)
     files:
+      - target/sim/verilator/src/verilator_uart_rx.sv
       - target/sim/verilator/src/cheshire_soc_wrapper.sv
 
   - target: all(fpga, xilinx)
diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index c64d12ce..3a186444 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -13,7 +13,7 @@
 
 #define RST_CYCLES 5
 
-#define SIMULATION_RATE_CHUNK 1024
+#define SIMULATION_RATE_CHUNK 10000
 
 // #define BENCHMARK
 
@@ -39,6 +39,15 @@ static void jtag_tick_io(Vcheshire_soc_wrapper& top) {
   top.jtag_trst_ni = trst_n;
 }
 
+static void handle_uart(char data) {
+  static std::string uart_buffer;
+  uart_buffer.push_back(data);
+
+  if (data == '\r' || data == '\n') {
+    VL_PRINTF("[UART] %s", uart_buffer.c_str());
+    uart_buffer.clear();
+  }
+}
 
 int main(int argc, char** argv) {
     // This is a more complicated example, please also see the simpler examples/make_hello_c.
@@ -131,6 +140,10 @@ int main(int argc, char** argv) {
 
         // Monitoring (posedge clk_i)
         if (top->clk_i) {
+          if (top->uart_data_valid_o) {
+            handle_uart(top->uart_data_o);
+          }
+
           if (cycle % SIMULATION_RATE_CHUNK == 0) {
             auto current = std::chrono::high_resolution_clock::now();
             auto total_elapsed_us = std::chrono::duration_cast<std::chrono::microseconds>(current - start).count();
@@ -142,7 +155,7 @@ int main(int argc, char** argv) {
                 total_elapsed_us, total_cycles_per_sec, last_cycles_per_sec);
           }
 #ifdef BENCHMARK
-          if (cycle == 100000)
+          if (cycle == 1000000)
             break;
 #endif
         }
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 4ca712d9..3fd06e64 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -15,7 +15,11 @@ module cheshire_soc_wrapper (
   input  logic jtag_tms_i,
   input  logic jtag_tdi_i,
   output logic jtag_tdo_o,
-  output logic jtag_tdo_oe_o
+  output logic jtag_tdo_oe_o,
+
+  // UART
+  output logic       uart_data_valid_o,
+  output logic [7:0] uart_data_o
 );
 
   `include "cheshire/typedef.svh"
@@ -192,4 +196,21 @@ module cheshire_soc_wrapper (
   // );
   assign axi_llc_mst_rsp = '0;
 
+  ////////////
+  //  UART  //
+  ////////////
+
+  verilator_uart_rx #(
+    .BaudPeriodCycles(1000 * 1000 * 1000 / 115200 / 5)  // 1 second / baud rate / clock period
+  ) i_uart_rx (
+    .clk_i,
+    .rst_ni,
+    .uart_rx_i    ( uart_tx           ),
+    .data_valid_o ( uart_data_valid_o ),
+    .data_o       ( uart_data_o       )
+  );
+
+  // no UART input into DUT
+  assign uart_rx = 1'b0;
+
 endmodule
diff --git a/target/sim/verilator/src/verilator_uart_rx.sv b/target/sim/verilator/src/verilator_uart_rx.sv
new file mode 100644
index 00000000..16e47633
--- /dev/null
+++ b/target/sim/verilator/src/verilator_uart_rx.sv
@@ -0,0 +1,122 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Max Wipfli <mwipfli@student.ethz.ch>
+
+`include "common_cells/registers.svh"
+
+module verilator_uart_rx #(
+  parameter  int unsigned BaudPeriodCycles = 1736,
+  localparam int unsigned DataBits         = 8
+) (
+  input logic clk_i,
+  input logic rst_ni,
+  input logic uart_rx_i,
+
+  output logic                data_valid_o,
+  output logic [DataBits-1:0] data_o
+);
+
+  localparam int unsigned CounterWidth = $clog2(BaudPeriodCycles) + 1;
+
+  logic start;
+  logic sample;
+
+  //////////////////
+  //  baud clock  //
+  //////////////////
+
+
+  logic [CounterWidth-1:0] baud_counter_q, baud_counter_d;
+  `FF(baud_counter_q, baud_counter_d, '0);
+
+  always_comb begin
+    baud_counter_d = baud_counter_q + 1'b1;
+    sample         = 1'b0;
+
+    if (start) begin
+      baud_counter_d = BaudPeriodCycles / 2;
+    end else if (baud_counter_d == BaudPeriodCycles) begin
+      baud_counter_d = '0;
+      sample         = 1'b1;
+    end
+  end
+
+  //////////////////////
+  //  shift register  //
+  //////////////////////
+
+  logic [DataBits-1:0] data_sr_q, data_sr_d;
+  `FF(data_sr_q, data_sr_d, '0);
+
+  logic data_sr_push;
+
+  always_comb begin
+    data_sr_d = data_sr_q;
+    if (data_sr_push) begin
+      data_sr_d = {uart_rx_i, data_sr_q[DataBits-1:1]};
+    end
+  end
+
+  assign data_o = data_sr_q;
+
+  /////////////////////
+  //  state machine  //
+  /////////////////////
+
+  typedef enum logic [1:0] {
+    StIdle,
+    StStartBit,
+    StDataBit,
+    StStopBit
+  } state_e;
+
+  state_e state_q, state_d;
+  `FF(state_q, state_d, StIdle);
+
+  logic [$clog2(DataBits):0] bit_counter_q, bit_counter_d;
+  `FF(bit_counter_q, bit_counter_d, '0);
+
+  always_comb begin
+    state_d       = state_q;
+    start         = 1'b0;
+    data_sr_push  = 1'b0;
+    bit_counter_d = bit_counter_q;
+    data_valid_o  = 1'b0;
+
+    unique case (state_q)
+      StIdle: begin
+        if (uart_rx_i == 1'b0) begin
+          state_d       = StStartBit;
+          start         = 1'b1;
+          bit_counter_d = 1'b0;
+        end
+      end
+      StStartBit: begin
+        if (sample) begin
+          state_d = StDataBit;
+        end
+      end
+      StDataBit: begin
+        if (sample) begin
+          data_sr_push  = 1'b1;
+          bit_counter_d = bit_counter_q + 1'b1;
+          if (bit_counter_d == DataBits) begin
+            state_d = StStopBit;
+          end
+        end
+      end
+      StStopBit: begin
+        if (sample) begin
+          state_d      = StIdle;
+          data_valid_o = 1'b1;
+        end
+      end
+      default: begin
+        state_d = StIdle;
+      end
+    endcase
+  end
+
+endmodule
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 0ea7ddf0..3f3da45b 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -31,7 +31,7 @@ VERILATOR_ARGS += -DASSERTS_OFF
 
 # Tracing
 # enables VCD tracing of the topmost 5 layers
-VERILATOR_ARGS += --trace --trace-structs --no-trace-top --trace-depth 5 -CFLAGS "-DCHS_TRACE_VCD=1"
+# VERILATOR_ARGS += --trace --trace-structs --no-trace-top --trace-depth 5 -CFLAGS "-DCHS_TRACE_VCD=1"
 
 VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/sim/main.cpp \
 	$(RISCV_DBG_DIR)/tb/remote_bitbang/remote_bitbang.c \

From 649e64c40e65034840b2426e1d91826bec32bbba Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Sat, 21 Jun 2025 13:44:59 +0200
Subject: [PATCH 13/39] target/sim/verilator: Minor C++ cleanup

---
 target/sim/verilator/sim/main.cpp | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index 3a186444..51a126c8 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -25,6 +25,13 @@ extern int jtag_tick(int port, unsigned char *jtag_TCK, unsigned char *jtag_TMS,
 
 
 static void jtag_tick_io(Vcheshire_soc_wrapper& top) {
+  static int count = 0;
+  if (count < 10) {
+    count++;
+    return;
+  }
+  count = 0;
+
   unsigned char tck, tms, tdi, trst_n;
   int ret = jtag_tick(3335, &tck, &tms, &tdi, &trst_n, top.jtag_tdo_o);
   if (ret) {
@@ -123,7 +130,7 @@ int main(int argc, char** argv) {
 
           // JTAG I/O
           if (top->rst_ni) {
-#ifndef BENCHMARK
+#if 0
             jtag_tick_io(*top);
 #endif
           }

From f021065ed68819787dc63309e0164eb4e2e63da4 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Mon, 23 Jun 2025 11:06:29 +0200
Subject: [PATCH 14/39] target/sim/verilator: Add working serial link
 preloading

---
 target/sim/src/elfloader.cpp                  |   8 +-
 target/sim/verilator/sim/Mem64Master.h        | 100 +++++++++++
 target/sim/verilator/sim/main.cpp             | 156 +++++++++++++-----
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 106 ++++++++++--
 target/sim/verilator/verilator.mk             |   4 +-
 5 files changed, 317 insertions(+), 57 deletions(-)
 create mode 100644 target/sim/verilator/sim/Mem64Master.h

diff --git a/target/sim/src/elfloader.cpp b/target/sim/src/elfloader.cpp
index b02860c9..b273f566 100644
--- a/target/sim/src/elfloader.cpp
+++ b/target/sim/src/elfloader.cpp
@@ -158,6 +158,7 @@ int section_index = 0;
 extern "C" {
   char get_entry(long long *entry_ret);
   char get_section(long long *address_ret, long long *len_ret);
+  char read_section_raw(long long address, char *buf, long long len);
   char read_section(long long address, const svOpenArrayHandle buffer, long long len);
   char read_elf(const char *filename);
 }
@@ -199,7 +200,12 @@ extern "C" char read_section(long long address, const svOpenArrayHandle buffer,
 {
   // get actual pointer
   char *buf = (char *) svGetArrayPtr(buffer);
-  
+
+  return read_section_raw(address, buf, len);
+}
+
+extern "C" char read_section_raw(long long address, char *buf, long long len)
+{
   // check that the address points to a section
   if (!mems.count(address)) {
     printf("[ELF] ERROR: No section found for address %p\n", address);
diff --git a/target/sim/verilator/sim/Mem64Master.h b/target/sim/verilator/sim/Mem64Master.h
new file mode 100644
index 00000000..1d265366
--- /dev/null
+++ b/target/sim/verilator/sim/Mem64Master.h
@@ -0,0 +1,100 @@
+// Copyright 2025 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Max Wipfli <mwipfli@student.ethz.ch>
+
+#include <cassert>
+#include <cstdint>
+#include <cstdio>
+#include <cstring>
+#include <queue>
+
+// 64-bit memory interface master (currently only supporting aligned 64-bit writes)
+class Mem64Master {
+private:
+    struct WriteTransaction {
+        uint64_t addr;
+        uint64_t data;
+    };
+
+public:
+    Mem64Master(
+        uint8_t*  mem_req_o,
+        uint64_t* mem_addr_o,
+        uint8_t*  mem_we_o,
+        uint64_t* mem_wdata_o,
+        uint8_t*  mem_be_o,
+        uint8_t*  mem_gnt_i
+    ) : m_mem_req_o(mem_req_o)
+      , m_mem_addr_o(mem_addr_o)
+      , m_mem_we_o(mem_we_o)
+      , m_mem_wdata_o(mem_wdata_o)
+      , m_mem_be_o(mem_be_o)
+      , m_mem_gnt_i(mem_gnt_i) {
+        // zero all outputs
+        *m_mem_req_o = 0;
+        *m_mem_addr_o = 0;
+        *m_mem_we_o = 0;
+        *m_mem_wdata_o = 0;
+        *m_mem_be_o = 0;
+    }
+
+    void write(uint64_t addr, uint64_t data) {
+        m_write_queue.push({ addr, data });
+    }
+
+    void write_chunk(uint64_t addr, void *data, size_t bytes) {
+        assert(addr % sizeof(uint64_t) == 0 && "unaligned writes not yet supported");
+        assert(bytes % sizeof(uint64_t) == 0 && "unaligned write size not yet supported");
+
+        for (size_t i = 0; i < bytes; i += sizeof(uint64_t)) {
+            uint64_t word;
+            memcpy(&word, (char *)data + i, sizeof(uint64_t));
+            write(addr + i, word);
+        }
+    }
+
+    // handle before @(posedge clk): reads signals, does not modify signals
+    void handle_before() {
+        m_handshake = (*m_mem_req_o && *m_mem_gnt_i);
+    }
+
+    // handle before @(posedge clk): modifies signals for next cycle
+    void handle_after() {
+        if (m_handshake) {
+            // current request was handled
+            m_handshake = false;
+            *m_mem_req_o = 0;
+        }
+
+        if (!*m_mem_req_o && !m_write_queue.empty()) {
+            // apply new request
+            const auto& transaction = m_write_queue.front();
+            *m_mem_req_o   = 1;
+            *m_mem_addr_o  = transaction.addr;
+            *m_mem_we_o    = 1;
+            *m_mem_wdata_o = transaction.data;
+            *m_mem_be_o    = 0xff;
+            m_write_queue.pop();
+            if (m_write_queue.empty()) {
+                printf("Mem64Master: emptied write queue\n");
+            }
+        }
+    }
+
+private:
+    // holds pairs of (addr, data)
+    std::queue<WriteTransaction> m_write_queue;
+
+    // handshake detected
+    bool m_handshake;
+
+    // interface
+    uint8_t*  m_mem_req_o;
+    uint64_t* m_mem_addr_o;
+    uint8_t*  m_mem_we_o;
+    uint64_t* m_mem_wdata_o;
+    uint8_t*  m_mem_be_o;
+    uint8_t*  m_mem_gnt_i;
+};
diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index 51a126c8..ea296ca0 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -2,10 +2,14 @@
 #include <memory> // std::unique_ptr
 
 #include <verilated.h> // common Verilator routines
+#if VM_TRACE
 #include <verilated_vcd_c.h> // trace to VCD
+#endif
 
 #include "Vcheshire_soc_wrapper.h" // Verilated model
 
+#include "Mem64Master.h"
+
 // clock periods and time step in pico seconds
 #define CLK_PERIOD_PS     5000
 #define RTC_PERIOD_PS 30520000
@@ -17,6 +21,16 @@
 
 // #define BENCHMARK
 
+extern "C" {
+  char get_entry(long long *entry_ret);
+  char get_section(long long *address_ret, long long *len_ret);
+  char read_section_raw(long long address, char *buf, long long len);
+  char read_elf(const char *filename);
+}
+
+std::unique_ptr<VerilatedContext> contextp;
+std::unique_ptr<Vcheshire_soc_wrapper> topp;
+std::unique_ptr<Mem64Master> mem_master;
 bool do_exit = false;
 int  exit_code = 0;
 
@@ -24,7 +38,7 @@ extern int jtag_tick(int port, unsigned char *jtag_TCK, unsigned char *jtag_TMS,
     unsigned char *jtag_TDI, unsigned char *jtag_TRSTn, unsigned char jtag_TDO);
 
 
-static void jtag_tick_io(Vcheshire_soc_wrapper& top) {
+static void jtag_tick_io() {
   static int count = 0;
   if (count < 10) {
     count++;
@@ -33,46 +47,74 @@ static void jtag_tick_io(Vcheshire_soc_wrapper& top) {
   count = 0;
 
   unsigned char tck, tms, tdi, trst_n;
-  int ret = jtag_tick(3335, &tck, &tms, &tdi, &trst_n, top.jtag_tdo_o);
+  int ret = jtag_tick(3335, &tck, &tms, &tdi, &trst_n, topp->jtag_tdo_o);
   if (ret) {
     do_exit = true;
     exit_code = ret >> 1;
     return;
   }
 
-  top.jtag_tck_i   = tck;
-  top.jtag_tms_i   = tms;
-  top.jtag_tdi_i   = tdi;
-  top.jtag_trst_ni = trst_n;
+  topp->jtag_tck_i   = tck;
+  topp->jtag_tms_i   = tms;
+  topp->jtag_tdi_i   = tdi;
+  topp->jtag_trst_ni = trst_n;
 }
 
 static void handle_uart(char data) {
   static std::string uart_buffer;
   uart_buffer.push_back(data);
 
-  if (data == '\r' || data == '\n') {
+  if (data == '\n') {
     VL_PRINTF("[UART] %s", uart_buffer.c_str());
     uart_buffer.clear();
   }
 }
 
-int main(int argc, char** argv) {
-    // This is a more complicated example, please also see the simpler examples/make_hello_c.
+static bool elf_preload_open(const char *filename) {
+    char ret = read_elf(filename);
+    if (ret != 0) {
+        VL_PRINTF("[ELF] failed to read ELF: %d\n", ret);
+        return false;
+    }
+    return true;
+}
+
+static void elf_preload_write_enqueue() {
+    long long section_address, section_len;
+    size_t num_writes = 0;
+
+    while (get_section(&section_address, &section_len)) {
+        VL_PRINTF("[ELF] loading section at 0x%llx (%lld bytes)\n", section_address, section_len);
+
+        char *buf = (char *)calloc(section_len + sizeof(uint64_t), 1);
+        read_section_raw(section_address, buf, section_len);
+
+        for (size_t i = 0; i < section_len; i += sizeof(uint64_t)) {
+            mem_master->write(section_address + i, *(uint64_t *)(buf + i));
+            num_writes++;
+        }
+
+        free(buf);
+    }
+
+    long long entry;
+    get_entry(&entry);
+    // write entrypoint
+    mem_master->write(0x03000000, entry);
+    num_writes++;
+    // set start bit (read by boot ROM)
+    mem_master->write(0x03000008, 2);
+    num_writes++;
 
+    VL_PRINTF("[ELF] enqueued %zu memory writes\n", num_writes);
+}
+
+int main(int argc, char** argv) {
     // Create logs/ directory in case we have traces to put under it
     Verilated::mkdir("logs");
 
     // Construct a VerilatedContext to hold simulation time, etc.
-    // Multiple modules (made later below with Vtop) may share the same
-    // context to share time, or modules may have different contexts if
-    // they should be independent from each other.
-
-    // Using unique_ptr is similar to
-    // "VerilatedContext* contextp = new VerilatedContext" then deleting at end.
-    const auto contextp = std::make_unique<VerilatedContext>();
-    // const std::unique_ptr<VerilatedContext> contextp{new VerilatedContext};
-    // Do not instead make Vtop as a file-scope static variable, as the
-    // "C++ static initialization order fiasco" may cause a crash
+    contextp = std::make_unique<VerilatedContext>();
 
     // Set debug level, 0 is off, 9 is highest presently used
     // May be overridden by commandArgs argument parsing
@@ -90,65 +132,99 @@ int main(int argc, char** argv) {
     contextp->commandArgs(argc, argv);
 
     // "TOP" will be the hierarchical name of the module
-    const auto top = std::make_unique<Vcheshire_soc_wrapper>(contextp.get(), "TOP");
+    topp = std::make_unique<Vcheshire_soc_wrapper>(contextp.get(), "TOP");
 
-#if CHS_TRACE_VCD
+#if VM_TRACE
     Verilated::traceEverOn(true);
     const auto trace = std::make_unique<VerilatedVcdC>();
-    top->trace(trace.get(), 5);
+    topp->trace(trace.get(), 5);
     trace->open("dump.vcd");
 #endif
 
     // Initial Inputs
-    top->clk_i  = 1;
-    top->rtc_i  = 1;
-    top->rst_ni = 0;
+    topp->clk_i  = 1;
+    topp->rtc_i  = 1;
+    topp->rst_ni = 1;
 
     auto start = std::chrono::high_resolution_clock::now();
     auto last = start;
     uint64_t cycle = 0;
     uint64_t next_rtc_toggle_ps = 0;
 
+    mem_master = std::make_unique<Mem64Master>(
+        &topp->slink_mem_req_i,
+        &topp->slink_mem_addr_i,
+        &topp->slink_mem_we_i,
+        &topp->slink_mem_wdata_i,
+        &topp->slink_mem_be_i,
+        &topp->slink_mem_gnt_o
+    );
+
+    // ELF preloading
+    const char *filename = "../../../sw/tests/helloworld.spm.elf";
+    if (!elf_preload_open(filename))
+      return 1;
+
     // Simulate until $finish
     while (!contextp->gotFinish() && !do_exit) {
         // Toggle Clock
-        top->clk_i = !top->clk_i;
+        topp->clk_i = !topp->clk_i;
 
         // Apply Inputs (negedge clk_i)
-        if (!top->clk_i) {
-          cycle++;
+        if (!topp->clk_i) {
+          // Apply Reset
+          if (cycle == 1)
+            topp->rst_ni = 0;
 
           // Release Reset
-          if (cycle == RST_CYCLES)
-            top->rst_ni = 1;
+          if (cycle == RST_CYCLES + 1)
+            topp->rst_ni = 1;
 
           // Toggle Real Time Clock
           if (contextp->time() >= next_rtc_toggle_ps) {
-            top->rtc_i = !top->rtc_i;
+            topp->rtc_i = !topp->rtc_i;
             next_rtc_toggle_ps += RTC_PERIOD_PS / 2;
           }
 
-          // JTAG I/O
-          if (top->rst_ni) {
+          // TODO: This is determined experimentally.
+          // We should rather poll until the SPM has been configured properly.
+          if (cycle == 2000)
+            elf_preload_write_enqueue();
+
+          // I/O
+          if (cycle > RST_CYCLES && topp->rst_ni) {
 #if 0
-            jtag_tick_io(*top);
+            jtag_tick_io();
 #endif
           }
         }
 
+
         contextp->timeInc(TIME_STEP_PS);
 
+        // Monitor Synchronous Outputs: just before @(posedge clk_i)
+        if (topp->clk_i) {
+          mem_master->handle_before();
+        }
+
         // Evaluate model
-        top->eval();
+        topp->eval();
 
-#if CHS_TRACE_VCD
+        // Apply Synchronous Inputs: just after @(posedge clk_i)
+        if (topp->clk_i) {
+          mem_master->handle_after();
+        }
+
+#if VM_TRACE
         trace->dump(contextp->time());
 #endif
 
         // Monitoring (posedge clk_i)
-        if (top->clk_i) {
-          if (top->uart_data_valid_o) {
-            handle_uart(top->uart_data_o);
+        if (topp->clk_i) {
+          cycle++;
+
+          if (topp->uart_data_valid_o) {
+            handle_uart(topp->uart_data_o);
           }
 
           if (cycle % SIMULATION_RATE_CHUNK == 0) {
@@ -169,7 +245,7 @@ int main(int argc, char** argv) {
     }
 
     // Final model cleanup
-    top->final();
+    topp->final();
 
 #ifdef TRACE
       trace->close();
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 3fd06e64..7800d1cf 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -4,7 +4,14 @@
 //
 // Max Wipfli <mwipfli@student.ethz.ch>
 
-module cheshire_soc_wrapper (
+function automatic cheshire_pkg::cheshire_cfg_t gen_cheshire_cfg();
+  cheshire_pkg::cheshire_cfg_t ret = cheshire_pkg::DefaultCfg;
+  return ret;
+endfunction
+
+module cheshire_soc_wrapper # (
+  parameter cheshire_pkg::cheshire_cfg_t DutCfg = gen_cheshire_cfg()
+) (
   input logic clk_i,
   input logic rtc_i,
   input logic rst_ni,
@@ -19,21 +26,20 @@ module cheshire_soc_wrapper (
 
   // UART
   output logic       uart_data_valid_o,
-  output logic [7:0] uart_data_o
-);
+  output logic [7:0] uart_data_o,
 
-  `include "cheshire/typedef.svh"
+  // Memory Interface (Serial Link)
+  input  logic                             slink_mem_req_i,
+  input  logic [DutCfg.AddrWidth-1:0]      slink_mem_addr_i,
+  input  logic                             slink_mem_we_i,
+  input  logic [DutCfg.AxiDataWidth-1:0]   slink_mem_wdata_i,
+  input  logic [DutCfg.AxiDataWidth/8-1:0] slink_mem_be_i,
+  output logic                             slink_mem_gnt_o
+);
 
   import cheshire_pkg::*;
 
-  function automatic cheshire_pkg::cheshire_cfg_t gen_cheshire_cfg();
-    cheshire_pkg::cheshire_cfg_t ret = cheshire_pkg::DefaultCfg;
-    ret.SerialLink = 1'b0;
-    return ret;
-  endfunction
-
-  localparam cheshire_cfg_t DutCfg = gen_cheshire_cfg();
-
+  `include "cheshire/typedef.svh"
   `CHESHIRE_TYPEDEF_ALL(, DutCfg)
 
   ///////////
@@ -74,8 +80,6 @@ module cheshire_soc_wrapper (
   logic [SlinkNumChan-1:0]                    slink_rcv_clk_o;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_i;
   logic [SlinkNumChan-1:0][SlinkNumLanes-1:0] slink_o;
-  assign slink_rcv_clk_i = '1;
-  assign slink_i         = '1;
 
   cheshire_soc #(
     .Cfg                ( DutCfg ),
@@ -213,4 +217,78 @@ module cheshire_soc_wrapper (
   // no UART input into DUT
   assign uart_rx = 1'b0;
 
+  ///////////////////
+  //  Serial Link  //
+  ///////////////////
+
+  axi_mst_req_t slink_axi_mst_req;
+  axi_mst_rsp_t slink_axi_mst_rsp;
+
+  // Mirror instance of serial link, reflecting another chip
+  serial_link #(
+    .axi_req_t    ( axi_mst_req_t ),
+    .axi_rsp_t    ( axi_mst_rsp_t ),
+    .cfg_req_t    ( reg_req_t ),
+    .cfg_rsp_t    ( reg_rsp_t ),
+    .aw_chan_t    ( axi_mst_aw_chan_t ),
+    .ar_chan_t    ( axi_mst_ar_chan_t ),
+    .r_chan_t     ( axi_mst_r_chan_t  ),
+    .w_chan_t     ( axi_mst_w_chan_t  ),
+    .b_chan_t     ( axi_mst_b_chan_t  ),
+    .hw2reg_t     ( serial_link_single_channel_reg_pkg::serial_link_single_channel_hw2reg_t ),
+    .reg2hw_t     ( serial_link_single_channel_reg_pkg::serial_link_single_channel_reg2hw_t ),
+    .NumChannels  ( SlinkNumChan   ),
+    .NumLanes     ( SlinkNumLanes  ),
+    .MaxClkDiv    ( SlinkMaxClkDiv )
+  ) i_serial_link (
+    .clk_i          ( clk_i  ),
+    .rst_ni         ( rst_ni ),
+    .clk_sl_i       ( clk_i  ),
+    .rst_sl_ni      ( rst_ni ),
+    .clk_reg_i      ( clk_i  ),
+    .rst_reg_ni     ( rst_ni ),
+    .testmode_i     ( test_mode ),
+    .axi_in_req_i   ( slink_axi_mst_req ),
+    .axi_in_rsp_o   ( slink_axi_mst_rsp ),
+    .axi_out_req_o  (    ),
+    .axi_out_rsp_i  ( '0 ),
+    .cfg_req_i      ( '0 ),
+    .cfg_rsp_o      (    ),
+    .ddr_rcv_clk_i  ( slink_rcv_clk_o ),
+    .ddr_rcv_clk_o  ( slink_rcv_clk_i ),
+    .ddr_i          ( slink_o ),
+    .ddr_o          ( slink_i ),
+    .isolated_i     ( '0 ),
+    .isolate_o      ( ),
+    .clk_ena_o      ( ),
+    .reset_no       ( )
+  );
+
+  // Adapter to memory interface for easier C++ handling
+  axi_from_mem #(
+    .MemAddrWidth ( DutCfg.AddrWidth    ),
+    .AxiAddrWidth ( DutCfg.AddrWidth    ),
+    .DataWidth    ( DutCfg.AxiDataWidth ),
+    .MaxRequests  ( 8                   ),
+    .AxiProt      ( 3'b000              ),
+    .axi_req_t    ( axi_mst_req_t       ),
+    .axi_rsp_t    ( axi_mst_rsp_t       )
+  ) i_serial_link_mem (
+    .clk_i,
+    .rst_ni,
+    .mem_req_i       ( slink_mem_req_i   ),
+    .mem_addr_i      ( slink_mem_addr_i  ),
+    .mem_we_i        ( slink_mem_we_i    ),
+    .mem_wdata_i     ( slink_mem_wdata_i ),
+    .mem_be_i        ( slink_mem_be_i    ),
+    .mem_gnt_o       ( slink_mem_gnt_o   ),
+    .mem_rsp_valid_o (                   ),
+    .mem_rsp_rdata_o (                   ),
+    .mem_rsp_error_o (                   ),
+    .slv_aw_cache_i  ( 4'b0000           ),
+    .slv_ar_cache_i  ( 4'b0000           ),
+    .axi_req_o       ( slink_axi_mst_req ),
+    .axi_rsp_i       ( slink_axi_mst_rsp )
+  );
+
 endmodule
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 3f3da45b..1d65cf9d 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -20,7 +20,6 @@ VERILATOR_ARGS += -O3 --x-assign fast --x-initial fast --noassert
 # Disable common_cells assertions
 VERILATOR_ARGS += -DASSERTS_OFF
 # C++ Compiler Optimization
-
 # VERILATOR_ARGS += -CFLAGS "-march=native"
 # VERILATOR_ARGS += -CFLAGS "-mtune=native"
 # VERILATOR_ARGS += -CFLAGS "-O2"
@@ -31,9 +30,10 @@ VERILATOR_ARGS += -DASSERTS_OFF
 
 # Tracing
 # enables VCD tracing of the topmost 5 layers
-# VERILATOR_ARGS += --trace --trace-structs --no-trace-top --trace-depth 5 -CFLAGS "-DCHS_TRACE_VCD=1"
+# VERILATOR_ARGS += --trace --trace-structs --no-trace-top --trace-depth 5
 
 VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/sim/main.cpp \
+	$(CHS_ROOT)/target/sim/src/elfloader.cpp \
 	$(RISCV_DBG_DIR)/tb/remote_bitbang/remote_bitbang.c \
 	$(RISCV_DBG_DIR)/tb/remote_bitbang/sim_jtag.c
 

From 3297a5d99eaf4f654c098b09dec3be269aca1d36 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Mon, 23 Jun 2025 12:58:14 +0200
Subject: [PATCH 15/39] target/sim/verilator: Improve reset handling

---
 target/sim/verilator/sim/main.cpp | 26 ++++++++++++++++----------
 1 file changed, 16 insertions(+), 10 deletions(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index ea296ca0..eb2b4767 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -124,8 +124,10 @@ int main(int argc, char** argv) {
     // May be overridden by commandArgs argument parsing
     contextp->randReset(2);
 
+#if VM_TRACE
     // Verilator must compute traced signals
     contextp->traceEverOn(true);
+#endif
 
     // Pass arguments so Verilated code can see them, e.g. $value$plusargs
     // This needs to be called before you create any model
@@ -150,6 +152,7 @@ int main(int argc, char** argv) {
     auto last = start;
     uint64_t cycle = 0;
     uint64_t next_rtc_toggle_ps = 0;
+    bool reset_done = false;
 
     mem_master = std::make_unique<Mem64Master>(
         &topp->slink_mem_req_i,
@@ -172,13 +175,16 @@ int main(int argc, char** argv) {
 
         // Apply Inputs (negedge clk_i)
         if (!topp->clk_i) {
-          // Apply Reset
-          if (cycle == 1)
+          if (cycle == 1) {
+            // Apply Reset
             topp->rst_ni = 0;
+          }
 
-          // Release Reset
-          if (cycle == RST_CYCLES + 1)
+          if (cycle == RST_CYCLES + 1) {
+            // Release Reset
             topp->rst_ni = 1;
+            reset_done = true;
+          }
 
           // Toggle Real Time Clock
           if (contextp->time() >= next_rtc_toggle_ps) {
@@ -192,7 +198,7 @@ int main(int argc, char** argv) {
             elf_preload_write_enqueue();
 
           // I/O
-          if (cycle > RST_CYCLES && topp->rst_ni) {
+          if (reset_done) {
 #if 0
             jtag_tick_io();
 #endif
@@ -203,7 +209,7 @@ int main(int argc, char** argv) {
         contextp->timeInc(TIME_STEP_PS);
 
         // Monitor Synchronous Outputs: just before @(posedge clk_i)
-        if (topp->clk_i) {
+        if (reset_done && topp->clk_i) {
           mem_master->handle_before();
         }
 
@@ -211,7 +217,7 @@ int main(int argc, char** argv) {
         topp->eval();
 
         // Apply Synchronous Inputs: just after @(posedge clk_i)
-        if (topp->clk_i) {
+        if (reset_done && topp->clk_i) {
           mem_master->handle_after();
         }
 
@@ -234,8 +240,8 @@ int main(int argc, char** argv) {
             last = current;
             auto total_cycles_per_sec = 1000000.0 * cycle / total_elapsed_us;
             auto last_cycles_per_sec = 1000000.0 * SIMULATION_RATE_CHUNK / last_elapsed_us;
-            VL_PRINTF("elapsed: %lu us, %.1f cycles/sec (total), %.1f cycles/sec (last)\n",
-                total_elapsed_us, total_cycles_per_sec, last_cycles_per_sec);
+            VL_PRINTF("elapsed: %lu us, %lu cycles, %.1f cycles/sec (total), %.1f cycles/sec (last)\n",
+                total_elapsed_us, cycle, total_cycles_per_sec, last_cycles_per_sec);
           }
 #ifdef BENCHMARK
           if (cycle == 1000000)
@@ -247,7 +253,7 @@ int main(int argc, char** argv) {
     // Final model cleanup
     topp->final();
 
-#ifdef TRACE
+#if VM_TRACE
       trace->close();
 #endif
 

From ea56ba4089d04f751abd7af1180d050389453c9d Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Mon, 7 Jul 2025 12:23:47 +0200
Subject: [PATCH 16/39] target/sim/verilator: Modify status print

---
 target/sim/verilator/sim/main.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index eb2b4767..60048f7f 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -240,8 +240,8 @@ int main(int argc, char** argv) {
             last = current;
             auto total_cycles_per_sec = 1000000.0 * cycle / total_elapsed_us;
             auto last_cycles_per_sec = 1000000.0 * SIMULATION_RATE_CHUNK / last_elapsed_us;
-            VL_PRINTF("elapsed: %lu us, %lu cycles, %.1f cycles/sec (total), %.1f cycles/sec (last)\n",
-                total_elapsed_us, cycle, total_cycles_per_sec, last_cycles_per_sec);
+            VL_PRINTF("elapsed: %.3f sec, %lu cycles, %.1f cycles/sec (total), %.1f cycles/sec (last)\n",
+                total_elapsed_us / 1e6, cycle, total_cycles_per_sec, last_cycles_per_sec);
           }
 #ifdef BENCHMARK
           if (cycle == 1000000)

From 73804873bab7644817d72f559613d60c0c1ed3e3 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Mon, 7 Jul 2025 12:23:58 +0200
Subject: [PATCH 17/39] target/sim/verilator: Enable multi-threading

---
 target/sim/verilator/verilator.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 1d65cf9d..4a6cedc4 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -19,6 +19,8 @@ VERILATOR_ARGS  ?= -j 0 -Wall $(VERILATOR_WNO) -timescale 1ns/1ps
 VERILATOR_ARGS += -O3 --x-assign fast --x-initial fast --noassert
 # Disable common_cells assertions
 VERILATOR_ARGS += -DASSERTS_OFF
+# multithreading
+VERILATOR_ARGS += --threads 12
 # C++ Compiler Optimization
 # VERILATOR_ARGS += -CFLAGS "-march=native"
 # VERILATOR_ARGS += -CFLAGS "-mtune=native"

From ae5b05a630b630e3e3868209efc45fac3430e6a6 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Mon, 7 Jul 2025 13:23:32 +0200
Subject: [PATCH 18/39] target/sim/verilator: Add support for SW exit codes via
 DDR link

---
 target/sim/verilator/sim/Mem64Master.h        | 91 ++++++++++++++++---
 target/sim/verilator/sim/main.cpp             | 33 ++++++-
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 30 +++---
 3 files changed, 126 insertions(+), 28 deletions(-)

diff --git a/target/sim/verilator/sim/Mem64Master.h b/target/sim/verilator/sim/Mem64Master.h
index 1d265366..c219e242 100644
--- a/target/sim/verilator/sim/Mem64Master.h
+++ b/target/sim/verilator/sim/Mem64Master.h
@@ -8,12 +8,28 @@
 #include <cstdint>
 #include <cstdio>
 #include <cstring>
+#include <optional>
 #include <queue>
 
 // 64-bit memory interface master (currently only supporting aligned 64-bit writes)
 class Mem64Master {
 private:
-    struct WriteTransaction {
+    struct WriteRequest {
+        uint64_t addr;
+        uint64_t data;
+    };
+
+    struct ReadRequest {
+        uint64_t addr;
+    };
+
+    struct InflightRequest {
+        uint64_t addr;
+        bool     is_write;
+    };
+
+public:
+    struct ReadResponse {
         uint64_t addr;
         uint64_t data;
     };
@@ -25,13 +41,17 @@ class Mem64Master {
         uint8_t*  mem_we_o,
         uint64_t* mem_wdata_o,
         uint8_t*  mem_be_o,
-        uint8_t*  mem_gnt_i
+        uint8_t*  mem_gnt_i,
+        uint8_t*  mem_rsp_valid_i,
+        uint64_t* mem_rsp_rdata_i
     ) : m_mem_req_o(mem_req_o)
       , m_mem_addr_o(mem_addr_o)
       , m_mem_we_o(mem_we_o)
       , m_mem_wdata_o(mem_wdata_o)
       , m_mem_be_o(mem_be_o)
-      , m_mem_gnt_i(mem_gnt_i) {
+      , m_mem_gnt_i(mem_gnt_i)
+      , m_mem_rsp_valid_i(mem_rsp_valid_i)
+      , m_mem_rsp_rdata_i(mem_rsp_rdata_i) {
         // zero all outputs
         *m_mem_req_o = 0;
         *m_mem_addr_o = 0;
@@ -41,7 +61,7 @@ class Mem64Master {
     }
 
     void write(uint64_t addr, uint64_t data) {
-        m_write_queue.push({ addr, data });
+        m_write_request_queue.push({ addr, data });
     }
 
     void write_chunk(uint64_t addr, void *data, size_t bytes) {
@@ -55,9 +75,34 @@ class Mem64Master {
         }
     }
 
+    void read(uint64_t addr) {
+        m_read_request_queue.push({ addr });
+    }
+
+    std::optional<ReadResponse> get_read_response() {
+        if (m_read_response_queue.empty())
+          return {};
+        auto response = m_read_response_queue.front();
+        m_read_response_queue.pop();
+        return response;
+    }
+
     // handle before @(posedge clk): reads signals, does not modify signals
     void handle_before() {
+        // request channel
         m_handshake = (*m_mem_req_o && *m_mem_gnt_i);
+
+        // response channel
+        if (*m_mem_rsp_valid_i) {
+          const auto& request = m_inflight_request_queue.front();
+          if (request.is_write) {
+            // no response needed
+          } else {
+             // push to read repsonse queue (now including response data)
+             m_read_response_queue.push({ request.addr, *m_mem_rsp_rdata_i });
+          }
+          m_inflight_request_queue.pop();
+        }
     }
 
     // handle before @(posedge clk): modifies signals for next cycle
@@ -68,24 +113,42 @@ class Mem64Master {
             *m_mem_req_o = 0;
         }
 
-        if (!*m_mem_req_o && !m_write_queue.empty()) {
-            // apply new request
-            const auto& transaction = m_write_queue.front();
+        if (!*m_mem_req_o && !m_write_request_queue.empty()) {
+            // apply new write request
+            const auto& request = m_write_request_queue.front();
             *m_mem_req_o   = 1;
-            *m_mem_addr_o  = transaction.addr;
+            *m_mem_addr_o  = request.addr;
             *m_mem_we_o    = 1;
-            *m_mem_wdata_o = transaction.data;
+            *m_mem_wdata_o = request.data;
             *m_mem_be_o    = 0xff;
-            m_write_queue.pop();
-            if (m_write_queue.empty()) {
+
+            m_inflight_request_queue.push({ request.addr, true });
+            m_write_request_queue.pop();
+
+            if (m_write_request_queue.empty()) {
                 printf("Mem64Master: emptied write queue\n");
             }
         }
+
+        if (!*m_mem_req_o && !m_read_request_queue.empty()) {
+            // apply new read request
+            const auto& request = m_read_request_queue.front();
+            *m_mem_req_o   = 1;
+            *m_mem_addr_o  = request.addr;
+            *m_mem_we_o    = 0;
+            *m_mem_wdata_o = 0;
+            *m_mem_be_o    = 0xff;
+
+            m_inflight_request_queue.push({ request.addr, false });
+            m_read_request_queue.pop();
+        }
     }
 
 private:
-    // holds pairs of (addr, data)
-    std::queue<WriteTransaction> m_write_queue;
+    std::queue<WriteRequest> m_write_request_queue;
+    std::queue<ReadRequest> m_read_request_queue;
+    std::queue<InflightRequest> m_inflight_request_queue;
+    std::queue<ReadResponse> m_read_response_queue;
 
     // handshake detected
     bool m_handshake;
@@ -97,4 +160,6 @@ class Mem64Master {
     uint64_t* m_mem_wdata_o;
     uint8_t*  m_mem_be_o;
     uint8_t*  m_mem_gnt_i;
+    uint8_t*  m_mem_rsp_valid_i;
+    uint64_t* m_mem_rsp_rdata_i;
 };
diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index 60048f7f..c46c10eb 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -109,6 +109,34 @@ static void elf_preload_write_enqueue() {
     VL_PRINTF("[ELF] enqueued %zu memory writes\n", num_writes);
 }
 
+static void poll_for_exit() {
+    static bool request_inflight = false;
+    static uint64_t idle_cycles = 0;
+
+    if (request_inflight) {
+      auto maybe_response = mem_master->get_read_response();
+      if (maybe_response) {
+        auto data = maybe_response->data;
+
+        request_inflight = false;
+        idle_cycles = 0;
+        if (data & 0x1) {
+          do_exit = true;
+          exit_code = data >> 1;
+          VL_PRINTF("[EXIT] received exit code from software: %d\n", exit_code);
+        }
+      }
+    } else {
+      idle_cycles++;
+
+      if (idle_cycles >= 1000) {
+        mem_master->read(0x03000008);
+        request_inflight = true;
+      }
+    }
+
+}
+
 int main(int argc, char** argv) {
     // Create logs/ directory in case we have traces to put under it
     Verilated::mkdir("logs");
@@ -160,7 +188,9 @@ int main(int argc, char** argv) {
         &topp->slink_mem_we_i,
         &topp->slink_mem_wdata_i,
         &topp->slink_mem_be_i,
-        &topp->slink_mem_gnt_o
+        &topp->slink_mem_gnt_o,
+        &topp->slink_mem_rsp_valid_o,
+        &topp->slink_mem_rsp_rdata_o
     );
 
     // ELF preloading
@@ -199,6 +229,7 @@ int main(int argc, char** argv) {
 
           // I/O
           if (reset_done) {
+            poll_for_exit();
 #if 0
             jtag_tick_io();
 #endif
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 7800d1cf..a07736d1 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -34,7 +34,9 @@ module cheshire_soc_wrapper # (
   input  logic                             slink_mem_we_i,
   input  logic [DutCfg.AxiDataWidth-1:0]   slink_mem_wdata_i,
   input  logic [DutCfg.AxiDataWidth/8-1:0] slink_mem_be_i,
-  output logic                             slink_mem_gnt_o
+  output logic                             slink_mem_gnt_o,
+  output logic                             slink_mem_rsp_valid_o,
+  output logic [DutCfg.AxiDataWidth-1:0]   slink_mem_rsp_rdata_o
 );
 
   import cheshire_pkg::*;
@@ -276,19 +278,19 @@ module cheshire_soc_wrapper # (
   ) i_serial_link_mem (
     .clk_i,
     .rst_ni,
-    .mem_req_i       ( slink_mem_req_i   ),
-    .mem_addr_i      ( slink_mem_addr_i  ),
-    .mem_we_i        ( slink_mem_we_i    ),
-    .mem_wdata_i     ( slink_mem_wdata_i ),
-    .mem_be_i        ( slink_mem_be_i    ),
-    .mem_gnt_o       ( slink_mem_gnt_o   ),
-    .mem_rsp_valid_o (                   ),
-    .mem_rsp_rdata_o (                   ),
-    .mem_rsp_error_o (                   ),
-    .slv_aw_cache_i  ( 4'b0000           ),
-    .slv_ar_cache_i  ( 4'b0000           ),
-    .axi_req_o       ( slink_axi_mst_req ),
-    .axi_rsp_i       ( slink_axi_mst_rsp )
+    .mem_req_i       ( slink_mem_req_i       ),
+    .mem_addr_i      ( slink_mem_addr_i      ),
+    .mem_we_i        ( slink_mem_we_i        ),
+    .mem_wdata_i     ( slink_mem_wdata_i     ),
+    .mem_be_i        ( slink_mem_be_i        ),
+    .mem_gnt_o       ( slink_mem_gnt_o       ),
+    .mem_rsp_valid_o ( slink_mem_rsp_valid_o ),
+    .mem_rsp_rdata_o ( slink_mem_rsp_rdata_o ),
+    .mem_rsp_error_o (                       ),
+    .slv_aw_cache_i  ( 4'b0000               ),
+    .slv_ar_cache_i  ( 4'b0000               ),
+    .axi_req_o       ( slink_axi_mst_req     ),
+    .axi_rsp_i       ( slink_axi_mst_rsp     )
   );
 
 endmodule

From 8a7f04b6b7973ad5b415271a39bf27ce1d62e72b Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 8 Jul 2025 10:15:10 +0200
Subject: [PATCH 19/39] target/sim/verilator: Use 8 threads, more C
 optimizations

---
 target/sim/verilator/verilator.mk | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 4a6cedc4..3d7adce5 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -20,11 +20,9 @@ VERILATOR_ARGS += -O3 --x-assign fast --x-initial fast --noassert
 # Disable common_cells assertions
 VERILATOR_ARGS += -DASSERTS_OFF
 # multithreading
-VERILATOR_ARGS += --threads 12
+VERILATOR_ARGS += --threads 8
 # C++ Compiler Optimization
-# VERILATOR_ARGS += -CFLAGS "-march=native"
-# VERILATOR_ARGS += -CFLAGS "-mtune=native"
-# VERILATOR_ARGS += -CFLAGS "-O2"
+VERILATOR_ARGS += -CFLAGS "-O3" -CFLAGS "-march=native" -CFLAGS "-mtune=native"
 
 # Profiling
 # generates `gmon.out` that can be processed by `gprof` and then `verilator_profcfunc`

From eeb4324a4687b95fe0dbb7611e358b48599939ab Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 8 Jul 2025 10:25:31 +0200
Subject: [PATCH 20/39] target/sim/verilator: Switch to Clang

---
 target/sim/verilator/verilator.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 3d7adce5..043bc636 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -23,6 +23,8 @@ VERILATOR_ARGS += -DASSERTS_OFF
 VERILATOR_ARGS += --threads 8
 # C++ Compiler Optimization
 VERILATOR_ARGS += -CFLAGS "-O3" -CFLAGS "-march=native" -CFLAGS "-mtune=native"
+# Use Clang (faster simulation than GCC)
+VERILATOR_ARGS += --compiler clang -MAKEFLAGS "CC=clang" -MAKEFLAGS "CXX=clang++"
 
 # Profiling
 # generates `gmon.out` that can be processed by `gprof` and then `verilator_profcfunc`

From 3d8cd28a654404a2647253864f41da081b906e66 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 8 Jul 2025 10:26:07 +0200
Subject: [PATCH 21/39] target/sim/verilator: Allow passing CLI arguments to
 simulation

---
 target/sim/verilator/verilator.mk | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 043bc636..f4ae94a5 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -53,6 +53,6 @@ $(CHS_ROOT)/target/sim/verilator/cheshire_soc.vlt: $(CHS_ROOT)/target/sim/verila
 	@echo "#!/bin/sh" > $@
 	@echo 'set -eu' >> $@
 	@echo 'cd $$(dirname "$$0")' >> $@
-	@echo '$(VERILATOR_PREFIX) ./obj_dir/Vcheshire_soc_wrapper' >> $@
+	@echo '$(VERILATOR_PREFIX) ./obj_dir/Vcheshire_soc_wrapper "$$@"' >> $@
 	@chmod +x $@
 

From 27516b91119619c5312f411bac139762c44f63bb Mon Sep 17 00:00:00 2001
From: Paul Scheffler <paulsc@iis.ee.ethz.ch>
Date: Mon, 7 Jul 2025 19:06:39 +0200
Subject: [PATCH 22/39] sw [WIP]: Add some tests

---
 sw/tests/dma_long.spm.c                |   38 +
 sw/tests/matmul.c                      |  168 ++
 sw/tests/matmul_data.h                 | 3082 ++++++++++++++++++++++++
 sw/tests/uart_fast.c                   |   26 +
 target/sim/src/fixture_cheshire_soc.sv |    6 +-
 target/sim/src/tb_cheshire_soc.sv      |    8 +-
 target/sim/vcs/start.cheshire_soc.sh   |    1 +
 target/sim/vsim/start.cheshire_soc.tcl |    1 +
 8 files changed, 3325 insertions(+), 5 deletions(-)
 create mode 100644 sw/tests/dma_long.spm.c
 create mode 100644 sw/tests/matmul.c
 create mode 100644 sw/tests/matmul_data.h
 create mode 100644 sw/tests/uart_fast.c

diff --git a/sw/tests/dma_long.spm.c b/sw/tests/dma_long.spm.c
new file mode 100644
index 00000000..4d598df4
--- /dev/null
+++ b/sw/tests/dma_long.spm.c
@@ -0,0 +1,38 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Nicole Narr <narrn@student.ethz.ch>
+// Christopher Reinwardt <creinwar@student.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+#include "regs/cheshire.h"
+#include "dif/clint.h"
+#include "params.h"
+#include "util.h"
+#include "dif/dma.h"
+
+int main(void) {
+    // Source and dst
+    volatile uint64_t dma_src = 0x80000000;
+    volatile uint64_t dma_dst = 0x80010000;
+
+    volatile uint64_t mcycle_start = get_mcycle();
+    volatile uint64_t mcycle_tot = get_mcycle() - mcycle_start;
+
+    for (int i = 1; i <= 11; ++i) {
+        fence();
+        uint64_t len = 1 << i;
+        uint64_t reps = 1024*1024 >> i;
+
+        mcycle_start = get_mcycle();
+
+        *((volatile uint32_t*)(void*)(uintptr_t)(0x010000d4)) = 1;
+
+        sys_dma_2d_blk_memcpy(dma_dst, (uintptr_t)(void*)dma_src, len, 0,
+                              0, reps, DMA_CONF_DECOUPLE_NONE);
+        mcycle_tot = get_mcycle() - mcycle_start;
+    }
+
+    return 0;
+}
diff --git a/sw/tests/matmul.c b/sw/tests/matmul.c
new file mode 100644
index 00000000..1574fd58
--- /dev/null
+++ b/sw/tests/matmul.c
@@ -0,0 +1,168 @@
+#include "regs/cheshire.h"
+#include "dif/clint.h"
+#include "params.h"
+#include "util.h"
+
+#include "matmul_data.h"
+int sN = 32;
+
+const int CHKSUM = 10614161;
+const int ITERATIONS = 16;
+
+
+// Get cycle count since reset
+static inline uint64_t get_minstret() {
+    uint64_t reg;
+    asm volatile("csrr %0, minstret" : "=r"(reg)::"memory");
+    return reg;
+}
+
+#define ROWOP(c0, c1, c2, c3) \
+    bb0 = &b[(n+0)*b_colstride + k]; \
+    bb1 = &b[(n+1)*b_colstride + k]; \
+    bb2 = &b[(n+2)*b_colstride + k]; \
+    bb3 = &b[(n+3)*b_colstride + k]; \
+    asm volatile( \
+        "fld  f0,  0(%[bb0]) \n" \
+        "fld  f1,  0(%[bb1]) \n" \
+        "fld  f2,  0(%[bb2]) \n" \
+        "fld  f3,  0(%[bb3]) \n" \
+        "fld  f4,  8(%[bb0]) \n" \
+        "fld  f5,  8(%[bb1]) \n" \
+        "fld  f6,  8(%[bb2]) \n" \
+        "fld  f7,  8(%[bb3]) \n" \
+        "fmadd.d %[cx0], %[ax0], f0, %[cx0] \n" \
+        "fmadd.d %[cx1], %[ax0], f1, %[cx1] \n" \
+        "fmadd.d %[cx2], %[ax0], f2, %[cx2] \n" \
+        "fmadd.d %[cx3], %[ax0], f3, %[cx3] \n" \
+        "fmadd.d %[cx0], %[ax1], f4, %[cx0] \n" \
+        "fmadd.d %[cx1], %[ax1], f5, %[cx1] \n" \
+        "fmadd.d %[cx2], %[ax1], f6, %[cx2] \n" \
+        "fmadd.d %[cx3], %[ax1], f7, %[cx3] \n" \
+        "fld  f0, 16(%[bb0]) \n" \
+        "fld  f1, 16(%[bb1]) \n" \
+        "fld  f2, 16(%[bb2]) \n" \
+        "fld  f3, 16(%[bb3]) \n" \
+        "fld  f4, 24(%[bb0]) \n" \
+        "fld  f5, 24(%[bb1]) \n" \
+        "fld  f6, 24(%[bb2]) \n" \
+        "fld  f7, 24(%[bb3]) \n" \
+        "fmadd.d %[cx0], %[ax2], f0, %[cx0] \n" \
+        "fmadd.d %[cx1], %[ax2], f1, %[cx1] \n" \
+        "fmadd.d %[cx2], %[ax2], f2, %[cx2] \n" \
+        "fmadd.d %[cx3], %[ax2], f3, %[cx3] \n" \
+        "fmadd.d %[cx0], %[ax3], f4, %[cx0] \n" \
+        "fmadd.d %[cx1], %[ax3], f5, %[cx1] \n" \
+        "fmadd.d %[cx2], %[ax3], f6, %[cx2] \n" \
+        "fmadd.d %[cx3], %[ax3], f7, %[cx3] \n" \
+        : \
+          [bb0]"+&r"(bb0), [bb1]"+&r"(bb1), [bb2]"+&r"(bb2), [bb3]"+&r"(bb3), \
+            [cx0]"+&f"(c0), [cx1]"+&f"(c1), [cx2]"+&f"(c2), [cx3]"+&f"(c3), \
+            [ax0]"+&f"(ax[0]), [ax1]"+&f"(ax[1]), [ax2]"+&f"(ax[2]), [ax3]"+&f"(ax[3]) \
+        :: "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7" \
+    ); \
+
+int __attribute__ ((visibility("hidden"))) __attribute__((noinline)) mmopt(
+    double* __restrict a,
+    double* __restrict b,
+    double* __restrict c,
+    int      N,
+    int      M,
+    int      K,
+    int      a_rowstride,
+    int      b_colstride,
+    int      c_rowstride
+) {
+    for (int m = 0; m < M; m+=4)
+    for (int n = 0; n < N; n+=4) {
+        // One output block per n-m pair
+
+        register double cb0  = c[c_rowstride*(m+0)+n+0];
+        register double cb1  = c[c_rowstride*(m+0)+n+1];
+        register double cb2  = c[c_rowstride*(m+0)+n+2];
+        register double cb3  = c[c_rowstride*(m+0)+n+3];
+        register double cb4  = c[c_rowstride*(m+1)+n+0];
+        register double cb5  = c[c_rowstride*(m+1)+n+1];
+        register double cb6  = c[c_rowstride*(m+1)+n+2];
+        register double cb7  = c[c_rowstride*(m+1)+n+3];
+        register double cb8  = c[c_rowstride*(m+2)+n+0];
+        register double cb9  = c[c_rowstride*(m+2)+n+1];
+        register double cb10 = c[c_rowstride*(m+2)+n+2];
+        register double cb11 = c[c_rowstride*(m+2)+n+3];
+        register double cb12 = c[c_rowstride*(m+3)+n+0];
+        register double cb13 = c[c_rowstride*(m+3)+n+1];
+        register double cb14 = c[c_rowstride*(m+3)+n+2];
+        register double cb15 = c[c_rowstride*(m+3)+n+3];
+
+        for (int k = 0; k < K; k+=4) {
+            register double *bb0, *bb1, *bb2, *bb3;
+
+            register double* ax = &a[m*a_rowstride + k];
+            ROWOP(cb0, cb1, cb2, cb3)
+
+            ax += a_rowstride;
+            ROWOP(cb4, cb5, cb6, cb7)
+
+            ax += a_rowstride;
+            ROWOP(cb8, cb9, cb10, cb11)
+
+            ax += a_rowstride;
+            ROWOP(cb12, cb13, cb14, cb15)
+        }
+        // Write back output block
+        c[(m+0)*c_rowstride + (n+0)] = cb0;
+        c[(m+0)*c_rowstride + (n+1)] = cb1;
+        c[(m+0)*c_rowstride + (n+2)] = cb2;
+        c[(m+0)*c_rowstride + (n+3)] = cb3;
+        c[(m+1)*c_rowstride + (n+0)] = cb4;
+        c[(m+1)*c_rowstride + (n+1)] = cb5;
+        c[(m+1)*c_rowstride + (n+2)] = cb6;
+        c[(m+1)*c_rowstride + (n+3)] = cb7;
+        c[(m+2)*c_rowstride + (n+0)] = cb8;
+        c[(m+2)*c_rowstride + (n+1)] = cb9;
+        c[(m+2)*c_rowstride + (n+2)] = cb10;
+        c[(m+2)*c_rowstride + (n+3)] = cb11;
+        c[(m+3)*c_rowstride + (n+0)] = cb12;
+        c[(m+3)*c_rowstride + (n+1)] = cb13;
+        c[(m+3)*c_rowstride + (n+2)] = cb14;
+        c[(m+3)*c_rowstride + (n+3)] = cb15;
+    }
+    return 0;
+}
+
+int main(void) {
+
+    // Get start cycle count
+    uint32_t instret = get_minstret();
+    uint32_t cycles = get_mcycle();
+
+    for (int i = 0; i < ITERATIONS; ++i) {
+        mmopt(
+            float_data_a,
+            float_data_b,
+            float_data_c,
+            sN, sN, sN,
+            sN, sN, sN
+        );
+    }
+
+    // Get end cycle count
+    cycles = get_mcycle() - cycles;
+    instret = get_minstret() - instret;
+
+    // Compute checksum
+    double checksum = 0.0;
+    for (int y = 0; y < sN; y++) {
+        double sign = (y & 1) ? -1.0 : 1.0;
+        for (int x = 0; x < sN; x++) {
+            checksum += sign*1000.0*1000.0*float_data_c[y*sN+x];
+        }
+    }
+
+    // Scale checksum to int.
+    // Take ~2 digits off (divide by 128) to account for FP rounding.
+    uint64_t chkint = (uint64_t)(checksum) >> 7;
+
+    // Check return
+    return (chkint != CHKSUM);
+}
diff --git a/sw/tests/matmul_data.h b/sw/tests/matmul_data.h
new file mode 100644
index 00000000..95b57d4b
--- /dev/null
+++ b/sw/tests/matmul_data.h
@@ -0,0 +1,3082 @@
+#define NN 1024
+
+__attribute__((aligned(8))) double float_data_a [NN] = {
+    0.5352350007344391,
+    0.4340999186868998,
+    0.3573451265334625,
+    0.659877532628472,
+    0.40853921437460894,
+    0.3354228481944037,
+    0.48833816165085,
+    0.03940478777764589,
+    0.7585197684433818,
+    0.7308074291972139,
+    0.12187569370840279,
+    0.5914408651199228,
+    0.33901095078768173,
+    0.934096273831717,
+    0.5217518670462218,
+    0.896709983408266,
+    0.991984552154219,
+    0.16769154033383038,
+    0.8276114461606534,
+    0.130490395423713,
+    0.37102367657065705,
+    0.03819386018411575,
+    0.8787352942183696,
+    0.0670103601745633,
+    0.464775185852243,
+    0.5523675879615805,
+    0.32012811136551833,
+    0.4148976360932447,
+    0.008806127930397811,
+    0.6206644817725114,
+    0.3083133613960074,
+    0.7777989615621607,
+    0.3001731367360575,
+    0.5451352039072916,
+    0.7543933435572973,
+    0.15044999045782415,
+    0.5623470545100572,
+    0.8746708163827082,
+    0.46054924018583465,
+    0.03588711504886111,
+    0.3186146168786429,
+    0.6123257191226615,
+    0.8292670490557523,
+    0.4667497831385504,
+    0.6500578343072372,
+    0.7033950328107438,
+    0.4767846807955809,
+    0.5643026947238519,
+    0.4667231897508465,
+    0.047747185571421547,
+    0.4014910742993021,
+    0.2799344730073534,
+    0.248644318867275,
+    0.4842955273167646,
+    0.9652452690546509,
+    0.021766164014830336,
+    0.4989635433680225,
+    0.8631644794983719,
+    0.4713414470089018,
+    0.9022864960426287,
+    0.6408922635454807,
+    0.9655958989669046,
+    0.7494955940762992,
+    0.19772487031386488,
+    0.6131871993091498,
+    0.1153300482192483,
+    0.8626974808409035,
+    0.4683605904126733,
+    0.6852147966692926,
+    0.11919154822350952,
+    0.5353611627851229,
+    0.6115256163505468,
+    0.19756061509553957,
+    0.048376192124068296,
+    0.7008521905121031,
+    0.5365629235635951,
+    0.33034541831671094,
+    0.5836903326699904,
+    0.4325493218146902,
+    0.29162680904624483,
+    0.7893267576047148,
+    0.03849836071307289,
+    0.4163227385756013,
+    0.8691911422994578,
+    0.319288277047894,
+    0.10751688065497367,
+    0.45009499972438816,
+    0.3674200955364346,
+    0.2656554447532048,
+    0.1449277176439191,
+    0.33447176953647406,
+    0.5647780245474932,
+    0.3687890828435174,
+    0.0370426075140855,
+    0.46879660919241406,
+    0.7969891083841032,
+    0.27467799471562593,
+    0.2708796464280676,
+    0.13213214175212473,
+    0.9795132414957441,
+    0.36836118250203465,
+    0.09690316182801262,
+    0.7978049338955066,
+    0.02579276833414812,
+    0.22292598082661286,
+    0.8870831581099181,
+    0.4275597207619688,
+    0.49331675554249,
+    0.9183030829372818,
+    0.393981061073861,
+    0.5326304083119843,
+    0.8762503929800484,
+    0.31414750936905134,
+    0.3938021087720709,
+    0.5396460808503604,
+    0.8686474751422611,
+    0.46231357204273693,
+    0.24661517903696883,
+    0.15779447788212142,
+    0.855451540278821,
+    0.40656338652193214,
+    0.6806113646235357,
+    0.33389682514977226,
+    0.42918080759436383,
+    0.9684440955646876,
+    0.5151820254678332,
+    0.8533188872214227,
+    0.45326888983661884,
+    0.5199019760978683,
+    0.5912060607348202,
+    0.849790177819391,
+    0.5682404577587885,
+    0.5885573266839357,
+    0.5627415798429155,
+    0.703669752848177,
+    0.3025310295939335,
+    0.24923211984440574,
+    0.6983818714976057,
+    0.9669019371802734,
+    0.607857529196033,
+    0.043584372786693915,
+    0.5160218832096133,
+    0.7424835058256062,
+    0.22233351557663128,
+    0.9208365517273671,
+    0.402694352615635,
+    0.3360413141646311,
+    0.4989779230706036,
+    0.05411104789275101,
+    0.8028179169686925,
+    0.3670400367475437,
+    0.8100277289328653,
+    0.6320451675735316,
+    0.6198269605870753,
+    0.9796309001883268,
+    0.28970006610181354,
+    0.8026306770821668,
+    0.28620778692139526,
+    0.207399217412649,
+    0.3446883083400746,
+    0.4513164976114663,
+    0.365323553038427,
+    0.7540456656243462,
+    0.10758964755155542,
+    0.47069837103835777,
+    0.4353892022037008,
+    0.6576225863935043,
+    0.03305290193326893,
+    0.9832073983978341,
+    0.06769761387961681,
+    0.45554405645424023,
+    0.8074710903684919,
+    0.09695686572637008,
+    0.3452084616133393,
+    0.02027397462540048,
+    0.5869067139303112,
+    0.6798540822794223,
+    0.21940105220469341,
+    0.8826709277184172,
+    0.1269612695707094,
+    0.8083446231761735,
+    0.48707963624693784,
+    0.7202591418416773,
+    0.29880798358118754,
+    0.39797914623399033,
+    0.16713571560652118,
+    0.9681474819872848,
+    0.3308929153451038,
+    0.047395490536004226,
+    0.042614255771095344,
+    0.35466387787188725,
+    0.6664217903674834,
+    0.2783888671793331,
+    0.3377368238269802,
+    0.326053967593386,
+    0.16764421322615497,
+    0.4431463083688566,
+    0.1789977858753986,
+    0.9630258585194897,
+    0.9098091950581768,
+    0.12755910542111926,
+    0.4055945116287927,
+    0.23475049455298458,
+    0.36415847463829454,
+    0.05943047425254522,
+    0.4202190793590731,
+    0.4264719801421728,
+    0.8753887817872771,
+    0.6486616151437884,
+    0.22373926870407257,
+    0.5994499102338221,
+    0.6504882153182292,
+    0.8087306172269466,
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+__attribute__((aligned(8))) double float_data_b [NN] = {
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+};
+
+__attribute__((aligned(8))) double float_data_c [NN] = {
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+    0.68337370785922072031,
+    0.72346412281148926516,
+    0.98856642605699222044,
+    0.06419975210251705182,
+    0.43245328810081025008,
+    0.95089541206884764428,
+    0.80646774282220293848,
+    0.37449673743936345613,
+    0.73600724805295183513,
+    0.56298760866691894097,
+    0.18154843972018286136,
+    0.64205837317930876468,
+    0.97703178915818642906,
+    0.98483114130997542274,
+    0.85075665866453556997,
+    0.20826227327326149278,
+    0.02451473228287948273,
+    0.71852639456524491102,
+    0.02651913137538242521,
+    0.08716590038640948247,
+    0.58122030018534173925,
+    0.57279112926688983033,
+    0.98420187737238812361,
+    0.97989381697835392083,
+    0.08238849511088764068,
+    0.70248863069818018227,
+    0.87351228039932275164,
+    0.50600127613507258334,
+    0.61337265517418554044,
+    0.59759228966577248179,
+    0.62929343631990340090,
+    0.42271064883701395385,
+    0.04770197468523873593,
+    0.54583150676702040354,
+    0.01109998648237475773,
+    0.80173996270821599242,
+    0.81669481294747162192,
+    0.26332521334033725489,
+    0.20930201576468677809,
+    0.15515407678251514634,
+    0.76879175078530755452,
+    0.17171983435520655700,
+    0.40173136421181055384,
+    0.05315059256127863110,
+    0.53930146834189540388,
+    0.97602282078746786090,
+    0.97160032610225386863,
+    0.11837388277568273375,
+    0.99687069353187421429,
+    0.90584619533513149425,
+    0.14203438036394977821
+};
diff --git a/sw/tests/uart_fast.c b/sw/tests/uart_fast.c
new file mode 100644
index 00000000..6f31f0f6
--- /dev/null
+++ b/sw/tests/uart_fast.c
@@ -0,0 +1,26 @@
+// Copyright 2023 ETH Zurich and University of Bologna.
+// Licensed under the Apache License, Version 2.0, see LICENSE for details.
+// SPDX-License-Identifier: Apache-2.0
+//
+// Nicole Narr <narrn@student.ethz.ch>
+// Christopher Reinwardt <creinwar@student.ethz.ch>
+// Paul Scheffler <paulsc@iis.ee.ethz.ch>
+
+#include "regs/cheshire.h"
+#include "dif/clint.h"
+#include "dif/uart.h"
+#include "params.h"
+#include "util.h"
+
+int main(void) {
+    char str[] =
+        "Lorem ipsum dolor sit amet, consectetur adipiscing elit, sed do eiusmod tempor\r\n"
+        "incididunt ut labore et dolore magna aliqua. Ut enim ad minim veniam, quis\r\n"
+        "nostrud exercitation ullamco laboris nisi ut aliquip ex ea commodo consequat.\r\n";
+    uint32_t rtc_freq = *reg32(&__base_regs, CHESHIRE_RTC_FREQ_REG_OFFSET);
+    uint64_t reset_freq = clint_get_core_freq(rtc_freq, 2500);
+    uart_init(&__base_uart, reset_freq, __BOOT_BAUDRATE * 8);
+    uart_write_str(&__base_uart, str, sizeof(str) - 1);
+    uart_write_flush(&__base_uart);
+    return 0;
+}
diff --git a/target/sim/src/fixture_cheshire_soc.sv b/target/sim/src/fixture_cheshire_soc.sv
index 056f0b33..34eb0a9c 100644
--- a/target/sim/src/fixture_cheshire_soc.sv
+++ b/target/sim/src/fixture_cheshire_soc.sv
@@ -8,8 +8,9 @@
 
 module fixture_cheshire_soc #(
   /// The selected simulation configuration from the `tb_cheshire_pkg`.
-  parameter int unsigned SelectedCfg = 32'd0,
-  parameter bit          UseDramSys  = 1'b0
+  parameter int unsigned SelectedCfg  = 32'd0,
+  parameter bit          UseDramSys   = 1'b0,
+  parameter int unsigned UartBaudRate = 115200
 );
 
   `include "cheshire/typedef.svh"
@@ -170,6 +171,7 @@ module fixture_cheshire_soc #(
   vip_cheshire_soc #(
     .DutCfg            ( DutCfg ),
     .UseDramSys        ( UseDramSys ),
+    .UartBaudRate      ( UartBaudRate ),
     .axi_ext_llc_req_t ( axi_llc_req_t ),
     .axi_ext_llc_rsp_t ( axi_llc_rsp_t ),
     .axi_ext_mst_req_t ( axi_mst_req_t ),
diff --git a/target/sim/src/tb_cheshire_soc.sv b/target/sim/src/tb_cheshire_soc.sv
index 57a15e8b..fd571c3c 100644
--- a/target/sim/src/tb_cheshire_soc.sv
+++ b/target/sim/src/tb_cheshire_soc.sv
@@ -7,13 +7,15 @@
 
 module tb_cheshire_soc #(
   /// The selected simulation configuration from the `tb_cheshire_pkg`.
-  parameter int unsigned SelectedCfg = 32'd0,
-  parameter bit          UseDramSys  = 1'b0
+  parameter int unsigned SelectedCfg  = 32'd0,
+  parameter bit          UseDramSys   = 1'b0,
+  parameter int unsigned UartBaudRate = 115200
 );
 
   fixture_cheshire_soc #(
     .SelectedCfg  (SelectedCfg),
-    .UseDramSys   (UseDramSys)
+    .UseDramSys   (UseDramSys),
+    .UartBaudRate (UartBaudRate)
   ) fix();
 
   string      preload_elf;
diff --git a/target/sim/vcs/start.cheshire_soc.sh b/target/sim/vcs/start.cheshire_soc.sh
index 6352c520..db3e63fc 100755
--- a/target/sim/vcs/start.cheshire_soc.sh
+++ b/target/sim/vcs/start.cheshire_soc.sh
@@ -29,6 +29,7 @@ fi
 
 flags+="-cpp ${CXX_PATH} "
 [[ -n "${SELCFG}" ]]   && flags+="-pvalue+SelectedCfg=${SELCFG} "
+[[ -n "${UARTBAUD}" ]] && flags+="-pvalue+UartBaudRate=${UARTBAUD} "
 
 pargs=""
 [[ -n "${BOOTMODE}" ]] && pargs+="+BOOTMODE=${BOOTMODE} "
diff --git a/target/sim/vsim/start.cheshire_soc.tcl b/target/sim/vsim/start.cheshire_soc.tcl
index e6a005d4..02d4f334 100644
--- a/target/sim/vsim/start.cheshire_soc.tcl
+++ b/target/sim/vsim/start.cheshire_soc.tcl
@@ -29,6 +29,7 @@ if { ![info exists VOPTARGS] } {
 
 set flags "-suppress 3009 -suppress 8386 -error 7 -cpppath ${CXX_PATH} "
 if { [info exists SELCFG] } { append flags "-GSelectedCfg=${SELCFG} " }
+if { [info exists UARTBAUD] } { append flags "-GUartBaudRate=${UARTBAUD} " }
 
 set pargs ""
 if { [info exists BOOTMODE] } { append pargs "+BOOTMODE=${BOOTMODE} " }

From 8ddc0c02937740f2fb21bb7471b746416b017663 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 8 Jul 2025 14:48:52 +0200
Subject: [PATCH 23/39] target/sim/verilator: Properly measure simulation rate
 without preloading

---
 target/sim/verilator/sim/Mem64Master.h |  4 +++
 target/sim/verilator/sim/main.cpp      | 44 ++++++++++++++++++++++++--
 2 files changed, 46 insertions(+), 2 deletions(-)

diff --git a/target/sim/verilator/sim/Mem64Master.h b/target/sim/verilator/sim/Mem64Master.h
index c219e242..35e6dd7d 100644
--- a/target/sim/verilator/sim/Mem64Master.h
+++ b/target/sim/verilator/sim/Mem64Master.h
@@ -60,6 +60,10 @@ class Mem64Master {
         *m_mem_be_o = 0;
     }
 
+    bool has_write() {
+        return !m_write_request_queue.empty();
+    }
+
     void write(uint64_t addr, uint64_t data) {
         m_write_request_queue.push({ addr, data });
     }
diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index c46c10eb..c9e0a9f1 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -17,7 +17,7 @@
 
 #define RST_CYCLES 5
 
-#define SIMULATION_RATE_CHUNK 10000
+#define SIMULATION_RATE_CHUNK 50000
 
 // #define BENCHMARK
 
@@ -38,6 +38,11 @@ extern int jtag_tick(int port, unsigned char *jtag_TCK, unsigned char *jtag_TMS,
     unsigned char *jtag_TDI, unsigned char *jtag_TRSTn, unsigned char jtag_TDO);
 
 
+double get_seconds() {
+    auto duration = std::chrono::system_clock::now().time_since_epoch();
+    return std::chrono::duration_cast<std::chrono::microseconds>(duration).count() / 1e6;
+}
+
 static void jtag_tick_io() {
   static int count = 0;
   if (count < 10) {
@@ -161,6 +166,17 @@ int main(int argc, char** argv) {
     // This needs to be called before you create any model
     contextp->commandArgs(argc, argv);
 
+    const char *filename_plusarg = contextp->commandArgsPlusMatch("BINARY=");
+    if (strlen(filename_plusarg) == 0) {
+      VL_PRINTF("Error: no binary specified (+BINARY=...)\n");
+      return 1;
+    }
+    const char *filename = filename_plusarg + strlen("+BINARY=");
+    if (!filename || strlen(filename) == 0 || filename[0] != '/') {
+      VL_PRINTF("Error: +BINARY requires absolute path\n");
+      return 1;
+    }
+
     // "TOP" will be the hierarchical name of the module
     topp = std::make_unique<Vcheshire_soc_wrapper>(contextp.get(), "TOP");
 
@@ -182,6 +198,12 @@ int main(int argc, char** argv) {
     uint64_t next_rtc_toggle_ps = 0;
     bool reset_done = false;
 
+    uint64_t start_cycle = cycle;
+    uint64_t start_time = get_seconds();
+
+    uint64_t preload_done_cycle = 0;
+    double preload_done_time = -1;
+
     mem_master = std::make_unique<Mem64Master>(
         &topp->slink_mem_req_i,
         &topp->slink_mem_addr_i,
@@ -194,7 +216,6 @@ int main(int argc, char** argv) {
     );
 
     // ELF preloading
-    const char *filename = "../../../sw/tests/helloworld.spm.elf";
     if (!elf_preload_open(filename))
       return 1;
 
@@ -227,6 +248,12 @@ int main(int argc, char** argv) {
           if (cycle == 2000)
             elf_preload_write_enqueue();
 
+          if (cycle > 2000 && !preload_done_cycle && !mem_master->has_write()) {
+            preload_done_cycle = cycle;
+            preload_done_time = get_seconds();
+            VL_PRINTF("[ELF] preload complete\n");
+          }
+
           // I/O
           if (reset_done) {
             poll_for_exit();
@@ -281,6 +308,18 @@ int main(int argc, char** argv) {
         }
     }
 
+    uint64_t exit_cycle = cycle;
+    double exit_time = get_seconds();
+
+    auto total_cycles = exit_cycle - start_cycle;
+    auto total_time = exit_time - start_time;
+    VL_PRINTF("[STAT] total:            %.3f seconds, %lu cycles, %.1f kHz\n",
+        total_time, total_cycles, total_cycles / total_time / 1e3);
+    auto run_cycles = exit_cycle - preload_done_cycle;
+    auto run_time = exit_time - preload_done_time;
+    VL_PRINTF("[STAT] after preloading: %.3f seconds, %lu cycles, %.1f kHz\n",
+        run_time, run_cycles, run_cycles / run_time / 1e3);
+
     // Final model cleanup
     topp->final();
 
@@ -295,6 +334,7 @@ int main(int argc, char** argv) {
 #endif
 
     // Final simulation summary
+    VL_PRINTF("\n");
     contextp->statsPrintSummary();
 
     // Return good completion status

From 19d2d3146d6d960280830f5e0f52f7d3e6af7715 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 8 Jul 2025 14:50:12 +0200
Subject: [PATCH 24/39] target/sim/verilator: Speed-up preloading by using
 bigger axi_from_mem queue

---
 target/sim/verilator/src/cheshire_soc_wrapper.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index a07736d1..ebba1cbb 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -271,7 +271,7 @@ module cheshire_soc_wrapper # (
     .MemAddrWidth ( DutCfg.AddrWidth    ),
     .AxiAddrWidth ( DutCfg.AddrWidth    ),
     .DataWidth    ( DutCfg.AxiDataWidth ),
-    .MaxRequests  ( 8                   ),
+    .MaxRequests  ( 64                  ),
     .AxiProt      ( 3'b000              ),
     .axi_req_t    ( axi_mst_req_t       ),
     .axi_rsp_t    ( axi_mst_rsp_t       )

From 33a0d2e9391188b509b477aca1e85ff1b5ecb8ff Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 8 Jul 2025 14:54:53 +0200
Subject: [PATCH 25/39] target/sim/verilator: Use taskset to avoid slow
 parallel execution

---
 target/sim/verilator/verilator.mk | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index f4ae94a5..bdaea719 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -11,6 +11,8 @@ RISCV_DBG_DIR = $(shell bender path riscv-dbg)
 VERILATOR_PREFIX ?= oseda
 VERILATOR        ?= verilator
 
+CHS_VERILATOR_THREADS ?= 4
+
 # Silly Verilator warnings: these are perfectly valid and should not be warnings
 VERILATOR_WNO   = -Wno-fatal -Wno-style \
 	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
@@ -20,7 +22,7 @@ VERILATOR_ARGS += -O3 --x-assign fast --x-initial fast --noassert
 # Disable common_cells assertions
 VERILATOR_ARGS += -DASSERTS_OFF
 # multithreading
-VERILATOR_ARGS += --threads 8
+VERILATOR_ARGS += --threads $(CHS_VERILATOR_THREADS)
 # C++ Compiler Optimization
 VERILATOR_ARGS += -CFLAGS "-O3" -CFLAGS "-march=native" -CFLAGS "-mtune=native"
 # Use Clang (faster simulation than GCC)
@@ -53,6 +55,6 @@ $(CHS_ROOT)/target/sim/verilator/cheshire_soc.vlt: $(CHS_ROOT)/target/sim/verila
 	@echo "#!/bin/sh" > $@
 	@echo 'set -eu' >> $@
 	@echo 'cd $$(dirname "$$0")' >> $@
-	@echo '$(VERILATOR_PREFIX) ./obj_dir/Vcheshire_soc_wrapper "$$@"' >> $@
+	@echo 'taskset -c 0-$(shell expr $(CHS_VERILATOR_THREADS) - 1) $(VERILATOR_PREFIX) ./obj_dir/Vcheshire_soc_wrapper "$$@"' >> $@
 	@chmod +x $@
 

From 9a71b76cf802f4b59b4437ad647cf87cb2165f22 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 8 Jul 2025 17:09:47 +0200
Subject: [PATCH 26/39] target/sim/verilator: Implement fake DRAM using tc_sram

---
 target/sim/verilator/sim/main.cpp             |  3 +-
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 93 ++++++++++++-------
 2 files changed, 63 insertions(+), 33 deletions(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index c9e0a9f1..f3f53c8d 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -256,7 +256,8 @@ int main(int argc, char** argv) {
 
           // I/O
           if (reset_done) {
-            poll_for_exit();
+            if (preload_done_cycle > 0)
+              poll_for_exit();
 #if 0
             jtag_tick_io();
 #endif
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index ebba1cbb..2c4eef4e 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -169,38 +169,67 @@ module cheshire_soc_wrapper # (
   //  DRAM  //
   ////////////
 
-  // axi_sim_mem #(
-  //   .AddrWidth          ( DutCfg.AddrWidth    ),
-  //   .DataWidth          ( DutCfg.AxiDataWidth ),
-  //   .IdWidth            ( $bits(axi_llc_id_t) ),
-  //   .UserWidth          ( DutCfg.AxiUserWidth ),
-  //   .axi_req_t          ( axi_llc_req_t ),
-  //   .axi_rsp_t          ( axi_llc_rsp_t ),
-  //   .WarnUninitialized  ( 0 ),
-  //   .ClearErrOnAccess   ( 1 ),
-  //   .ApplDelay          ( 0ps ),
-  //   .AcqDelay           ( 0ps )
-  // ) i_dram_sim_mem (
-  //   .clk_i              ( clk_i  ),
-  //   .rst_ni             ( rst_ni ),
-  //   .axi_req_i          ( axi_llc_mst_req ),
-  //   .axi_rsp_o          ( axi_llc_mst_rsp ),
-  //   .mon_w_valid_o      ( ),
-  //   .mon_w_addr_o       ( ),
-  //   .mon_w_data_o       ( ),
-  //   .mon_w_id_o         ( ),
-  //   .mon_w_user_o       ( ),
-  //   .mon_w_beat_count_o ( ),
-  //   .mon_w_last_o       ( ),
-  //   .mon_r_valid_o      ( ),
-  //   .mon_r_addr_o       ( ),
-  //   .mon_r_data_o       ( ),
-  //   .mon_r_id_o         ( ),
-  //   .mon_r_user_o       ( ),
-  //   .mon_r_beat_count_o ( ),
-  //   .mon_r_last_o       ( )
-  // );
-  assign axi_llc_mst_rsp = '0;
+  // Emulate DRAM using an AXI-to-MEM adapter and a huge tc_sram spanning the full address space.
+
+  logic                             dram_mem_req;
+  logic [DutCfg.AddrWidth-1:0]      dram_mem_addr;
+  logic [DutCfg.AxiDataWidth-1:0]   dram_mem_wdata;
+  logic [DutCfg.AxiDataWidth/8-1:0] dram_mem_strb;
+  logic                             dram_mem_we;
+  logic                             dram_mem_rvalid;
+  logic [DutCfg.AxiDataWidth-1:0]   dram_mem_rdata;
+
+  axi_to_mem #(
+    .axi_req_t    ( axi_llc_req_t       ),
+    .axi_resp_t   ( axi_llc_rsp_t       ),
+    .AddrWidth    ( DutCfg.AddrWidth    ),
+    .DataWidth    ( DutCfg.AxiDataWidth ),
+    .IdWidth      ( $bits(axi_llc_id_t) ),
+    .NumBanks     ( 1                   ),
+    .BufDepth     ( 1                   ),
+    .HideStrb     ( 1'b1                ),
+    .OutFifoDepth ( 1                   )
+  ) i_dram_axi (
+    .clk_i,
+    .rst_ni,
+    .busy_o       (                 ),
+    .axi_req_i    ( axi_llc_mst_req ),
+    .axi_resp_o   ( axi_llc_mst_rsp ),
+    .mem_req_o    ( dram_mem_req    ),
+    .mem_gnt_i    ( 1'b1            ),
+    .mem_addr_o   ( dram_mem_addr   ),
+    .mem_wdata_o  ( dram_mem_wdata  ),
+    .mem_strb_o   ( dram_mem_strb   ),
+    .mem_atop_o   (                 ),
+    .mem_we_o     ( dram_mem_we     ),
+    .mem_rvalid_i ( dram_mem_rvalid ),
+    .mem_rdata_i  ( dram_mem_rdata  )
+  );
+
+  // NOTE: This strategy ceases to work once we overflow 32-bit integers for NumDramWords, as
+  // tc_sram was never design for things like this.
+  localparam int unsigned DramDataWidth = $clog2(DutCfg.LlcOutRegionEnd - DutCfg.LlcOutRegionStart);
+  localparam int unsigned NumDramWords = (1 << DramDataWidth) / DutCfg.AxiDataWidth;
+  tc_sram #(
+    .NumWords  ( NumDramWords        ),
+    .DataWidth ( DutCfg.AxiDataWidth ),
+    .ByteWidth ( 8                   ),
+    .NumPorts  ( 1                   ),
+    .Latency   ( 1                   )
+  ) i_dram (
+    .clk_i,
+    .rst_ni,
+    .req_i   ( dram_mem_req                     ),
+    .we_i    ( dram_mem_we                      ),
+    .addr_i  ( dram_mem_addr[DramDataWidth-1:0] ),
+    .wdata_i ( dram_mem_wdata                   ),
+    .be_i    ( dram_mem_strb                    ),
+    .rdata_o ( dram_mem_rdata                   )
+  );
+
+  logic dram_mem_req_q;
+  `FF(dram_mem_req_q, dram_mem_req, 1'b0);
+  assign dram_mem_rvalid = dram_mem_req_q;
 
   ////////////
   //  UART  //

From c5d69fbc8d5e33c437390c0617dba986f43dd77c Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Wed, 9 Jul 2025 10:44:42 +0200
Subject: [PATCH 27/39] target/sim/verilator: Split R/W channels for DRAM to
 avoid DMA lock-up

---
 .../sim/verilator/src/cheshire_soc_wrapper.sv | 75 +++++++++++--------
 1 file changed, 44 insertions(+), 31 deletions(-)

diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 2c4eef4e..cd27204a 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -169,34 +169,41 @@ module cheshire_soc_wrapper # (
   //  DRAM  //
   ////////////
 
-  // Emulate DRAM using an AXI-to-MEM adapter and a huge tc_sram spanning the full address space.
+  // Emulate DRAM using an AXI-to-MEM adapter and a tc_sram
 
-  logic                             dram_mem_req;
-  logic [DutCfg.AddrWidth-1:0]      dram_mem_addr;
-  logic [DutCfg.AxiDataWidth-1:0]   dram_mem_wdata;
-  logic [DutCfg.AxiDataWidth/8-1:0] dram_mem_strb;
-  logic                             dram_mem_we;
-  logic                             dram_mem_rvalid;
-  logic [DutCfg.AxiDataWidth-1:0]   dram_mem_rdata;
+  // NOTE: This strategy ceases to work once we overflow 32-bit integers for NumDramWords, as
+  // tc_sram was never designed for things like this.
+  // This also assumes that the DRAM region is naturally aligned to a power of two.
+  localparam int unsigned DramAddrWidth     = $clog2(DutCfg.LlcOutRegionEnd - DutCfg.LlcOutRegionStart);
+  localparam int unsigned DramDataWidth     = DutCfg.AxiDataWidth;
+
+  logic [1:0]                      dram_mem_req;
+  logic [1:0][DramAddrWidth-1:0]   dram_mem_addr;
+  logic [1:0][DramDataWidth-1:0]   dram_mem_wdata;
+  logic [1:0][DramDataWidth/8-1:0] dram_mem_strb;
+  logic [1:0]                      dram_mem_we;
+  logic [1:0]                      dram_mem_rvalid;
+  logic [1:0][DramDataWidth-1:0]   dram_mem_rdata;
 
-  axi_to_mem #(
+  axi_to_mem_split #(
     .axi_req_t    ( axi_llc_req_t       ),
     .axi_resp_t   ( axi_llc_rsp_t       ),
-    .AddrWidth    ( DutCfg.AddrWidth    ),
-    .DataWidth    ( DutCfg.AxiDataWidth ),
+    .AddrWidth    ( DramAddrWidth       ),
+    .AxiDataWidth ( DramDataWidth       ),
     .IdWidth      ( $bits(axi_llc_id_t) ),
-    .NumBanks     ( 1                   ),
+    .MemDataWidth ( DramDataWidth       ),
     .BufDepth     ( 1                   ),
     .HideStrb     ( 1'b1                ),
     .OutFifoDepth ( 1                   )
   ) i_dram_axi (
     .clk_i,
     .rst_ni,
+    .test_i       ( 1'b0            ),
     .busy_o       (                 ),
     .axi_req_i    ( axi_llc_mst_req ),
     .axi_resp_o   ( axi_llc_mst_rsp ),
     .mem_req_o    ( dram_mem_req    ),
-    .mem_gnt_i    ( 1'b1            ),
+    .mem_gnt_i    ( 2'b11           ),
     .mem_addr_o   ( dram_mem_addr   ),
     .mem_wdata_o  ( dram_mem_wdata  ),
     .mem_strb_o   ( dram_mem_strb   ),
@@ -206,29 +213,35 @@ module cheshire_soc_wrapper # (
     .mem_rdata_i  ( dram_mem_rdata  )
   );
 
-  // NOTE: This strategy ceases to work once we overflow 32-bit integers for NumDramWords, as
-  // tc_sram was never design for things like this.
-  localparam int unsigned DramDataWidth = $clog2(DutCfg.LlcOutRegionEnd - DutCfg.LlcOutRegionStart);
-  localparam int unsigned NumDramWords = (1 << DramDataWidth) / DutCfg.AxiDataWidth;
+  localparam int unsigned DramWordAddrWidth = DramAddrWidth - $clog2(DramDataWidth / 8);
+  localparam int unsigned NumDramWords      = 1 << DramWordAddrWidth;
+
+  // Translate byte addresses (from axi_to_mem_split) to word addresses (for tc_sram)
+  logic [1:0][DramWordAddrWidth-1:0] dram_mem_word_addr;
+  assign dram_mem_word_addr = {
+    dram_mem_addr[1][DramAddrWidth-1:DramAddrWidth-DramWordAddrWidth],
+    dram_mem_addr[0][DramAddrWidth-1:DramAddrWidth-DramWordAddrWidth]
+  };
+
   tc_sram #(
-    .NumWords  ( NumDramWords        ),
-    .DataWidth ( DutCfg.AxiDataWidth ),
-    .ByteWidth ( 8                   ),
-    .NumPorts  ( 1                   ),
-    .Latency   ( 1                   )
-  ) i_dram (
+    .NumWords  ( NumDramWords  ),
+    .DataWidth ( DramDataWidth ),
+    .ByteWidth ( 8             ),
+    .NumPorts  ( 2             ),
+    .Latency   ( 1             )
+  ) i_dram(
     .clk_i,
     .rst_ni,
-    .req_i   ( dram_mem_req                     ),
-    .we_i    ( dram_mem_we                      ),
-    .addr_i  ( dram_mem_addr[DramDataWidth-1:0] ),
-    .wdata_i ( dram_mem_wdata                   ),
-    .be_i    ( dram_mem_strb                    ),
-    .rdata_o ( dram_mem_rdata                   )
+    .req_i   ( dram_mem_req       ),
+    .we_i    ( dram_mem_we        ),
+    .addr_i  ( dram_mem_word_addr ),
+    .wdata_i ( dram_mem_wdata     ),
+    .be_i    ( dram_mem_strb      ),
+    .rdata_o ( dram_mem_rdata     )
   );
 
-  logic dram_mem_req_q;
-  `FF(dram_mem_req_q, dram_mem_req, 1'b0);
+  logic [1:0] dram_mem_req_q;
+  `FF(dram_mem_req_q, dram_mem_req, 2'b0);
   assign dram_mem_rvalid = dram_mem_req_q;
 
   ////////////

From 98aee59e6a8ecaea6bd975dbe404ba64329f2181 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Wed, 9 Jul 2025 12:02:44 +0200
Subject: [PATCH 28/39] sw/tests/dma_long: Reduce # repetitions

---
 sw/tests/dma_long.spm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/sw/tests/dma_long.spm.c b/sw/tests/dma_long.spm.c
index 4d598df4..9afcbddf 100644
--- a/sw/tests/dma_long.spm.c
+++ b/sw/tests/dma_long.spm.c
@@ -23,7 +23,7 @@ int main(void) {
     for (int i = 1; i <= 11; ++i) {
         fence();
         uint64_t len = 1 << i;
-        uint64_t reps = 1024*1024 >> i;
+        uint64_t reps = 64*1024 >> i;
 
         mcycle_start = get_mcycle();
 

From c8788e34c2576aac41df4748d752a4124759c873 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 10 Jul 2025 10:21:27 +0200
Subject: [PATCH 29/39] target/sim/verilator: Use define to disable instruction
 tracer

---
 target/sim/verilator/verilator.mk | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index bdaea719..e4e0d9fb 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -21,6 +21,8 @@ VERILATOR_ARGS  ?= -j 0 -Wall $(VERILATOR_WNO) -timescale 1ns/1ps
 VERILATOR_ARGS += -O3 --x-assign fast --x-initial fast --noassert
 # Disable common_cells assertions
 VERILATOR_ARGS += -DASSERTS_OFF
+# Disable CVA6 instruction tracer
+VERILATOR_ARGS += -DCVA6_NO_TRACE
 # multithreading
 VERILATOR_ARGS += --threads $(CHS_VERILATOR_THREADS)
 # C++ Compiler Optimization

From 0ac7b4324744b54364ee2d67928fd82adf7b90cd Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 10 Jul 2025 10:24:55 +0200
Subject: [PATCH 30/39] target/sim/verilator: Work around assignment issues
 using split_var directives

---
 .gitignore                        | 1 +
 hw/cheshire_soc.sv                | 4 ++--
 target/sim/verilator/config.vlt   | 7 +++++++
 target/sim/verilator/verilator.mk | 8 ++++----
 4 files changed, 14 insertions(+), 6 deletions(-)
 create mode 100644 target/sim/verilator/config.vlt

diff --git a/.gitignore b/.gitignore
index 80ef51f9..41a54a3c 100644
--- a/.gitignore
+++ b/.gitignore
@@ -53,6 +53,7 @@ target/sim/verilator/obj_dir/
 target/sim/verilator/*.flist
 target/sim/verilator/*.fst
 target/sim/verilator/*.vlt
+!target/sim/verilator/config.vlt
 target/sim/verilator/*.vcd
 target/sim/verilator/logs/
 target/sim/verilator/trace_hart_*.dasm
diff --git a/hw/cheshire_soc.sv b/hw/cheshire_soc.sv
index b3b62544..b612f448 100644
--- a/hw/cheshire_soc.sv
+++ b/hw/cheshire_soc.sv
@@ -588,8 +588,8 @@ module cheshire_soc import cheshire_pkg::*; #(
   assign intr.intn.bus_err.cores = core_bus_err_intr_comb;
 
   for (genvar i = 0; i < NumIntHarts; i++) begin : gen_cva6_cores
-    axi_cva6_req_t core_out_req, core_ur_req;
-    axi_cva6_rsp_t core_out_rsp, core_ur_rsp;
+    axi_cva6_req_t core_out_req, core_ur_req /*verilator split_var*/;
+    axi_cva6_rsp_t core_out_rsp, core_ur_rsp /*verilator split_var*/;
 
     // CLIC interface
     logic clic_irq_valid, clic_irq_ready;
diff --git a/target/sim/verilator/config.vlt b/target/sim/verilator/config.vlt
new file mode 100644
index 00000000..21d5813b
--- /dev/null
+++ b/target/sim/verilator/config.vlt
@@ -0,0 +1,7 @@
+`verilator_config
+
+// CVA6: avoid wrong runtime results (probably a Verilator bug) from "combinational loops"
+// This can show up in some cases as a core deadlock.
+// Probably this issue: https://github.com/verilator/verilator/issues/5350
+split_var -module "load_unit" -var "req_port_i"
+split_var -module "load_unit" -var "req_port_o"
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index e4e0d9fb..721db9fa 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -43,14 +43,14 @@ VERILATOR_CXX_SRCS = $(CHS_VERILATOR_DIR)/sim/main.cpp \
 	$(RISCV_DBG_DIR)/tb/remote_bitbang/remote_bitbang.c \
 	$(RISCV_DBG_DIR)/tb/remote_bitbang/sim_jtag.c
 
+VERILATOR_CONFIG = $(CHS_VERILATOR_DIR)/config.vlt
+
 $(CHS_VERILATOR_DIR)/cheshire_soc.flist: $(CHS_ROOT)/Bender.yml
 	$(BENDER) script verilator $(CHS_BENDER_RTL_FLAGS) > $@
-	# TODO: Add verilator target for these upstream to avoid patch-in
-	echo '$(shell $(BENDER) path axi)/src/axi_sim_mem.sv' >> $@
 
-$(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist $(VERILATOR_CXX_SRCS)
+$(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper: $(CHS_ROOT)/target/sim/verilator/cheshire_soc.flist $(VERILATOR_CXX_SRCS) $(VERILATOR_CONFIG)
 	+cd $(CHS_VERILATOR_DIR) && $(VERILATOR_PREFIX) $(VERILATOR) $(VERILATOR_ARGS) \
-		-DASSERTS_OFF -f $< $(VERILATOR_CXX_SRCS) \
+		-f $< $(VERILATOR_CXX_SRCS) $(VERILATOR_CONFIG) \
 		--cc --exe --build --top-module cheshire_soc_wrapper
 
 $(CHS_ROOT)/target/sim/verilator/cheshire_soc.vlt: $(CHS_ROOT)/target/sim/verilator/obj_dir/Vcheshire_soc_wrapper

From 239b06e3a9795a128363e781187dbb1fb99e6042 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 10 Jul 2025 10:25:29 +0200
Subject: [PATCH 31/39] target/sim/verilator: Link using clang++

---
 target/sim/verilator/verilator.mk | 13 ++++++++++++-
 1 file changed, 12 insertions(+), 1 deletion(-)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index 721db9fa..dbffd416 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -28,7 +28,18 @@ VERILATOR_ARGS += --threads $(CHS_VERILATOR_THREADS)
 # C++ Compiler Optimization
 VERILATOR_ARGS += -CFLAGS "-O3" -CFLAGS "-march=native" -CFLAGS "-mtune=native"
 # Use Clang (faster simulation than GCC)
-VERILATOR_ARGS += --compiler clang -MAKEFLAGS "CC=clang" -MAKEFLAGS "CXX=clang++"
+VERILATOR_ARGS += --compiler clang -MAKEFLAGS "CC=clang" -MAKEFLAGS "CXX=clang++" -MAKEFLAGS "LINK=clang++"
+
+# Link Time Optimization (LTO)
+# VERILATOR_ARGS += -CFLAGS "-flto" -LDFLAGS "-flto"
+
+# Thread Profile-Guided Optimization (PGO)
+# VERILATOR_ARGS += --prof-pgo
+# VERILATOR_ARGS += profile.vlt
+
+# Compiler Profile-Guided Optimization (PGO)
+# VERILATOR_ARGS += -CFLAGS "-fprofile-generate" -MAKEFLAGS "LINK=clang++" -LDFLAGS "-fprofile-generate"
+# VERILATOR_ARGS += -CFLAGS "-fprofile-use=../default.profdata"
 
 # Profiling
 # generates `gmon.out` that can be processed by `gprof` and then `verilator_profcfunc`

From 4b4b8b567ea9a3608df95438a0b2cabf843f7dd6 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 10 Jul 2025 10:25:47 +0200
Subject: [PATCH 32/39] sw/tests/dma_2d: Insert fence() after DMA copy

---
 sw/tests/dma_2d.spm.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/sw/tests/dma_2d.spm.c b/sw/tests/dma_2d.spm.c
index 1ce1f102..e085a465 100644
--- a/sw/tests/dma_2d.spm.c
+++ b/sw/tests/dma_2d.spm.c
@@ -34,6 +34,7 @@ int main(void) {
     // Issue blocking 2D memcpy (exclude null terminator from source)
     sys_dma_2d_blk_memcpy((uintptr_t)(void *)dst, (uintptr_t)(void *)src, sizeof(src_cached) - 4, 7,
                           1, 4, DMA_CONF_DECOUPLE_NONE);
+    fence();
 
     // Check destination string
     int errors = sizeof(gold);

From 5312cfcc216da5c150f7b87f3a681d67e05d2487 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 10 Jul 2025 10:42:12 +0200
Subject: [PATCH 33/39] target/sim/verilator: Make UART baud rate configurable

---
 target/sim/verilator/src/cheshire_soc_wrapper.sv | 3 ++-
 target/sim/verilator/verilator.mk                | 5 ++++-
 2 files changed, 6 insertions(+), 2 deletions(-)

diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index cd27204a..1a6615f2 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -10,7 +10,8 @@ function automatic cheshire_pkg::cheshire_cfg_t gen_cheshire_cfg();
 endfunction
 
 module cheshire_soc_wrapper # (
-  parameter cheshire_pkg::cheshire_cfg_t DutCfg = gen_cheshire_cfg()
+  parameter cheshire_pkg::cheshire_cfg_t DutCfg       = gen_cheshire_cfg(),
+  parameter int unsigned                 UartBaudRate = 115200
 ) (
   input logic clk_i,
   input logic rtc_i,
diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index dbffd416..b6ea400a 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -11,12 +11,15 @@ RISCV_DBG_DIR = $(shell bender path riscv-dbg)
 VERILATOR_PREFIX ?= oseda
 VERILATOR        ?= verilator
 
-CHS_VERILATOR_THREADS ?= 4
+CHS_VERILATOR_THREADS   ?= 4
+CHS_VERILATOR_UART_BAUD ?= 115200
 
 # Silly Verilator warnings: these are perfectly valid and should not be warnings
 VERILATOR_WNO   = -Wno-fatal -Wno-style \
 	-Wno-BLKANDNBLK -Wno-WIDTHEXPAND -Wno-WIDTHTRUNC -Wno-WIDTHCONCAT -Wno-ASCRANGE
 VERILATOR_ARGS  ?= -j 0 -Wall $(VERILATOR_WNO) -timescale 1ns/1ps
+# UART baud rate
+VERILATOR_ARGS += -GUartBaudRate=$(CHS_VERILATOR_UART_BAUD)
 # Verilation optimizations
 VERILATOR_ARGS += -O3 --x-assign fast --x-initial fast --noassert
 # Disable common_cells assertions

From 22092886c79fb6475b12969a279db25969b1f0be Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Thu, 10 Jul 2025 17:40:31 +0200
Subject: [PATCH 34/39] target/sim/verilator: Prepare fw_payload and DTB
 preloading

---
 Bender.yml                                    |   1 +
 target/sim/verilator/sim/Mem64Master.h        |   2 +
 target/sim/verilator/sim/main.cpp             |  79 +++++++-
 .../sim/verilator/src/cheshire_soc_wrapper.sv |   4 +-
 target/sim/verilator/src/verilator_ram.sv     | 188 ++++++++++++++++++
 5 files changed, 267 insertions(+), 7 deletions(-)
 create mode 100644 target/sim/verilator/src/verilator_ram.sv

diff --git a/Bender.yml b/Bender.yml
index fd5bf3f0..7c0d3689 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -56,6 +56,7 @@ sources:
 
   - target: any(verilator)
     files:
+      - target/sim/verilator/src/verilator_ram.sv
       - target/sim/verilator/src/verilator_uart_rx.sv
       - target/sim/verilator/src/cheshire_soc_wrapper.sv
 
diff --git a/target/sim/verilator/sim/Mem64Master.h b/target/sim/verilator/sim/Mem64Master.h
index 35e6dd7d..564f7357 100644
--- a/target/sim/verilator/sim/Mem64Master.h
+++ b/target/sim/verilator/sim/Mem64Master.h
@@ -131,6 +131,8 @@ class Mem64Master {
 
             if (m_write_request_queue.empty()) {
                 printf("Mem64Master: emptied write queue\n");
+            } else if (m_write_request_queue.size() % 1000 == 0) {
+                printf("Mem64Master: %zu writes remaining\n", m_write_request_queue.size());
             }
         }
 
diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index f3f53c8d..a155f6b3 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -84,7 +84,7 @@ static bool elf_preload_open(const char *filename) {
     return true;
 }
 
-static void elf_preload_write_enqueue() {
+static void elf_preload_write_enqueue(bool is_zsl) {
     long long section_address, section_len;
     size_t num_writes = 0;
 
@@ -94,6 +94,14 @@ static void elf_preload_write_enqueue() {
         char *buf = (char *)calloc(section_len + sizeof(uint64_t), 1);
         read_section_raw(section_address, buf, section_len);
 
+        if (is_zsl) {
+          assert(section_address == 0);
+          section_address = 0x10000000; // SPM start
+          VL_PRINTF("[ELF] ZSL will be loaded at 0x%llx instead of 0x0\n", section_address);
+        } else {
+          assert(section_address != 0);
+        }
+
         for (size_t i = 0; i < section_len; i += sizeof(uint64_t)) {
             mem_master->write(section_address + i, *(uint64_t *)(buf + i));
             num_writes++;
@@ -104,6 +112,7 @@ static void elf_preload_write_enqueue() {
 
     long long entry;
     get_entry(&entry);
+    VL_PRINTF("[ELF] entry point: %p\n", (void*)entry);
     // write entrypoint
     mem_master->write(0x03000000, entry);
     num_writes++;
@@ -114,6 +123,39 @@ static void elf_preload_write_enqueue() {
     VL_PRINTF("[ELF] enqueued %zu memory writes\n", num_writes);
 }
 
+static void bin_preload_write_enqueue(const char* bin_path, uint64_t load_addr) {
+    FILE *fp = fopen(bin_path, "rb");
+    if (!fp) {
+      perror("fopen");
+      exit(1);
+    }
+    fseek(fp, 0, SEEK_END);
+    uint64_t size = ftell(fp);
+    if (size >= 0x200000) size = 0x200000; // HACK: only load first page of fw_payload
+    fseek(fp, 0, SEEK_SET);
+    uint64_t num_words = (size + sizeof(uint64_t) - 1) / sizeof(uint64_t);
+    uint64_t* buf = (uint64_t*)calloc(num_words, sizeof(uint64_t));
+    size_t nread = fread(buf, 1, size, fp);
+    if (nread != size) {
+      VL_PRINTF("[BIN] Error: could not read entire file %s\n", bin_path);
+      exit(1);
+    }
+    fclose(fp);
+
+    size_t num_writes = 0;
+    for (size_t i = 0; i < num_words; i++) {
+      if (buf[i] == 0x0)
+        // skip writing zeros (for speed)
+        continue;
+
+      mem_master->write(load_addr + i * sizeof(uint64_t), buf[i]);
+      num_writes++;
+    }
+
+    free(buf);
+    VL_PRINTF("[BIN] enqueued %zu memory writes (skipped %zu zero words)\n", num_writes, num_words - num_writes);
+}
+
 static void poll_for_exit() {
     static bool request_inflight = false;
     static uint64_t idle_cycles = 0;
@@ -166,16 +208,37 @@ int main(int argc, char** argv) {
     // This needs to be called before you create any model
     contextp->commandArgs(argc, argv);
 
+    // for (int i = 0; i < argc; i++) {
+    //   VL_PRINTF("%s\n", argv[i]);
+    // }
+
     const char *filename_plusarg = contextp->commandArgsPlusMatch("BINARY=");
     if (strlen(filename_plusarg) == 0) {
       VL_PRINTF("Error: no binary specified (+BINARY=...)\n");
       return 1;
     }
-    const char *filename = filename_plusarg + strlen("+BINARY=");
+    const char *filename = strdup(filename_plusarg + strlen("+BINARY="));
     if (!filename || strlen(filename) == 0 || filename[0] != '/') {
       VL_PRINTF("Error: +BINARY requires absolute path\n");
       return 1;
     }
+    VL_PRINTF("[ELF] BINARY: %s\n", filename);
+
+    const char *fw_payload_plusarg = contextp->commandArgsPlusMatch("FW_PAYLOAD=");
+    const char *fw_payload_bin = NULL;
+    if (strlen(fw_payload_plusarg) != 0) {
+      fw_payload_bin = strdup(fw_payload_plusarg + strlen("+FW_PAYLOAD="));
+      VL_PRINTF("[FW] FW_PAYLOAD: %s\n", fw_payload_bin);
+    }
+
+    const char *fw_dtb_plusarg = contextp->commandArgsPlusMatch("FW_DTB=");
+    const char *fw_dtb_bin = NULL;
+    if (strlen(fw_dtb_plusarg) != 0) {
+      fw_dtb_bin = strdup(fw_dtb_plusarg + strlen("+FW_DTB="));
+      VL_PRINTF("[FW] DTB: %s\n", fw_dtb_bin);
+    }
+
+    bool is_firmware = fw_payload_bin != NULL;
 
     // "TOP" will be the hierarchical name of the module
     topp = std::make_unique<Vcheshire_soc_wrapper>(contextp.get(), "TOP");
@@ -245,8 +308,14 @@ int main(int argc, char** argv) {
 
           // TODO: This is determined experimentally.
           // We should rather poll until the SPM has been configured properly.
-          if (cycle == 2000)
-            elf_preload_write_enqueue();
+          if (cycle == 2000) {
+            if (is_firmware) {
+              // preload payloads before the actual ZSL ELF, to avoid premature execution
+              bin_preload_write_enqueue(fw_payload_bin, 0x80000000);
+              bin_preload_write_enqueue(fw_dtb_bin, 0x80800000);
+            }
+            elf_preload_write_enqueue(is_firmware);
+          }
 
           if (cycle > 2000 && !preload_done_cycle && !mem_master->has_write()) {
             preload_done_cycle = cycle;
@@ -256,7 +325,7 @@ int main(int argc, char** argv) {
 
           // I/O
           if (reset_done) {
-            if (preload_done_cycle > 0)
+            if (!is_firmware && preload_done_cycle > 0)
               poll_for_exit();
 #if 0
             jtag_tick_io();
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index 1a6615f2..da1e1781 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -224,13 +224,13 @@ module cheshire_soc_wrapper # (
     dram_mem_addr[0][DramAddrWidth-1:DramAddrWidth-DramWordAddrWidth]
   };
 
-  tc_sram #(
+  verilator_ram #(
     .NumWords  ( NumDramWords  ),
     .DataWidth ( DramDataWidth ),
     .ByteWidth ( 8             ),
     .NumPorts  ( 2             ),
     .Latency   ( 1             )
-  ) i_dram(
+  ) i_dram (
     .clk_i,
     .rst_ni,
     .req_i   ( dram_mem_req       ),
diff --git a/target/sim/verilator/src/verilator_ram.sv b/target/sim/verilator/src/verilator_ram.sv
new file mode 100644
index 00000000..c732df9c
--- /dev/null
+++ b/target/sim/verilator/src/verilator_ram.sv
@@ -0,0 +1,188 @@
+// Copyright (c) 2020 ETH Zurich and University of Bologna.
+// Copyright and related rights are licensed under the Solderpad Hardware
+// License, Version 0.51 (the "License"); you may not use this file except in
+// compliance with the License.  You may obtain a copy of the License at
+// http://solderpad.org/licenses/SHL-0.51. Unless required by applicable law
+// or agreed to in writing, software, hardware and materials distributed under
+// this License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR
+// CONDITIONS OF ANY KIND, either express or implied. See the License for the
+// specific language governing permissions and limitations under the License.
+
+// Author: Wolfgang Roenninger <wroennin@ethz.ch>
+
+// Description: Functional module of a generic SRAM
+//
+// Parameters:
+// - NumWords:    Number of words in the macro. Address width can be calculated with:
+//                `AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1`
+//                The module issues a warning if there is a request on an address which is
+//                not in range.
+// - DataWidth:   Width of the ports `wdata_i` and `rdata_o`.
+// - ByteWidth:   Width of a byte, the byte enable signal `be_i` can be calculated with the
+//                ceiling division `ceil(DataWidth, ByteWidth)`.
+// - NumPorts:    Number of read and write ports. Each is a full port. Ports with a higher
+//                index read and write after the ones with lower indices.
+// - Latency:     Read latency, the read data is available this many cycles after a request.
+// - PrintSimCfg: Prints at the beginning of the simulation a `Hello` message with
+//                the instantiated parameters and signal widths.
+// - ImplKey:     Key by which an instance can refer to a specific implementation (e.g. macro).
+//                May be used to look up additional parameters for implementation (e.g. generator,
+//                line width, muxing) in an external reference, such as a configuration file.
+//
+// Ports:
+// - `clk_i`:   Clock
+// - `rst_ni`:  Asynchronous reset, active low
+// - `req_i`:   Request, active high
+// - `we_i`:    Write request, active high
+// - `addr_i`:  Request address
+// - `wdata_i`: Write data, has to be valid on request
+// - `be_i`:    Byte enable, active high
+// - `rdata_o`: Read data, valid `Latency` cycles after a request with `we_i` low.
+//
+// Behaviour:
+// - Address collision:  When Ports are making a write access onto the same address,
+//                       the write operation will start at the port with the lowest address
+//                       index, each port will overwrite the changes made by the previous ports
+//                       according how the respective `be_i` signal is set.
+// - Read data on write: This implementation will not produce a read data output on the signal
+//                       `rdata_o` when `req_i` and `we_i` are asserted. The output data is stable
+//                       on write requests.
+
+module verilator_ram #(
+  parameter int unsigned NumWords     = 32'd1024, // Number of Words in data array
+  parameter int unsigned DataWidth    = 32'd128,  // Data signal width
+  parameter int unsigned ByteWidth    = 32'd8,    // Width of a data byte
+  parameter int unsigned NumPorts     = 32'd2,    // Number of read and write ports
+  parameter int unsigned Latency      = 32'd1,    // Latency when the read data is available
+  parameter bit          PrintSimCfg  = 1'b0,     // Print configuration
+  parameter              ImplKey      = "none",   // Reference to specific implementation
+  // DEPENDENT PARAMETERS, DO NOT OVERWRITE!
+  parameter int unsigned AddrWidth = (NumWords > 32'd1) ? $clog2(NumWords) : 32'd1,
+  parameter int unsigned BeWidth   = (DataWidth + ByteWidth - 32'd1) / ByteWidth, // ceil_div
+  parameter type         addr_t    = logic [AddrWidth-1:0],
+  parameter type         data_t    = logic [DataWidth-1:0],
+  parameter type         be_t      = logic [BeWidth-1:0]
+) (
+  input  logic                 clk_i,      // Clock
+  input  logic                 rst_ni,     // Asynchronous reset active low
+  // input ports
+  input  logic  [NumPorts-1:0] req_i,      // request
+  input  logic  [NumPorts-1:0] we_i,       // write enable
+  input  addr_t [NumPorts-1:0] addr_i,     // request address
+  input  data_t [NumPorts-1:0] wdata_i,    // write data
+  input  be_t   [NumPorts-1:0] be_i,       // write byte enable
+  // output ports
+  output data_t [NumPorts-1:0] rdata_o     // read data
+);
+
+  // memory array
+  data_t sram [NumWords-1:0];
+  // hold the read address when no read access is made
+  addr_t [NumPorts-1:0] r_addr_q;
+
+  // set the read output if requested
+  // The read data at the highest array index is set combinational.
+  // It gets then delayed for a number of cycles until it gets available at the output at
+  // array index 0.
+
+  // read data output assignment
+  data_t [NumPorts-1:0][Latency-1:0] rdata_q,  rdata_d;
+  if (Latency == 32'd0) begin : gen_no_read_lat
+    for (genvar i = 0; i < NumPorts; i++) begin : gen_port
+      assign rdata_o[i] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]];
+    end
+  end else begin : gen_read_lat
+
+    always_comb begin
+      for (int unsigned i = 0; i < NumPorts; i++) begin
+        rdata_o[i] = rdata_q[i][0];
+        for (int unsigned j = 0; j < (Latency-1); j++) begin
+          rdata_d[i][j] = rdata_q[i][j+1];
+        end
+        rdata_d[i][Latency-1] = (req_i[i] && !we_i[i]) ? sram[addr_i[i]] : sram[r_addr_q[i]];
+      end
+    end
+  end
+
+  // write memory array
+  always_ff @(posedge clk_i or negedge rst_ni) begin
+    if (!rst_ni) begin
+      for (int unsigned i = 0; i < NumWords; i++) begin
+        sram[i] <= '0;
+      end
+      for (int i = 0; i < NumPorts; i++) begin
+        r_addr_q[i] <= {AddrWidth{1'b0}};
+        // initialize the read output register for each port
+        for (int unsigned j = 0; j < Latency; j++) begin
+          rdata_q[i][j] <= '0;
+        end
+      end
+    end else begin
+      // read value latch happens before new data is written to the sram
+      for (int unsigned i = 0; i < NumPorts; i++) begin
+        if (Latency != 0) begin
+          for (int unsigned j = 0; j < Latency; j++) begin
+            rdata_q[i][j] <= rdata_d[i][j];
+          end
+        end
+      end
+      // there is a request for the SRAM, latch the required register
+      for (int unsigned i = 0; i < NumPorts; i++) begin
+        if (req_i[i]) begin
+          if (we_i[i]) begin
+            // update value when write is set at clock
+            for (int unsigned j = 0; j < BeWidth; j++) begin
+              if (be_i[i][j]) begin
+                sram[addr_i[i]][j*ByteWidth+:ByteWidth] <= wdata_i[i][j*ByteWidth+:ByteWidth];
+              end
+            end
+          end else begin
+            // otherwise update read address for subsequent non request cycles
+            r_addr_q[i] <= addr_i[i];
+          end
+        end // if req_i
+      end // for ports
+    end // if !rst_ni
+  end
+
+// Validate parameters.
+// pragma translate_off
+`ifndef VERILATOR
+`ifndef TARGET_SYNTHESIS
+  initial begin: p_assertions
+    assert ($bits(addr_i)  == NumPorts * AddrWidth) else $fatal(1, "AddrWidth problem on `addr_i`");
+    assert ($bits(wdata_i) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `wdata_i`");
+    assert ($bits(be_i)    == NumPorts * BeWidth)   else $fatal(1, "BeWidth   problem on `be_i`"   );
+    assert ($bits(rdata_o) == NumPorts * DataWidth) else $fatal(1, "DataWidth problem on `rdata_o`");
+    assert (NumWords  >= 32'd1) else $fatal(1, "NumWords has to be > 0");
+    assert (DataWidth >= 32'd1) else $fatal(1, "DataWidth has to be > 0");
+    assert (ByteWidth >= 32'd1) else $fatal(1, "ByteWidth has to be > 0");
+    assert (NumPorts  >= 32'd1) else $fatal(1, "The number of ports must be at least 1!");
+  end
+  initial begin: p_sim_hello
+    if (PrintSimCfg) begin
+      $display("#################################################################################");
+      $display("verilator_ram functional instantiated with the configuration:"                    );
+      $display("Instance: %m"                                                                     );
+      $display("Number of ports   (dec): %0d", NumPorts                                           );
+      $display("Number of words   (dec): %0d", NumWords                                           );
+      $display("Address width     (dec): %0d", AddrWidth                                          );
+      $display("Data width        (dec): %0d", DataWidth                                          );
+      $display("Byte width        (dec): %0d", ByteWidth                                          );
+      $display("Byte enable width (dec): %0d", BeWidth                                            );
+      $display("Latency Cycles    (dec): %0d", Latency                                            );
+      $display("Simulation init   (str): %0s", SimInit                                            );
+      $display("#################################################################################");
+    end
+  end
+  for (genvar i = 0; i < NumPorts; i++) begin : gen_assertions
+    assert property ( @(posedge clk_i) disable iff (!rst_ni)
+        (req_i[i] |-> (addr_i[i] < NumWords))) else
+      $warning("Request address %0h not mapped, port %0d, expect random write or read behavior!",
+          addr_i[i], i);
+  end
+
+`endif
+`endif
+// pragma translate_on
+endmodule

From a52c677e4ccac4913c105b7b22f015ad42855a79 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Fri, 11 Jul 2025 12:22:00 +0200
Subject: [PATCH 35/39] target/sim/verilator: Optimize preloading into DRAM
 directly

---
 target/sim/verilator/sim/main.cpp             | 116 +++++++++++-------
 .../sim/verilator/src/cheshire_soc_wrapper.sv |  85 +++++++++----
 2 files changed, 134 insertions(+), 67 deletions(-)

diff --git a/target/sim/verilator/sim/main.cpp b/target/sim/verilator/sim/main.cpp
index a155f6b3..1f2f1170 100644
--- a/target/sim/verilator/sim/main.cpp
+++ b/target/sim/verilator/sim/main.cpp
@@ -1,4 +1,5 @@
 #include <chrono> // timers
+#include <cstdint>
 #include <memory> // std::unique_ptr
 
 #include <verilated.h> // common Verilator routines
@@ -30,7 +31,8 @@ extern "C" {
 
 std::unique_ptr<VerilatedContext> contextp;
 std::unique_ptr<Vcheshire_soc_wrapper> topp;
-std::unique_ptr<Mem64Master> mem_master;
+std::unique_ptr<Mem64Master> slink_master;
+std::unique_ptr<Mem64Master> dram_master;
 bool do_exit = false;
 int  exit_code = 0;
 
@@ -75,6 +77,30 @@ static void handle_uart(char data) {
   }
 }
 
+static size_t write_chunk(uint64_t dst_addr, uint64_t* data, size_t num_words) {
+    assert(dst_addr % sizeof(uint64_t) == 0 && "aligned address");
+    size_t num_writes = 0;
+
+    for (size_t i = 0; i < num_words; i++) {
+        uint64_t word_addr = dst_addr + i * sizeof(uint64_t);
+        if (word_addr >= 0x80000000ULL && word_addr < 0x100000000ULL) {
+            // DRAM
+            if (data[i] == 0)
+                // DRAM is zero-initialized, so skip writing zero words
+                continue;
+            dram_master->write(word_addr, data[i]);
+            num_writes++;
+        } else {
+            slink_master->write(word_addr, data[i]);
+            num_writes++;
+        }
+    }
+
+    VL_PRINTF("[MEM] writing %zu words to %p (skipping %zu zero words)\n",
+        num_writes, (void *)dst_addr, num_words - num_writes);
+    return num_writes;
+}
+
 static bool elf_preload_open(const char *filename) {
     char ret = read_elf(filename);
     if (ret != 0) {
@@ -84,15 +110,16 @@ static bool elf_preload_open(const char *filename) {
     return true;
 }
 
-static void elf_preload_write_enqueue(bool is_zsl) {
+static uint64_t elf_preload_write_enqueue(bool is_zsl) {
     long long section_address, section_len;
     size_t num_writes = 0;
 
     while (get_section(&section_address, &section_len)) {
         VL_PRINTF("[ELF] loading section at 0x%llx (%lld bytes)\n", section_address, section_len);
+        size_t num_words = (section_len + sizeof(uint64_t) - 1) / sizeof(uint64_t); // div ceil
 
-        char *buf = (char *)calloc(section_len + sizeof(uint64_t), 1);
-        read_section_raw(section_address, buf, section_len);
+        uint64_t* buf = (uint64_t*)calloc(num_words, sizeof(uint64_t));
+        read_section_raw(section_address, (char *)buf, section_len);
 
         if (is_zsl) {
           assert(section_address == 0);
@@ -102,25 +129,14 @@ static void elf_preload_write_enqueue(bool is_zsl) {
           assert(section_address != 0);
         }
 
-        for (size_t i = 0; i < section_len; i += sizeof(uint64_t)) {
-            mem_master->write(section_address + i, *(uint64_t *)(buf + i));
-            num_writes++;
-        }
-
+        num_writes += write_chunk(section_address, buf, num_words);
         free(buf);
     }
+    VL_PRINTF("[ELF] enqueued %zu memory writes\n", num_writes);
 
     long long entry;
     get_entry(&entry);
-    VL_PRINTF("[ELF] entry point: %p\n", (void*)entry);
-    // write entrypoint
-    mem_master->write(0x03000000, entry);
-    num_writes++;
-    // set start bit (read by boot ROM)
-    mem_master->write(0x03000008, 2);
-    num_writes++;
-
-    VL_PRINTF("[ELF] enqueued %zu memory writes\n", num_writes);
+    return entry;
 }
 
 static void bin_preload_write_enqueue(const char* bin_path, uint64_t load_addr) {
@@ -131,7 +147,6 @@ static void bin_preload_write_enqueue(const char* bin_path, uint64_t load_addr)
     }
     fseek(fp, 0, SEEK_END);
     uint64_t size = ftell(fp);
-    if (size >= 0x200000) size = 0x200000; // HACK: only load first page of fw_payload
     fseek(fp, 0, SEEK_SET);
     uint64_t num_words = (size + sizeof(uint64_t) - 1) / sizeof(uint64_t);
     uint64_t* buf = (uint64_t*)calloc(num_words, sizeof(uint64_t));
@@ -142,18 +157,16 @@ static void bin_preload_write_enqueue(const char* bin_path, uint64_t load_addr)
     }
     fclose(fp);
 
-    size_t num_writes = 0;
-    for (size_t i = 0; i < num_words; i++) {
-      if (buf[i] == 0x0)
-        // skip writing zeros (for speed)
-        continue;
-
-      mem_master->write(load_addr + i * sizeof(uint64_t), buf[i]);
-      num_writes++;
-    }
-
+    write_chunk(load_addr, buf, num_words);
     free(buf);
-    VL_PRINTF("[BIN] enqueued %zu memory writes (skipped %zu zero words)\n", num_writes, num_words - num_writes);
+}
+
+static void elf_preload_start_enqueue(uint64_t entrypoint_addr) {
+    VL_PRINTF("[ELF] starting execution, entry point %p\n", (void*)entrypoint_addr);
+    // write entrypoint
+    slink_master->write(0x03000000, entrypoint_addr);
+    // set start bit (read by boot ROM)
+    slink_master->write(0x03000008, 2);
 }
 
 static void poll_for_exit() {
@@ -161,7 +174,7 @@ static void poll_for_exit() {
     static uint64_t idle_cycles = 0;
 
     if (request_inflight) {
-      auto maybe_response = mem_master->get_read_response();
+      auto maybe_response = slink_master->get_read_response();
       if (maybe_response) {
         auto data = maybe_response->data;
 
@@ -177,7 +190,7 @@ static void poll_for_exit() {
       idle_cycles++;
 
       if (idle_cycles >= 1000) {
-        mem_master->read(0x03000008);
+        slink_master->read(0x03000008);
         request_inflight = true;
       }
     }
@@ -267,7 +280,7 @@ int main(int argc, char** argv) {
     uint64_t preload_done_cycle = 0;
     double preload_done_time = -1;
 
-    mem_master = std::make_unique<Mem64Master>(
+    slink_master = std::make_unique<Mem64Master>(
         &topp->slink_mem_req_i,
         &topp->slink_mem_addr_i,
         &topp->slink_mem_we_i,
@@ -278,6 +291,19 @@ int main(int argc, char** argv) {
         &topp->slink_mem_rsp_rdata_o
     );
 
+    dram_master = std::make_unique<Mem64Master>(
+        &topp->dram_mem_req_i,
+        &topp->dram_mem_addr_i,
+        &topp->dram_mem_we_i,
+        &topp->dram_mem_wdata_i,
+        &topp->dram_mem_be_i,
+        &topp->dram_mem_gnt_o,
+        &topp->dram_mem_rsp_valid_o,
+        &topp->dram_mem_rsp_rdata_o
+    );
+
+    uint64_t entrypoint_addr = -1;
+
     // ELF preloading
     if (!elf_preload_open(filename))
       return 1;
@@ -291,11 +317,13 @@ int main(int argc, char** argv) {
         if (!topp->clk_i) {
           if (cycle == 1) {
             // Apply Reset
+            VL_PRINTF("[RST] applying reset\n");
             topp->rst_ni = 0;
           }
 
           if (cycle == RST_CYCLES + 1) {
             // Release Reset
+            VL_PRINTF("[RST] releasing reset\n");
             topp->rst_ni = 1;
             reset_done = true;
           }
@@ -312,15 +340,19 @@ int main(int argc, char** argv) {
             if (is_firmware) {
               // preload payloads before the actual ZSL ELF, to avoid premature execution
               bin_preload_write_enqueue(fw_payload_bin, 0x80000000);
-              bin_preload_write_enqueue(fw_dtb_bin, 0x80800000);
+              bin_preload_write_enqueue(fw_dtb_bin,     0x90000000);
             }
-            elf_preload_write_enqueue(is_firmware);
+            entrypoint_addr = elf_preload_write_enqueue(is_firmware);
           }
 
-          if (cycle > 2000 && !preload_done_cycle && !mem_master->has_write()) {
-            preload_done_cycle = cycle;
-            preload_done_time = get_seconds();
-            VL_PRINTF("[ELF] preload complete\n");
+          if (cycle > 2000 && !preload_done_cycle) {
+            if (!slink_master->has_write() && !dram_master->has_write()) {
+              preload_done_cycle = cycle;
+              preload_done_time = get_seconds();
+              VL_PRINTF("[ELF] preload complete\n");
+
+              elf_preload_start_enqueue(entrypoint_addr);
+            }
           }
 
           // I/O
@@ -338,7 +370,8 @@ int main(int argc, char** argv) {
 
         // Monitor Synchronous Outputs: just before @(posedge clk_i)
         if (reset_done && topp->clk_i) {
-          mem_master->handle_before();
+          slink_master->handle_before();
+          dram_master->handle_before();
         }
 
         // Evaluate model
@@ -346,7 +379,8 @@ int main(int argc, char** argv) {
 
         // Apply Synchronous Inputs: just after @(posedge clk_i)
         if (reset_done && topp->clk_i) {
-          mem_master->handle_after();
+          slink_master->handle_after();
+          dram_master->handle_after();
         }
 
 #if VM_TRACE
diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index da1e1781..c6982fa8 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -37,7 +37,17 @@ module cheshire_soc_wrapper # (
   input  logic [DutCfg.AxiDataWidth/8-1:0] slink_mem_be_i,
   output logic                             slink_mem_gnt_o,
   output logic                             slink_mem_rsp_valid_o,
-  output logic [DutCfg.AxiDataWidth-1:0]   slink_mem_rsp_rdata_o
+  output logic [DutCfg.AxiDataWidth-1:0]   slink_mem_rsp_rdata_o,
+
+  // Memory Interface (DRAM)
+  input  logic                             dram_mem_req_i,
+  input  logic [DutCfg.AddrWidth-1:0]      dram_mem_addr_i,
+  input  logic                             dram_mem_we_i,
+  input  logic [DutCfg.AxiDataWidth-1:0]   dram_mem_wdata_i,
+  input  logic [DutCfg.AxiDataWidth/8-1:0] dram_mem_be_i,
+  output logic                             dram_mem_gnt_o,
+  output logic                             dram_mem_rsp_valid_o,
+  output logic [DutCfg.AxiDataWidth-1:0]   dram_mem_rsp_rdata_o
 );
 
   import cheshire_pkg::*;
@@ -178,13 +188,13 @@ module cheshire_soc_wrapper # (
   localparam int unsigned DramAddrWidth     = $clog2(DutCfg.LlcOutRegionEnd - DutCfg.LlcOutRegionStart);
   localparam int unsigned DramDataWidth     = DutCfg.AxiDataWidth;
 
-  logic [1:0]                      dram_mem_req;
-  logic [1:0][DramAddrWidth-1:0]   dram_mem_addr;
-  logic [1:0][DramDataWidth-1:0]   dram_mem_wdata;
-  logic [1:0][DramDataWidth/8-1:0] dram_mem_strb;
-  logic [1:0]                      dram_mem_we;
-  logic [1:0]                      dram_mem_rvalid;
-  logic [1:0][DramDataWidth-1:0]   dram_mem_rdata;
+  logic [2:0]                      dram_mem_req;
+  logic [2:0][DramAddrWidth-1:0]   dram_mem_addr;
+  logic [2:0][DramDataWidth-1:0]   dram_mem_wdata;
+  logic [2:0][DramDataWidth/8-1:0] dram_mem_strb;
+  logic [2:0]                      dram_mem_we;
+  logic [2:0]                      dram_mem_rvalid;
+  logic [2:0][DramDataWidth-1:0]   dram_mem_rdata;
 
   axi_to_mem_split #(
     .axi_req_t    ( axi_llc_req_t       ),
@@ -194,32 +204,55 @@ module cheshire_soc_wrapper # (
     .IdWidth      ( $bits(axi_llc_id_t) ),
     .MemDataWidth ( DramDataWidth       ),
     .BufDepth     ( 1                   ),
-    .HideStrb     ( 1'b1                ),
+    .HideStrb     ( 1'b0                ),
     .OutFifoDepth ( 1                   )
   ) i_dram_axi (
     .clk_i,
     .rst_ni,
-    .test_i       ( 1'b0            ),
-    .busy_o       (                 ),
-    .axi_req_i    ( axi_llc_mst_req ),
-    .axi_resp_o   ( axi_llc_mst_rsp ),
-    .mem_req_o    ( dram_mem_req    ),
-    .mem_gnt_i    ( 2'b11           ),
-    .mem_addr_o   ( dram_mem_addr   ),
-    .mem_wdata_o  ( dram_mem_wdata  ),
-    .mem_strb_o   ( dram_mem_strb   ),
-    .mem_atop_o   (                 ),
-    .mem_we_o     ( dram_mem_we     ),
-    .mem_rvalid_i ( dram_mem_rvalid ),
-    .mem_rdata_i  ( dram_mem_rdata  )
+    .test_i       ( 1'b0                 ),
+    .busy_o       (                      ),
+    .axi_req_i    ( axi_llc_mst_req      ),
+    .axi_resp_o   ( axi_llc_mst_rsp      ),
+    .mem_req_o    ( dram_mem_req[1:0]    ),
+    .mem_gnt_i    ( 2'b11                ),
+    .mem_addr_o   ( dram_mem_addr[1:0]   ),
+    .mem_wdata_o  ( dram_mem_wdata[1:0]  ),
+    .mem_strb_o   ( dram_mem_strb[1:0]   ),
+    .mem_atop_o   (                      ),
+    .mem_we_o     ( dram_mem_we[1:0]     ),
+    .mem_rvalid_i ( dram_mem_rvalid[1:0] ),
+    .mem_rdata_i  ( dram_mem_rdata[1:0]  )
   );
 
+  // direct access port from C++
+  assign dram_mem_req[2]      = dram_mem_req_i;
+  assign dram_mem_addr[2]     = dram_mem_addr_i;
+  assign dram_mem_wdata[2]    = dram_mem_wdata_i;
+  assign dram_mem_strb[2]     = dram_mem_be_i;
+  assign dram_mem_we[2]       = dram_mem_we_i;
+  assign dram_mem_gnt_o       = 1'b1;
+  assign dram_mem_rsp_valid_o = dram_mem_rvalid[2];
+  assign dram_mem_rsp_rdata_o = dram_mem_rdata[2];
+
   localparam int unsigned DramWordAddrWidth = DramAddrWidth - $clog2(DramDataWidth / 8);
   localparam int unsigned NumDramWords      = 1 << DramWordAddrWidth;
 
+  logic [DramAddrWidth-1:0] dram_mem_raddr_q;
+  `FF(dram_mem_raddr_q, dram_mem_addr[0], '0);
+
+  always_ff @(posedge clk_i) begin
+    // if (rst_ni && dram_mem_req[1] && dram_mem_we[1]) begin
+    //   $display("[DRAM] wrote 0x%x to address 0x%x", dram_mem_wdata[1], dram_mem_addr[1]);
+    // end
+    if (rst_ni && dram_mem_rvalid[0]) begin
+      $display("[DRAM] address 0x%x -> data 0x%x", dram_mem_raddr_q, dram_mem_rdata[0]);
+    end
+  end
+
   // Translate byte addresses (from axi_to_mem_split) to word addresses (for tc_sram)
-  logic [1:0][DramWordAddrWidth-1:0] dram_mem_word_addr;
+  logic [2:0][DramWordAddrWidth-1:0] dram_mem_word_addr;
   assign dram_mem_word_addr = {
+    dram_mem_addr[2][DramAddrWidth-1:DramAddrWidth-DramWordAddrWidth],
     dram_mem_addr[1][DramAddrWidth-1:DramAddrWidth-DramWordAddrWidth],
     dram_mem_addr[0][DramAddrWidth-1:DramAddrWidth-DramWordAddrWidth]
   };
@@ -228,7 +261,7 @@ module cheshire_soc_wrapper # (
     .NumWords  ( NumDramWords  ),
     .DataWidth ( DramDataWidth ),
     .ByteWidth ( 8             ),
-    .NumPorts  ( 2             ),
+    .NumPorts  ( 3             ),
     .Latency   ( 1             )
   ) i_dram (
     .clk_i,
@@ -241,8 +274,8 @@ module cheshire_soc_wrapper # (
     .rdata_o ( dram_mem_rdata     )
   );
 
-  logic [1:0] dram_mem_req_q;
-  `FF(dram_mem_req_q, dram_mem_req, 2'b0);
+  logic [2:0] dram_mem_req_q;
+  `FF(dram_mem_req_q, dram_mem_req, 3'b000);
   assign dram_mem_rvalid = dram_mem_req_q;
 
   ////////////

From 002d39a74a0a8ca77eadd12458700a0148fca14a Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Wed, 13 Aug 2025 14:50:08 +0200
Subject: [PATCH 36/39] target/sim/verilator: Re-enable LTO

---
 target/sim/verilator/verilator.mk | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/target/sim/verilator/verilator.mk b/target/sim/verilator/verilator.mk
index b6ea400a..8a3d719b 100644
--- a/target/sim/verilator/verilator.mk
+++ b/target/sim/verilator/verilator.mk
@@ -34,14 +34,14 @@ VERILATOR_ARGS += -CFLAGS "-O3" -CFLAGS "-march=native" -CFLAGS "-mtune=native"
 VERILATOR_ARGS += --compiler clang -MAKEFLAGS "CC=clang" -MAKEFLAGS "CXX=clang++" -MAKEFLAGS "LINK=clang++"
 
 # Link Time Optimization (LTO)
-# VERILATOR_ARGS += -CFLAGS "-flto" -LDFLAGS "-flto"
+VERILATOR_ARGS += -CFLAGS "-flto" -LDFLAGS "-flto"
 
 # Thread Profile-Guided Optimization (PGO)
 # VERILATOR_ARGS += --prof-pgo
 # VERILATOR_ARGS += profile.vlt
 
 # Compiler Profile-Guided Optimization (PGO)
-# VERILATOR_ARGS += -CFLAGS "-fprofile-generate" -MAKEFLAGS "LINK=clang++" -LDFLAGS "-fprofile-generate"
+# VERILATOR_ARGS += -CFLAGS "-fprofile-generate" -CFLAGS "-fprofile-update=atomic" -LDFLAGS "-fprofile-generate" -LDFLAGS "-fprofile-update=atomic"
 # VERILATOR_ARGS += -CFLAGS "-fprofile-use=../default.profdata"
 
 # Profiling

From ed71f20b02393dd998b37c06869457b9f303dd80 Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Wed, 13 Aug 2025 14:50:47 +0200
Subject: [PATCH 37/39] target/sim/verilator: Remove DRAM logging from wrapper

---
 target/sim/verilator/src/cheshire_soc_wrapper.sv | 9 ---------
 1 file changed, 9 deletions(-)

diff --git a/target/sim/verilator/src/cheshire_soc_wrapper.sv b/target/sim/verilator/src/cheshire_soc_wrapper.sv
index c6982fa8..2f28027b 100644
--- a/target/sim/verilator/src/cheshire_soc_wrapper.sv
+++ b/target/sim/verilator/src/cheshire_soc_wrapper.sv
@@ -240,15 +240,6 @@ module cheshire_soc_wrapper # (
   logic [DramAddrWidth-1:0] dram_mem_raddr_q;
   `FF(dram_mem_raddr_q, dram_mem_addr[0], '0);
 
-  always_ff @(posedge clk_i) begin
-    // if (rst_ni && dram_mem_req[1] && dram_mem_we[1]) begin
-    //   $display("[DRAM] wrote 0x%x to address 0x%x", dram_mem_wdata[1], dram_mem_addr[1]);
-    // end
-    if (rst_ni && dram_mem_rvalid[0]) begin
-      $display("[DRAM] address 0x%x -> data 0x%x", dram_mem_raddr_q, dram_mem_rdata[0]);
-    end
-  end
-
   // Translate byte addresses (from axi_to_mem_split) to word addresses (for tc_sram)
   logic [2:0][DramWordAddrWidth-1:0] dram_mem_word_addr;
   assign dram_mem_word_addr = {

From e7a52f226bc27a4dfdee0900a6004129a1565b4d Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 19 Aug 2025 10:09:18 +0200
Subject: [PATCH 38/39] TMP: Overwrite common_cells and cva6

---
 Bender.local | 3 +++
 1 file changed, 3 insertions(+)
 create mode 100644 Bender.local

diff --git a/Bender.local b/Bender.local
new file mode 100644
index 00000000..5583d2a9
--- /dev/null
+++ b/Bender.local
@@ -0,0 +1,3 @@
+overrides:
+  common_cells: { git: "https://github.com/pulp-platform/common_cells.git", rev: master }
+  cva6:         { git: "https://github.com/MaxWipfli/pulp_cva6.git",        rev: verilator_speedup }

From 14dfc64d6f70c512d2f772fd2a7ad452e6359b4b Mon Sep 17 00:00:00 2001
From: Max Wipfli <mwipfli@ethz.ch>
Date: Tue, 19 Aug 2025 10:15:15 +0200
Subject: [PATCH 39/39] TMP: Update Bender.lock

---
 Bender.lock | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/Bender.lock b/Bender.lock
index 6bf3ab46..e86fbb46 100644
--- a/Bender.lock
+++ b/Bender.lock
@@ -85,8 +85,8 @@ packages:
     - common_cells
     - register_interface
   common_cells:
-    revision: 9afda9abb565971649c2aa0985639c096f351171
-    version: 1.38.0
+    revision: b20ad7aba2080b3bb705680e0f70f1fc180ce290
+    version: null
     source:
       Git: https://github.com/pulp-platform/common_cells.git
     dependencies:
@@ -99,10 +99,10 @@ packages:
       Git: https://github.com/pulp-platform/common_verification.git
     dependencies: []
   cva6:
-    revision: 9338c2ca7cf1a47aef54322f89ce867825c3c8d5
+    revision: 2565f6dad38bb5630beac3d0043d9742c55d1ce2
     version: null
     source:
-      Git: https://github.com/pulp-platform/cva6.git
+      Git: https://github.com/MaxWipfli/pulp_cva6.git
     dependencies:
     - axi
     - common_cells